WO1999045911A2 - Universal reed-solomon coder-decoder - Google Patents
Universal reed-solomon coder-decoder Download PDFInfo
- Publication number
- WO1999045911A2 WO1999045911A2 PCT/US1999/005493 US9905493W WO9945911A2 WO 1999045911 A2 WO1999045911 A2 WO 1999045911A2 US 9905493 W US9905493 W US 9905493W WO 9945911 A2 WO9945911 A2 WO 9945911A2
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- error
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1515—Reed-Solomon codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/154—Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2933—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using a block and a convolutional code
- H03M13/2936—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using a block and a convolutional code comprising an outer Reed-Solomon code and an inner convolutional code
Definitions
- Reed-Solomon (RS) coding is a non-binary Bose, Chaudhuri and Hocquenghem (BCH) error correction code. Since each codeword (or a symbol) is represented by a byte (i.e., a fixed length sequence of "0" and " 1 "s) rather than a single bit as in binary BCH coding, and since the decoder can correct an erroneous symbol regardless of how many bits within that symbol are corrupted, RS coding is very powerful against burst errors.
- a Reed-Solomon codec (outer coding) concatenated with a convolutional codec (inner coding) provides the best of both worlds — block coding and convolutional coding.
- a soft-decision Viterbi decoder can be easily constructed to take in unquantized "soft" signals and provide a coding gain of about 2 dB over hard-decision decoding.
- a Viterbi decoder tends to generate burst errors.
- a Reed-Solomon decoder has difficulty performing soft-decision decoding, but can easily correct burst errors that exist at the output of the Viterbi decoder.
- a generating polynomial is also required.
- ⁇ g 0 + g, X + g 2 x 2 + g 3 x 3 + ... + g 2t x 2t
- ⁇ is the primitive element in of the Galois field.
- the present invention relates to a method and apparatus for a universal Reed- Solomon encoder and decoder.
- "Universal" is used herein to indicate that to realize any particular Reed-Solomon coding scheme, modifications to the general codec framework provided by the invention are minimal. Such a universal approach helps to expedite the design process for various Reed-Solomon coding standards.
- an approach to finding error patterns of the present invention uses a modified general form that takes advantage of properties of the generating polynomial g(x).
- n is a number of encoded codewords in the block
- k is a number of information symbols
- t is a number of correctable erroneous symbols
- ⁇ is an element of a Galois field
- r is the initial exponent for ⁇
- each ⁇ r+l is a root of g(x).
- the decoder includes a syndrome computer for computing a series of syndromes from the received codeword polynomial R(x) and an error location polynomial computer for computing an error location polynomial of degree v ⁇ t using the computed syndromes.
- the error location polynomial computer uses an iterative Berelkamp table.
- the decoder further includes means for determining error symbol locations by evaluating the error location polynomial for each element in the Galois field.
- the Reed-Solomon decoder further includes means for correcting errors in each error symbol according to the determined error patterns.
- FIG. 1 is a circuit block diagram of a conventional encoder circuit modified in accordance with the present invention.
- FIG. 2 is a flow diagram in accordance with a decoder embodiment of the present invention.
- FIG. 3 is a flow diagram of operation of a syndrome computer of the decoder embodiment of FIG. 2.
- FIG. 4 is a flow diagram of operation of an error location polynomial computer of the decoder embodiment of FIG. 2.
- FIG. 5 is a flow diagram of an error pattern determination block of the decoder embodiment of FIG. 2.
- each ⁇ r+1 is a root of the generating polynomial g(x).
- a Reed-Solomon coding scheme is completely specified by RS(n,k,t) and g(x). This is the reason that a universal RS codec can be very versatile for various RS coding specifications in different standards. Once the codec framework has been built, only a few changes are needed to yield another RS coding structure.
- any arithmetic operation between two symbols in an RS code can be easily carried out.
- the corresponding bits can be found from another look-up table (denoted as E2V "exponent-to-value" table) and then the two bytes can be operated on by a bit-wise XOR.
- E2V exponent-to-value
- a partial V2E look-up table for GF(256) is given as follows:
- the encoder 100 is the conventional encoder circuit for cyclic codes disclosed in the above-referenced Lin & Costello with modification.
- the encoder 100 is a division circuit that includes multipliers 101 weighted by coefficients g 0 , g ..., g n . k ., , adders 102 and storage devices or registers 110.
- the multipliers 101 each multiply a field element from the Galois field by a coefficient g ; .
- the adders 102 each add two elements from the Galois field.
- the registers 110 each store an element bj from the Galois field.
- Gate_B 122 connects information digits received on input 104 to bus 120.
- Switch 126 toggles between the input information digits on input 104 and parity-check digits stored in storage devices 110.
- the conventional encoder circuit is modified to include Gate_A 124, such that when a shorter generating polynomial is specified, Gate_A 124 is turned off and the remaining coefficients are re-indexed as g 0 , g fashion ..., g n . k . ⁇ .
- parity check digits are the remainder of x n_k u(x)/g(x), where u(x) is the information polynomial
- Step 1 With Gate_B 122 turned on, the k information digits UQ, u,,... u k ., are shifted into the circuit 100 and simultaneously into the communication channel on line 106 with the switch 126 set on for receiving the information digits on input 104.
- the information digits are shifted from the front, i.e., beginning with u k _, and ending with u 0 .
- the (n-k) digits in the registers 110 form the remainder and become the parity-check digits.
- Step 2 Turn off Gate_B 122.
- the switch 126 is set on for the parity check digits.
- Step 3 Shift the parity-check digits out and send them into the communication channel 106.
- each byte contains / bits when the underlying Galois Field is GF(2')- For example, each byte of the codewords is an 8-bit byte when the underlying field is GF(256); each byte of the codewords is a 6-bit byte when the underlying field is GF(64).
- a coded block of codewords of RS( «,&) at the output of the encoder then appears as shown in the following table:
- the received codewords may contains errors. That is, some or all bits in a certain codeword may be wrong, so that such codeword is said to be an erroneous symbol.
- An RS(n,k) code can correct up to t-(n-k)/2 erroneous symbols.
- Decoding is typically performed in five steps: 1) calculating syndromes, which are denoted as S 0 , S,, ... S 2t- ⁇ ; 2) building a Berlekamp table to find an error location polynomial, which is denoted by ⁇ (x); 3) finding the locations of the erroneous symbols; 4) finding the error patterns at those error locations; and 5) correcting the errors.
- FIG. 2 A flow diagram for an embodiment of an RS decoder in accordance with the present invention is shown in FIG. 2.
- the syndrome computer 200 uses the roots ⁇ 1 "1 of the generating polynomial defined in Eq.(la).
- the error symbol location determination block 206 iteratively uses the elements ⁇ 1 to find erroneous symbol locations. The operation of each of these blocks is now described further with reference to FIGs. 2 to 5.
- Block 200 Syndrome Computation
- the received codeword polynomial is given by:
- the syndromes are then given by:
- Block 204 Berlekamp Table for Error Location Polynomial
- the preferred embodiment uses the Berlekamp table as modified by the method disclosed in "Information Theory and Reliable Communication", R. Gallager, John Wiley and Sons, 1968 (hereinafter "Gallager”).
- An error location polynomial ⁇ (x) is obtained in an iterative manner.
- the error location polynomial is:
- ⁇ is the degree of ⁇ ( ⁇ ) (x)
- ⁇ is the i th coefficient of the polynomial ⁇ ( ⁇ ) (x) and is represented in terms of the exponent of the primitive element .
- d p and ⁇ (p) (x) are the discrepancy and error location polynomial of the p th row, respectively.
- the values d p , ⁇ (p) (x) and ⁇ -p are determined by following the procedures developed by Gallager.
- the second term in Eq.(9) is defined as Remedy (x), i.e.,
- the iteration continues until all the syndromes have been used.
- the iteration index "mu” therefore ranges from 0, 1, 2, ... 2t-l (maximum).
- the final form of the error location polynomial obtained at the end of the iterations can be represented as:
- v is the degree of the error location polynomial and v ⁇ t.
- the steps of each iteration for the Berlekamp table carried out in block 204 (FIG. 2) for finding the error location polynomial are shown in the block diagram of FIG. 4.
- the discrepancy is computed using ⁇ (x) and the new syndrome S f .
- Remedy(x) is computed using the discrepancy result, d p , and ⁇ (p) (x).
- the result for ⁇ ( ⁇ ) (x) is assigned to Temp(x) in block 406 and ⁇ ( ⁇ ) (x) is updated by adding Remedy(x) in block 408.
- a comparison is made between 2-l ⁇ and mu. If 2-1 ⁇ is less than or equal to mu, then the parameters in block 414 are updated and assigned. If 2i ⁇ is greater than mu, then the expression ⁇ -p is only updated in block 412.
- a helpful way to further understand the above procedure is to step through an example adapted from Lin & Costello. Consider a triple-error-correcting RS code with symbols from GF(2 4 ). The syndromes are then:
- the intermediate result ⁇ (5) (x) is different.
- the determination of the error location polynomial in block 204 only depends on the algebra of the Galois field. It does not depend on how the generating polynomial is defined. Thus, for various standards such as DVB and INTELSAT, this step of building the Berlekamp table is identical, that is, no hardware redesign is required.
- Block 206 Error Symbol Location Determination
- the operation in the error symbol location determination block is a trial-and- error process.
- the error pattern at each error location can be determined.
- the error pattern formula is a modified general form based on equation (6.35) disclosed in Lin & Costello.
- this modified general form for determining the error pattern at each error location is universally applicable for arbitrary ⁇ , r specified in the aforementioned generating polynomial. This is significant in that it enables the decoding of arbitrary Reed- Solomon codes generated by the generating polynomial g(x) given in Eq.(la) using a common hardware structure.
- FIG. 5 a flow diagram of the steps used in block 210 (FIG. 2) for finding the error pattern for the error locations is shown.
- the error evaluator polynomial Z(x) is computed using the coefficients of the error location polynomial ⁇ (x) from block 204 (FIG. 2) and syndromes from block 200 (FIG. 2).
- elements ⁇ are raised to certain powers corresponding to the error locations.
- the error pattern at a particular error location is computed using Eq.(14).
- the errors can be corrected simply by flipping the errored bits in each error symbol. This then provides the original codeword that was transmitted.
- an encoding/decoding algorithm of the present invention has been disclosed herein which can be used to design Reed-Solomon codecs to meet various industry specifications such as the DVB and INTELSAT standards as well as emerging cable modem standards.
- the universal RS coder/decoder framework is provided in such a way that a user only needs to specify four parameters to configure and define the RS coding scheme, and a coder/decoder can be readily available with a minimum amount of modification of such a universal codec.
- the algorithm further employs two lookup tables to expedite addition and multiplication operations.
Abstract
Description
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Priority Applications (1)
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AU31852/99A AU3185299A (en) | 1998-03-12 | 1999-03-12 | Universal reed-solomon coder-decoder |
Applications Claiming Priority (2)
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US7774098P | 1998-03-12 | 1998-03-12 | |
US60/077,740 | 1998-03-12 |
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WO1999045911A2 true WO1999045911A2 (en) | 1999-09-16 |
WO1999045911A9 WO1999045911A9 (en) | 2000-01-20 |
WO1999045911A3 WO1999045911A3 (en) | 2000-04-06 |
WO1999045911A8 WO1999045911A8 (en) | 2000-05-18 |
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PCT/US1999/005493 WO1999045911A2 (en) | 1998-03-12 | 1999-03-12 | Universal reed-solomon coder-decoder |
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WO (1) | WO1999045911A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1017177A1 (en) * | 1998-12-30 | 2000-07-05 | Texas Instruments Incorporated | Configurable Reed-Solomon encoder/decoder |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989002123A1 (en) * | 1987-08-24 | 1989-03-09 | Digital Equipment Corporation | High bandwidth reed-solomon encoding, decoding and error correcting circuit |
-
1999
- 1999-03-12 AU AU31852/99A patent/AU3185299A/en not_active Abandoned
- 1999-03-12 WO PCT/US1999/005493 patent/WO1999045911A2/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989002123A1 (en) * | 1987-08-24 | 1989-03-09 | Digital Equipment Corporation | High bandwidth reed-solomon encoding, decoding and error correcting circuit |
Non-Patent Citations (2)
Title |
---|
BLAHUT R.E.: "Theory and practice of error control codes" 1983 , ADDISON-WESLEY PUBLISHING COMPANY , ENGLAND XP002130500 page 184, paragraph 7.5.2 * |
INTERLANDO J C ET AL: "On the decoding of Reed-Solomon and BCH codes over integer residue rings" IEEE TRANSACTIONS ON INFORMATION THEORY, MAY 1997, IEEE, USA, vol. 43, no. 3, pages 1013-1021, XP002130499 ISSN: 0018-9448 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1017177A1 (en) * | 1998-12-30 | 2000-07-05 | Texas Instruments Incorporated | Configurable Reed-Solomon encoder/decoder |
US6385751B1 (en) | 1998-12-30 | 2002-05-07 | Texas Instruments Incorporated | Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder |
Also Published As
Publication number | Publication date |
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WO1999045911A3 (en) | 2000-04-06 |
WO1999045911A9 (en) | 2000-01-20 |
AU3185299A (en) | 1999-09-27 |
WO1999045911A8 (en) | 2000-05-18 |
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