WO1999045674A1 - Automatic encoding/decoding system - Google Patents
Automatic encoding/decoding system Download PDFInfo
- Publication number
- WO1999045674A1 WO1999045674A1 PCT/JP1998/000883 JP9800883W WO9945674A1 WO 1999045674 A1 WO1999045674 A1 WO 1999045674A1 JP 9800883 W JP9800883 W JP 9800883W WO 9945674 A1 WO9945674 A1 WO 9945674A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- discrete time
- encrypted data
- chaotic
- encryption
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/34—Encoding or coding, e.g. Huffman coding or error correction
Definitions
- the present invention relates to an automatic encryption / decryption system for protecting data.
- the present invention has been made in view of the above-mentioned current situation of encryption and decryption, and has as its object to realize an automatic decryption that can efficiently perform decryption from an arbitrary position while eliminating useless operations.
- An object of the present invention is to provide an encryption / decryption system.
- the present inventors have conducted intensive research and have succeeded in using the immediately preceding encrypted data as an initial value to generate a pseudo-random number in order, as an initial value. Found that only one pseudo-random number was needed, and completed a cryptosystem that could be decrypted at any time.
- they after further intensive research, they have introduced a differential structure into a functional system, and have completed an industrially extremely effective cryptosystem that functions without sharing the initial values.
- a first embodiment of the present invention provides an automatic encryption / decryption system that encrypts plaintext data using pseudo-random numbers and decrypts the encrypted data into plaintext data.
- a first pseudo-random number generating means for generating a pseudo-random number to be used for encrypting the next plain data based on the immediately-encrypted data already encrypted when encrypting a plurality of plain text data;
- Encryption means for encrypting the next plaintext data into encrypted data using the pseudorandom number generated by the first pseudorandom number generation means
- a second pseudo-random number generating means for generating a pseudo-random number at the time of decryption based on the first encrypted data of the continuous encrypted data when decrypting the plurality of encrypted data;
- Decryption means for decrypting the next successive cipher data into plaintext data using the pseudorandom number generated by the second pseudorandom number generation means;
- the second embodiment of the present invention provides a method in which 0 ⁇ xc (t) +1 is an internal retained value of the cipher at the discrete time t, and 0.5-yc (t) ⁇ 0. 5 is the sum of inputs to the chaotic cipher at discrete time t, 0 ⁇ zc (t) ⁇ 1 is the output of the chaotic cipher at discrete time t, and 0 ⁇ s (t) ⁇ 1 is the input at discrete time t.
- 0 ⁇ ⁇ 1 is the attenuation constant of the internal holding value X c (t)
- 0 ⁇ 3 ⁇ 0.5 is the gain constant from the sum yc (t) of inputs to the output zc (t), 0 ⁇ 7 ⁇ 0.5 as a threshold for the internal holding value xc (t), and 0 ⁇ e ⁇ 1 as a coupling constant that determines the intensity of chaotic modulation.
- X c (t + 1) (1- ⁇ ) ⁇ ⁇ c (t) + (1-a) z c (t) ⁇ + ⁇ s (t)
- Encryption means for encrypting the plaintext data into encrypted data based on
- 0 ⁇ d (t) ⁇ 1 is the internal held value of the chaotic decoder at discrete time t
- 1 0.5 ⁇ yd (t) ⁇ 0.5 is the sum of inputs to the chaotic decoder at discrete time t
- 0 Let ⁇ zd (t) ⁇ 1 be the output of the chaotic decoder at discrete time t, and 0 * s (t) * 1 be the decoded signal at discrete time t.
- ⁇ s (t) [xc (t + 1)-xd (t + 1)-(1 ⁇ ) a ⁇ xc (t)-xd (t) ⁇ ] ⁇ ⁇
- Decryption means for decrypting the encrypted data based on
- An automatic encryption / decryption system having the following features.
- FIG. 1 is a block diagram showing the configuration of an embodiment of the encryption system according to the present invention.
- FIG. 2 is a block diagram showing a configuration of an embodiment of the decoding system according to the present invention.
- FIG. 3 is an explanatory diagram of the encryption processing according to the embodiment of the present invention.
- FIG. 4 is an explanatory diagram of the decoding process according to the embodiment of the present invention.
- FIG. 5 is an explanatory diagram of application of the embodiment of the present invention to a personal computer.
- 1, 16, and 20 are subtractors
- 2, 6, 15, 17, 17, 22, 24, and 2 7 is a multiplier
- 3, 18, 25, 26 is an adder
- 5 23 is a function operator
- 0, 1, 1 and 2 are registers
- Reference numerals 14 and 28 denote delay circuits
- reference numerals 29, 30, 30, 31, 32 and 33 denote registers.
- the output terminal of the multiplier 27 connected to the input terminal of the system is connected to one input terminal of the adder 26
- the output terminal of the adder 26 is connected to the output terminal of the system and the input terminal of the delay circuit 28, and the output terminal of the delay circuit 28 is connected to the inverting input terminal of the subtractor 21 and one input of the multiplier 24.
- the output terminal of the multiplier 24 is connected to one input terminal of the adder 25.
- the output terminal of the subtracter 21 is connected to one input terminal of the multiplier 22, and the output terminal of the multiplier 22 is connected to one input terminal of the function operator 23.
- the output terminal of the adder 25 is connected to the other input terminal of the adder 25, and the output terminal of the adder 25 is connected to the other input terminal of the adder 26.
- Register 31 is connected to the non-inverting input terminal of subtracter 21
- register 32 is connected to the other input terminal of multiplier 22
- register 33 is connected to the other input terminal of function calculator 23.
- Register 30 is connected to the other input terminal of 24, and register 29 is connected to the other input terminal of multiplier 27, respectively.
- 0 ⁇ xc (t) ⁇ 1 is set to an internally held value at discrete time t
- 0.5 ⁇ yc (t) to 0.5 is set to a chaotic cipher at discrete time t.
- 0, zc (t) x 1 is the output of the chaotic cipher at discrete time t, 0 x s (: t) x 1 is the input signal at discrete time t, and 0 ⁇ « ⁇ 1 is the internal
- the damping constant of the holding value c (t), 0 x / 3 x 0.5 is the gain constant from the input sum yc (t) to the output zc (t), 0 ⁇ 7 x 0.5 is the internal holding value xc ( t), where 0 ⁇ £ ⁇ 1 is a coupling constant that determines the intensity of chaotic modulation.
- c (t + 1) (1- ⁇ ) ⁇ c (t) + (1-) z c (t) ⁇ + ⁇ s
- the expression (3) is executed by the subtractor 21, the expression (9) is executed by the multiplier 22 and the function calculator 23, and the expression (8) is executed by the multiplier 24.27. , Performed by adders 25, 26.
- the internal value is sequentially updated by the above equations (3) and (9).
- the current internal value is subtracted from the value of the register 31 by the subtracter 21, multiplied by the value of the register 32 by the multiplier 22, and sent to the function calculator 23.
- the output of the function operation unit 23 is sent to an adder 25, which is added to the current internal value multiplied by the value of the register 30 by a multiplier 24 and sent to an adder 26.
- This signal is the signal that disturbs the original signal and encrypts it.
- This signal is added by the adder 26 to the original signal multiplied by the value of the register 29 by the multiplier 27. In this way, the encryption is obtained. This is also the new internal value.
- the multiplier 27 can be completed by a shift operation unit, and needless to say, it can be configured at high speed and at low cost. .
- the input terminals of the system are connected to one input terminal of the subtractor 1, the input terminal of the delay circuit 13 and the non-inverting human terminal of the subtractor 20.
- the output terminal of the subtractor 20 is connected to one input terminal of the multiplier 15, and the output terminal of the multiplier 5 is connected to the output terminal of the system.
- the output terminal is connected to one input terminal of the multiplier 6, and
- the output terminal 6 is connected to one input terminal of the function calculator 5, and the output terminal of the function calculator 5 is connected to one input terminal of the adder 3.
- the output terminal of the adder 3 is connected to the input terminal of the delay circuit 13, the output terminal of the delay circuit 13 is connected to one input terminal of the multiplier 2, and the output terminal of the multiplier 2 Is connected to the other input terminal of the adder 3.
- the output terminal of the delay circuit 13 is also connected to the non-inverting input terminal of the subtractor 16, and the output terminal of the subtracter 16 is connected to one input terminal of the multiplier 17.
- the output terminal of the multiplier 17 is connected to one input terminal of the adder 18, and the other input terminal of the adder 18 is connected to the output terminal of the adder 3.
- the output terminal of the adder 18 is connected to the inverting input terminal of the subtractor 20, and the output terminal of the adder 20 is connected to one input terminal of the adder 15 as described above.
- Register 10 is connected to the inverting input terminal of subtracter 1
- register 11 is connected to the other input terminal of multiplier 6
- register 12 is connected to the other input terminal of function calculator 5, and the other input terminal of multiplier 2 is connected.
- the register 8b is connected to the terminal
- the register 8a is connected to the other input terminal of the multiplier 17, and the register 7 is connected to the other input terminal of the multiplier 1.5.
- 0 ⁇ xd (t) ⁇ 1 is the internal holding value of the power decoder at the discrete time t
- 0.5 ⁇ yd (t) ⁇ 0.5 is the discrete time.
- Equations (10), (11), and (13) are converted to the following equations (14) to (16) for convenience in decoding by the decoding system in FIG. rewrite.
- the subtractor 1 executes the equation (1 2), and the arithmetic unit 2 and the adder
- the constants of the respective expressions are given in registers 7 to 12. It is used to use the data before the delay circuits 13 and 14.
- the initial values d 0 and c 0 are used for the first decoding process, respectively.
- c 0 is the first data of the ciphertext.
- the multiplier 15 can execute the shift operation if ⁇ is set to a power of two, and it goes without saying that the processing time can be reduced.
- FIGS. 1 and 2 Some of the encryption circuits and the decryption circuits shown in FIGS. 1 and 2 can be used in common. When a device having both functions is to be manufactured, the cost can be reduced by using them in common. In the case of a single function, an ASIC with both functions can be used.
- Figure 3 shows the process of encrypting three pieces of data. Pseudorandom numbers are added by the process (b) using the first data of the data sequence (a) to be encrypted and an optional initial value (c). The first encrypted data is obtained. For the second encrypted data, the process (b) works using the second data of the data sequence (a) and the first encrypted data given instead of the initial value, and the second encrypted data is obtained. .
- Figure 4 shows how the encrypted data sequence (d) can be decrypted to obtain a decrypted data sequence (f) by the process (e) of removing pseudorandom numbers.
- this process is formulated using an equation. Assuming that the data sequence to be encrypted is s, the random data used for encryption 1 is ⁇ , the parameter indicating the degree of encryption is ⁇ , and the encrypted data sequence is X, the encryption process is as follows: Can be indicated by
- the initial value is also used for decryption by incorporating a chaotic dynamical system consisting of independent initial conditions in the encryption process and the decryption process. Not automatic encryption ⁇ Decryption system is obtained.
- data to be encrypted is transmitted from the personal computer 34 to the encrypting device 35 using the USB, which is a general-purpose I / 0 port, as shown in FIG.
- the encryption device 35 encrypts the data by a built-in electronic circuit, and sends the obtained encryption back to the personal computer using USB.
- the plaintext may be sent to the user, and the ciphertext may be sent back as a whole, or may be sent and received for each data. If an initial value is needed for the first decryption, the data should be prepended to the ciphertext. The reason is that the value is used for decoding the first data. With this configuration, it is not necessary to specially treat the decoding process of the first decoding in the decoding algorithm. In other words, decrypting the subsequent data can be obtained by processing the data that connects the first data of two consecutive data as the initial value as encryption.
- data at an arbitrary position in a data string can be instantaneously decoded using two pieces of data without using unnecessary operations, and particularly, large capacity. It has a great effect on data, for example, image data.
- a chaotic dynamical system when used, a dynamical system consisting of independent initial conditions is used for encryption and decryption, so that there is no need to know any initial values. Is obtained.
- ⁇ an image in which the original image has been disturbed can be obtained by arbitrarily controlling the degree of “disturbance”. This is particularly effective in cases where the service is provided with a different password.
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- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
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- Storage Device Security (AREA)
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP1998/000883 WO1999045674A1 (en) | 1998-03-04 | 1998-03-04 | Automatic encoding/decoding system |
CN98813971.5A CN1291391A (en) | 1998-03-04 | 1998-03-04 | Automatic encoding/decoding system |
Applications Claiming Priority (1)
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PCT/JP1998/000883 WO1999045674A1 (en) | 1998-03-04 | 1998-03-04 | Automatic encoding/decoding system |
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WO1999045674A1 true WO1999045674A1 (en) | 1999-09-10 |
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PCT/JP1998/000883 WO1999045674A1 (en) | 1998-03-04 | 1998-03-04 | Automatic encoding/decoding system |
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WO (1) | WO1999045674A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015197854A (en) * | 2014-04-02 | 2015-11-09 | 能美防災株式会社 | Inspection support system and inspection support device |
-
1998
- 1998-03-04 CN CN98813971.5A patent/CN1291391A/en active Pending
- 1998-03-04 WO PCT/JP1998/000883 patent/WO1999045674A1/en active Application Filing
Non-Patent Citations (3)
Title |
---|
IKENO S, OYAMA K: "MODERN CYPTOGRAPHY THEORY", MODERN CRYPTOGRAPHY THEORY, XX, XX, 1 January 1989 (1989-01-01), XX, pages 67 - 76, XP002920974 * |
NAGASHIMA Y.: "TRY TO MAKE A CHAOS GENERATOR.", INTERFACE., ELECTROCHEMICAL SOCIETY., US, vol. 20., no. 02., 1 January 1994 (1994-01-01), US, pages 168 - 177., XP002920975, ISSN: 1064-8208 * |
PAPADIMITRIOU S., BEZERIANOS A., BOUNTIS T.: "SECURE COMMUNICATION WITH CHAOTIC SYSTEMS OF DIFFERENCE EQUATIONS.", IEEE TRANSACTIONS ON COMPUTERS., IEEE SERVICE CENTER, LOS ALAMITOS, CA., US, vol. 46., no. 01., 1 January 1997 (1997-01-01), US, pages 27 - 38., XP000642241, ISSN: 0018-9340, DOI: 10.1109/12.559800 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015197854A (en) * | 2014-04-02 | 2015-11-09 | 能美防災株式会社 | Inspection support system and inspection support device |
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CN1291391A (en) | 2001-04-11 |
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