WO1999044223A3 - Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing - Google Patents

Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing Download PDF

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Publication number
WO1999044223A3
WO1999044223A3 PCT/US1999/004375 US9904375W WO9944223A3 WO 1999044223 A3 WO1999044223 A3 WO 1999044223A3 US 9904375 W US9904375 W US 9904375W WO 9944223 A3 WO9944223 A3 WO 9944223A3
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WO
WIPO (PCT)
Prior art keywords
kinks
layer
threshold
corner
active devices
Prior art date
Application number
PCT/US1999/004375
Other languages
French (fr)
Other versions
WO1999044223A2 (en
Inventor
Michael F Chisholm
David D Daniel
Brynne K Chisholm
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Publication of WO1999044223A2 publication Critical patent/WO1999044223A2/en
Publication of WO1999044223A3 publication Critical patent/WO1999044223A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

A shallow trench isolation (STI) process active devices avoids creating corner effects and sub-threshold kinks by a process which does not include additional steps or additional processing time. A predetermined material, such as polysilicon or doped polysilicon, is selected for a mask layer. The material reacts to form the same isolation material to a greater depth than the isolation material formed as a passivating trench layer at a silicon substrate, under simultaneous thermochemical reaction conditions. A relatively thicker protective layer is formed by the simultaneous reacition, and the protective layer projects the upper corners of the trench layer from removal when a padding layer is removed. The end result is a rounded protective corner which prevents the corner effect and the undesirable sub-threshold voltage-current non-linearities or kinks.
PCT/US1999/004375 1998-02-27 1999-02-26 Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing WO1999044223A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3289598A 1998-02-27 1998-02-27
US09/032,895 1998-02-27

Publications (2)

Publication Number Publication Date
WO1999044223A2 WO1999044223A2 (en) 1999-09-02
WO1999044223A3 true WO1999044223A3 (en) 1999-10-28

Family

ID=21867430

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/004375 WO1999044223A2 (en) 1998-02-27 1999-02-26 Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing

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WO (1) WO1999044223A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7514336B2 (en) 2005-12-29 2009-04-07 Agere Systems Inc. Robust shallow trench isolation structures and a method for forming shallow trench isolation structures

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254557A (en) * 1988-08-18 1990-02-23 Seiko Epson Corp Semiconductor device
JPH0445558A (en) * 1990-06-12 1992-02-14 Mitsubishi Electric Corp Element isolation structure and its formation method
EP0660391A2 (en) * 1993-12-20 1995-06-28 Kabushiki Kaisha Toshiba Semiconductor device with a trench isolation region and method of manufacturing the same
EP0736897A2 (en) * 1995-04-04 1996-10-09 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
WO1998012742A1 (en) * 1996-09-17 1998-03-26 Hitachi, Ltd. Semiconductor device and method of fabricating the same
US5763932A (en) * 1996-11-12 1998-06-09 Micron Technology, Inc. Isolation regions and methods of forming isolation regions
US5837612A (en) * 1997-08-01 1998-11-17 Motorola, Inc. Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254557A (en) * 1988-08-18 1990-02-23 Seiko Epson Corp Semiconductor device
JPH0445558A (en) * 1990-06-12 1992-02-14 Mitsubishi Electric Corp Element isolation structure and its formation method
EP0660391A2 (en) * 1993-12-20 1995-06-28 Kabushiki Kaisha Toshiba Semiconductor device with a trench isolation region and method of manufacturing the same
EP0736897A2 (en) * 1995-04-04 1996-10-09 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
WO1998012742A1 (en) * 1996-09-17 1998-03-26 Hitachi, Ltd. Semiconductor device and method of fabricating the same
US5763932A (en) * 1996-11-12 1998-06-09 Micron Technology, Inc. Isolation regions and methods of forming isolation regions
US5837612A (en) * 1997-08-01 1998-11-17 Motorola, Inc. Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 218 (E - 0925) 9 May 1990 (1990-05-09) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 233 (E - 1209) 28 May 1992 (1992-05-28) *

Also Published As

Publication number Publication date
WO1999044223A2 (en) 1999-09-02

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