WO1999040614A2 - Method of manufacturing a semiconductor device with linearly doping profile - Google Patents
Method of manufacturing a semiconductor device with linearly doping profile Download PDFInfo
- Publication number
- WO1999040614A2 WO1999040614A2 PCT/IB1999/000159 IB9900159W WO9940614A2 WO 1999040614 A2 WO1999040614 A2 WO 1999040614A2 IB 9900159 W IB9900159 W IB 9900159W WO 9940614 A2 WO9940614 A2 WO 9940614A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- doping
- mask
- openings
- profile
- drift region
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000012777 electrically insulating material Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 21
- 230000015556 catabolic process Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
Definitions
- the invention relates to a method of manufacturing a semiconductor device whereby a doping is provided in a semiconductor body through openings in a mask provided above a surface of the semiconductor body, whereupon a diffusion step is carried out such that the doping concentration in the semiconductor body rises in accordance with a desired profile in a lateral direction parallel to the surface.
- Such a method is known inter alia from the patent US-A 5,300,448.
- This describes a high-voltage transistor of the lateral DMOS type (LDMOS) in a comparatively thin silicon layer, provided on a buried oxide layer which covers the surface of a silicon crystal.
- LDMOS lateral DMOS type
- the drift region of the transistor is given a doping profile in which the doping concentration increases linearly from the source to the drain.
- the manufacture of this doping profile is achieved by means of a doping mask provided with openings whose diameters increase in a direction from the source to the drain and which are situated at a substantially constant pitch.
- the desired linear doping profile is formed by means of a diffusion step at high temperature and of long duration.
- the invention has for its object in general to provide a doping method whereby a smoother doping profile can be obtained than by the known method.
- the invention further has for its object to provide a semiconductor device for use at high voltages wherein degradation owing to local peaks in the electric field strength is avoided as much as possible.
- a method of the kind described in the opening paragraph is for this purpose characterized in that a mask is used for obtaining said profile whose pitch between openings becomes smaller in said lateral direction at least within part of the doping profile. It was found from experiments that peaks in the concentration in the eventual doping profile are at least substantially avoided, and thus also peaks in the electric field distribution.
- a major embodiment of a method according to the invention is characterized in that a doping profile is formed which changes gradually between a minimum doping concentration at one side and a maximum doping concentration at an opposed, second side, for which purpose a doping mask is used with a first partial region corresponding to a portion of the doping profile in which the doping concentration is lower than half the difference between the maximum value and the minimum value, while at least the openings in the first partial region of the doping mask have at least substantially equal widths and are situated at variable distances from one another, seen in the direction of the doping profile.
- the openings in the first partial region may be manufactured so as to have the smallest dimensions which are possible in the process used, so that it is possible to adjust the local concentration over a wide range of doping concentrations by means of the concentration of mask openings.
- a further embodiment of a method according to the invention, whereby the concentration is adjusted by means of the density of mask openings also for higher doping concentrations is characterized in that a second partial region has openings of varying widths, openings situated next to one another being separated from one another by portions of the mask material of at least substantially equal widths.
- the masked portions between the mask openings in the second partial region are provided so as to have the smallest dimensions which are possible in the process.
- the invention may be used to advantage in various types of semiconductor devices for obtaining a doping profile adapted to the specific device. Special advantages are obtained in the formation of the drift regions in high- voltage transistors.
- a preferred embodiment of a method according to the invention is characterized in that the transistor is of the lateral DMOS type, with a source zone, a drain zone, and a drift region of a first conductivity type and a back-gate region of the opposed, second conductivity type situated between the source zone and the drift region, the doping concentration in the drift region increasing in the direction from the source zone to the drain zone.
- the transistor may be formed in a surface layer of a first conductivity type which merges via a pn junction into a subjacent region or substrate of the second conductivity type.
- the drift region is preferably given a doping profile in which the concentration rises in the direction from the source to the drain proportionally to the square root of the distance.
- An embodiment in which the doping profile rises linearly with this distance is characterized in that the semiconductor body is formed by a silicon layer which is provided on a substrate of electrically insulating material.
- Fig. 1 is a cross-sectional view of an LDMOS transistor in the SOI technology, manufactured by a method according to the invention
- Fig. 2 is a cross-sectional view of this device during its manufacture
- Fig. 3 shows the doping profile obtained in the drift region of this device through ion implantation during manufacture
- Fig. 4 shows the doping profile obtained after diffusion.
- LDMOST high-voltage lateral, doubly diffused MOS transistor
- the invention is also applicable to other high-voltage elements such as high-voltage diodes or transistors of the LIGBT type (lateral insulated gate bipolar transistors).
- the transistor shown in Fig. 1 is constructed in the SOI technology (silicon on insulator) and comprises a comparatively thin silicon layer 1 on a substrate 2 of electrically insulating material.
- the substrate 2 is formed by a layer of silicon oxide which covers the surface of a subjacent silicon body 3.
- the silicon layer 1 has a thickness, for example, of between 0.2 and 0.5 ⁇ ; the oxide layer 2 has a thickness, for example, of 3.0 ⁇ m.
- the invention is obviously not limited to these values, but alternative values may be chosen in dependence on specific circumstances.
- Other circuit elements may be provided in the silicon body 3, if so desired, for example an integrated circuit.
- the transistor in this example is of the n-channel type and comprises an n-type source zone 4, a p-type back-gate region 5, and an n-type drain zone 6.
- the gate 7 is provided above the back-gate region 5 in which the channel of the transistor is defined, and is insulated from this channel by gate oxide 8.
- the gate 7 is made of doped polycrystalline silicon (poly), as is usual, but it may also be manufactured from an alternative suitable conducting material.
- the entire assembly is coated with an oxide layer 10 in which contact windows are provided at the areas of the source and drain zones and the gate.
- the source zone 4 is electrically connected to the p-type back-gate region 5 at the side facing away from the gate 7 by means of the metal contact 9 which short-circuits the pn junction between the two regions.
- the gate 7 and the drain zone 6 are connected to respective metal contacts 11 and 12.
- the contacts 9, 11 and 12 may be made, for example, of Al.
- the back-gate region 5 and the drain zone 6 are separated from one another by an interposed high-ohmic region 13 which forms a drift region of the transistor in which a depletion region can be formed during operation in the case of a high voltage between the source 4 and the drain 6.
- the drift region is of the n-type in this example, but in an alternative embodiment it may also be of the p-type.
- the breakdown voltage of the transistor is determined inter alia by the length and the doping concentration of the drift region. As is indicated in the cited US patent 5,300,448, a substantial improvement in the breakdown voltage can be obtained in that the drift region is given a doping profile in which the concentration rises linearly from the source to the drain.
- the profile is manufactured through the use of a doping mask which has openings with diameters which become greater in a predetermined manner from the source to the drain. It was found in practice that, although fairly smooth doping profiles can be obtained by the known method, nevertheless fluctuations often arise in the electric field which may cause impact ionization and hot-carrier degradation, so that the quality of the device may be impaired during operation. This disadvantage is at least substantially avoided through the use of a doping method according to the invention which leads to less strong fluctuations in the doping profile and thus in the electric field. Fig.
- the device shows the device in cross-section during its manufacture, with a doping mask 15 comprising a photoresist layer, in which openings 16, 18 are formed in a usual manner, being provided on the surface of the silicon layer 1 which is covered by a temporary oxide layer 14. It is noted that the drawing shows only the drift region 13 of the silicon layer 1.
- the mask 15 comprises two regions, i.e. the region to the left of the line 17 where the average doping concentration is lower than 50% of the maximum doping concentration, and the region to the right of the line 17 where the average doping concentration is higher than 50% of the maximum concentration.
- the first region of the mask comprises openings 16 which have equal or at least substantially equal dimensions and which are arranged with mutual interspacings which decrease from the left to the right.
- the openings 16 are preferably given dimensions which are the minimum dimensions in the process used, which renders it possible to choose the density of openings as favorably as possible.
- the diameter of the openings 16 is approximately 1.5 ⁇ m.
- the pitch between the openings 16 decreases from left to right from approximately 10 ⁇ m adjacent the back-gate region 5 to approximately 1.5 ⁇ m adjacent the line 17.
- the mask is provided with openings 18 which show an increasing diameter from left to right and which are mutually separated by interposed portions of the mask which have a fixed width, for example the smallest dimension possible in the process.
- the width of these mask portions is, for example, 1.5 ⁇ m.
- the dimensions of the openings 18 rise from the line 17, for example, in accordance with the progression 1.5 ⁇ m, 2 ⁇ m, 3 ⁇ m, ... etc.
- the silicon layer 1 is doped through the openings 16, 18 in the mask 15 with an n-type dopant, for example P ions which are provided in the layer 1 by implantation.
- the implantation dose is chosen to lie, for example, between 1*10 13 and 2*10 13 P ions per cm 2 . Given a thickness of the silicon layer 1 of approximately 0.3 ⁇ m, this will lead to a doping concentration of between 3.5* and 7*10 17 P atoms per cm 3 , neglecting possible dopant loss into oxide layers. In stead of P, of course, also As ions could be used. However P is preferred because of its higher diffusivity.
- Fig. 3 shows the doping concentration after the implantation step in the form of the heights of the columns 19. The horizontal axis in the drawing indicates the position in the silicon layer (in ⁇ m).
- the mask 15 is removed after the implantation, and the device is subjected to a diffusion step of long duration, for example at 1100 °C during 36 hours. Local peaks in the doping concentration are at least substantially smoothed out by this diffusion step, and a practically linear doping profile is obtained as shown in Fig. 4.
- the device may be subjected to further necessary process steps which are known per se for making the back-gate region, the source and drain zones, the gate oxide with the gate, the oxide layer 10, and the metal contacts. Reference is made to the cited US-A 5,300,448 for a more detailed description of these process steps.
- the doping profile is comparatively smooth, the electric fields in the drift region are comparatively weak, which leads to a considerable reduction in the degree of impact ionization, and thus to an improvement in the robustness of the transistor.
- This advantage may obviously also be obtained in high-voltage elements other than transistors, such as diodes or LIGBTs.
- the transistor is constructed in the SOI technology (silicon on insulator), in which a linear doping profile is desired.
- a doping profile is desired in which the concentration rises in accordance with the square root of the distance in other embodiments, in which the transistor is provided at the surface of a monocrystalline silicon substrate, and where the drift region is electrically insulated from the substrate by a cut-off pn junction.
- Such a doping profile may also be advantageously obtained through the use of a method according to the invention.
- the invention is not limited to the embodiment described above, but that many more variations are possible to those skilled in the art within the scope of the invention.
- the conductivity types of the example as described may be reversed.
- other dielectric layers such as silicon layers of different materials instead of oxide layers.
- a semiconductor body of SiC can be used.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019997009231A KR100582106B1 (en) | 1998-02-09 | 1999-01-28 | Method of manufacturing a semiconductor device |
EP99900604A EP0974158B1 (en) | 1998-02-09 | 1999-01-28 | Method of manufacturing a semiconductor device |
DE69942186T DE69942186D1 (en) | 1998-02-09 | 1999-01-28 | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT |
JP54018299A JP4634546B2 (en) | 1998-02-09 | 1999-01-28 | Manufacturing method of semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98200396.4 | 1998-02-09 | ||
EP98200396 | 1998-02-09 |
Publications (2)
Publication Number | Publication Date |
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WO1999040614A2 true WO1999040614A2 (en) | 1999-08-12 |
WO1999040614A3 WO1999040614A3 (en) | 1999-11-04 |
Family
ID=8233373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1999/000159 WO1999040614A2 (en) | 1998-02-09 | 1999-01-28 | Method of manufacturing a semiconductor device with linearly doping profile |
Country Status (6)
Country | Link |
---|---|
US (1) | US6376289B1 (en) |
EP (1) | EP0974158B1 (en) |
JP (1) | JP4634546B2 (en) |
KR (1) | KR100582106B1 (en) |
DE (1) | DE69942186D1 (en) |
WO (1) | WO1999040614A2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000031776A2 (en) * | 1998-11-25 | 2000-06-02 | Koninklijke Philips Electronics N.V. | Lateral thin-film silicon-on-insulator (soi) device having multiple doping profile slopes in the drift region |
WO2001061735A2 (en) * | 2000-02-15 | 2001-08-23 | Infineon Technologies Ag | Implantation mask for high energy ion implantation |
KR100409093B1 (en) * | 2001-07-12 | 2003-12-11 | 주식회사 엘리아테크 | A high voltage device and method of wiring metal on it |
US7518169B2 (en) | 2002-10-31 | 2009-04-14 | Infineon Technologies Ag | MOS-transistor on SOI substrate with source via |
FR2977072A1 (en) * | 2011-06-27 | 2012-12-28 | St Microelectronics Crolles 2 | Method for doping silicon substrate, involves annealing semiconductor substrate to obtain doped zone extending below and on both sides of stud and having approximately homogeneous concentration of doping agents |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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SE526207C2 (en) * | 2003-07-18 | 2005-07-26 | Infineon Technologies Ag | Ldmos transistor device, integrated circuit and manufacturing method thereof |
KR100598035B1 (en) * | 2004-02-24 | 2006-07-07 | 삼성전자주식회사 | Manufacturing method of charge transfer image element |
CN100369264C (en) * | 2005-08-26 | 2008-02-13 | 东南大学 | Three-dimensional multi-gate high-voltage N type transverse double-diffused metal-oxide semiconductor device |
CN100369265C (en) * | 2005-08-26 | 2008-02-13 | 东南大学 | Three-dimensional multi-gate high-voltage P type transverse double-diffused metal-oxide semiconductor device |
US20100117153A1 (en) * | 2008-11-07 | 2010-05-13 | Honeywell International Inc. | High voltage soi cmos device and method of manufacture |
JP2014192278A (en) * | 2013-03-27 | 2014-10-06 | New Japan Radio Co Ltd | Semiconductor device manufacturing method |
JP2015008184A (en) * | 2013-06-25 | 2015-01-15 | 株式会社 日立パワーデバイス | Semiconductor device |
CN104882476B (en) * | 2015-05-25 | 2018-09-25 | 上海先进半导体制造股份有限公司 | Transversal I GBT and preparation method thereof |
WO2018075238A1 (en) * | 2016-10-21 | 2018-04-26 | Sunpower Corporation | Solar cell emitter region fabrication apparatus |
EP3407385B1 (en) | 2017-05-23 | 2024-03-13 | NXP USA, Inc. | Semiconductor device suitable for electrostatic discharge (esd) protection |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0497427A2 (en) * | 1991-02-01 | 1992-08-05 | Koninklijke Philips Electronics N.V. | Semiconductor device for high voltage application and method of making the same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0380575A (en) * | 1989-08-23 | 1991-04-05 | Fujitsu Ltd | Manufacture of semiconductor device |
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1999
- 1999-01-28 JP JP54018299A patent/JP4634546B2/en not_active Expired - Fee Related
- 1999-01-28 DE DE69942186T patent/DE69942186D1/en not_active Expired - Lifetime
- 1999-01-28 WO PCT/IB1999/000159 patent/WO1999040614A2/en active IP Right Grant
- 1999-01-28 EP EP99900604A patent/EP0974158B1/en not_active Expired - Lifetime
- 1999-01-28 KR KR1019997009231A patent/KR100582106B1/en not_active IP Right Cessation
- 1999-02-05 US US09/246,664 patent/US6376289B1/en not_active Expired - Lifetime
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EP0497427A2 (en) * | 1991-02-01 | 1992-08-05 | Koninklijke Philips Electronics N.V. | Semiconductor device for high voltage application and method of making the same |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000031776A2 (en) * | 1998-11-25 | 2000-06-02 | Koninklijke Philips Electronics N.V. | Lateral thin-film silicon-on-insulator (soi) device having multiple doping profile slopes in the drift region |
WO2000031776A3 (en) * | 1998-11-25 | 2000-09-08 | Koninkl Philips Electronics Nv | Lateral thin-film silicon-on-insulator (soi) device having multiple doping profile slopes in the drift region |
WO2001061735A2 (en) * | 2000-02-15 | 2001-08-23 | Infineon Technologies Ag | Implantation mask for high energy ion implantation |
WO2001061735A3 (en) * | 2000-02-15 | 2002-07-18 | Infineon Technologies Ag | Implantation mask for high energy ion implantation |
KR100409093B1 (en) * | 2001-07-12 | 2003-12-11 | 주식회사 엘리아테크 | A high voltage device and method of wiring metal on it |
US7518169B2 (en) | 2002-10-31 | 2009-04-14 | Infineon Technologies Ag | MOS-transistor on SOI substrate with source via |
DE10250832B4 (en) * | 2002-10-31 | 2010-02-11 | Infineon Technologies Ag | MOS transistor on SOI substrate with source via and method for making such a transistor |
FR2977072A1 (en) * | 2011-06-27 | 2012-12-28 | St Microelectronics Crolles 2 | Method for doping silicon substrate, involves annealing semiconductor substrate to obtain doped zone extending below and on both sides of stud and having approximately homogeneous concentration of doping agents |
Also Published As
Publication number | Publication date |
---|---|
KR100582106B1 (en) | 2006-05-23 |
DE69942186D1 (en) | 2010-05-12 |
KR20010006152A (en) | 2001-01-26 |
US6376289B1 (en) | 2002-04-23 |
EP0974158B1 (en) | 2010-03-31 |
WO1999040614A3 (en) | 1999-11-04 |
JP4634546B2 (en) | 2011-02-16 |
EP0974158A2 (en) | 2000-01-26 |
JP2001522538A (en) | 2001-11-13 |
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