WO1999037083A3 - Affine transformation means and method of affine transformation - Google Patents

Affine transformation means and method of affine transformation Download PDF

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Publication number
WO1999037083A3
WO1999037083A3 PCT/RU1998/000403 RU9800403W WO9937083A3 WO 1999037083 A3 WO1999037083 A3 WO 1999037083A3 RU 9800403 W RU9800403 W RU 9800403W WO 9937083 A3 WO9937083 A3 WO 9937083A3
Authority
WO
WIPO (PCT)
Prior art keywords
affine transformation
transforming
transformation means
simplification
flexibility
Prior art date
Application number
PCT/RU1998/000403
Other languages
French (fr)
Other versions
WO1999037083A2 (en
Inventor
Boris Nikolayevich Vilkov
Alexander Roger Deas
Igor Anatolievich Abrossimov
Oleg Anatolievich Pliss
Original Assignee
Boris Nikolayevich Vilkov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to AU36318/99A priority Critical patent/AU3631899A/en
Application filed by Boris Nikolayevich Vilkov filed Critical Boris Nikolayevich Vilkov
Priority to CA002312126A priority patent/CA2312126A1/en
Priority to EP98967039A priority patent/EP1033029B1/en
Priority to JP2000540668A priority patent/JP2002510108A/en
Priority to DE69806501T priority patent/DE69806501T2/en
Publication of WO1999037083A2 publication Critical patent/WO1999037083A2/en
Publication of WO1999037083A3 publication Critical patent/WO1999037083A3/en
Priority to JP11341420A priority patent/JP2000231511A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Image Processing (AREA)

Abstract

A transformation means for transforming memory cell addresses between different memory device topologies providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach which allows the use of a wide spectrum of mapping classes and simplification of the transforming procedure.
PCT/RU1998/000403 1997-11-28 1998-11-30 Affine transformation means and method of affine transformation WO1999037083A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU36318/99A AU3631899A (en) 1997-11-28 1998-02-28 Affine transformation means and method of affine transformation
CA002312126A CA2312126A1 (en) 1997-11-28 1998-11-30 Affine transformation means and method of affine transformation
EP98967039A EP1033029B1 (en) 1997-11-28 1998-11-30 Affine transformation means and method of affine transformation
JP2000540668A JP2002510108A (en) 1997-11-28 1998-11-30 Affine transformation means and affine transformation method
DE69806501T DE69806501T2 (en) 1997-11-28 1998-11-30 DEVICE AND METHOD FOR AFFINE TRANSFORMATION
JP11341420A JP2000231511A (en) 1998-11-30 1999-11-30 Affine transforming means and its method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9725066.6A GB9725066D0 (en) 1997-11-28 1997-11-28 Address transformation means
GB9725066.6 1997-11-28

Publications (2)

Publication Number Publication Date
WO1999037083A2 WO1999037083A2 (en) 1999-07-22
WO1999037083A3 true WO1999037083A3 (en) 1999-10-28

Family

ID=10822706

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU1998/000403 WO1999037083A2 (en) 1997-11-28 1998-11-30 Affine transformation means and method of affine transformation

Country Status (7)

Country Link
EP (1) EP1033029B1 (en)
JP (1) JP2002510108A (en)
AU (1) AU3631899A (en)
CA (1) CA2312126A1 (en)
DE (1) DE69806501T2 (en)
GB (1) GB9725066D0 (en)
WO (1) WO1999037083A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2341014A1 (en) * 1998-08-19 2000-03-02 Alexander Roger Deas A system and method for defining transforms of memory device addresses
JP2009529756A (en) * 2006-03-13 2009-08-20 ヴェリジー（シンガポール） プライベート リミテッド Test data format conversion
CN109144419A (en) * 2018-08-20 2019-01-04 浪潮电子信息产业股份有限公司 A kind of solid state hard disk memory read-write method and system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485474A (en) * 1988-02-25 1996-01-16 The President And Fellows Of Harvard College Scheme for information dispersal and reconstruction

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485474A (en) * 1988-02-25 1996-01-16 The President And Fellows Of Harvard College Scheme for information dispersal and reconstruction

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KIRSCHNER N: "AN INTERACTIVE DESCRAMBLER PROGRAM FOR RAMS WITH REDUNDANCY", QUALITY PRODUCTIVITY PROFIT, PHILADELPHIA, 15 - 18 NOVEMBER 1982, no. SYMP. 1982, 1 November 1982 (1982-11-01), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 252 - 257, XP000746188 *

Also Published As

Publication number Publication date
DE69806501D1 (en) 2002-08-14
DE69806501T2 (en) 2003-02-27
EP1033029B1 (en) 2002-07-10
EP1033029A2 (en) 2000-09-06
JP2002510108A (en) 2002-04-02
WO1999037083A2 (en) 1999-07-22
GB9725066D0 (en) 1998-01-28
CA2312126A1 (en) 1999-07-22
AU3631899A (en) 1999-08-02

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