WO1999021326A2 - Optimisation de ressources dans un systeme multiprocesseurs pour reseau a commutation par paquets - Google Patents

Optimisation de ressources dans un systeme multiprocesseurs pour reseau a commutation par paquets Download PDF

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Publication number
WO1999021326A2
WO1999021326A2 PCT/FI1998/000816 FI9800816W WO9921326A2 WO 1999021326 A2 WO1999021326 A2 WO 1999021326A2 FI 9800816 W FI9800816 W FI 9800816W WO 9921326 A2 WO9921326 A2 WO 9921326A2
Authority
WO
WIPO (PCT)
Prior art keywords
queue
packets
elements
processor
connection
Prior art date
Application number
PCT/FI1998/000816
Other languages
English (en)
Finnish (fi)
Other versions
WO1999021326A3 (fr
Inventor
Jari Korhonen
Jyri Suvanen
Matti LEHTIMÄKI
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Priority to AU95439/98A priority Critical patent/AU9543998A/en
Publication of WO1999021326A2 publication Critical patent/WO1999021326A2/fr
Publication of WO1999021326A3 publication Critical patent/WO1999021326A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Definitions

  • the invention relates to serving packet switched connections, pref- erably ATM connections, in a multiprocessor system, and particularly to optimizing resource allocation in such a system.
  • the invention further relates to an SAR circuit employed in such a system.
  • a packet switched network information is transmitted in packets comprising at least a header part and a payload part.
  • the length of the packets is 53 bytes.
  • a five- byte header indicates with which connection the packet in question is associated.
  • Figure 1 shows five connections C A to C E .
  • a terminal using ATM connections is typically a workstation, a personal computer or the like wherein one efficient processor PROC1 processes the ATM connections.
  • the ATM terminal equipment comprises an SAR circuit (Segmentation And Re-assembly) SAR which receives ATM packets and writes them to a queue Q1 located in a memory, from which queue the processor retrieves them on a first in, first out principle (FIFO).
  • SAR circuit Segmentation And Re-assembly
  • one common SAR circuit shared by all processors serves all processors sharing a common queue.
  • the elements of the queue are formed in an unarranged manner from packets which belong to all C A to C E .
  • the processors spend much time searching the queue Q1 only for elements which belong to them.
  • to write to a shared queue would be difficult for the processors.
  • there are as many queues as there are processors but the SAR circuit is still a shared one the processors still waste their time searching the unarranged queues only for elements which belong to them.
  • An object of the invention is thus to provide a method and equipment implementing the method so as to solve the above problems. More specifically, the object of the invention is to enable resources to be more efficiently utilized in a multiprocessor system which serves several connections.
  • the objects of the invention can be achieved by a method, an arrangement and an SAR circuit characterized by what is said in the independent claims. The preferred embodiments of the invention are disclosed in the dependent claims.
  • the invention is based on the idea of forming a separate queue for each telecommunication connection to be served in a memory space of an SAR circuit, and conveying to each queue substantially only queue elements formed from packets which belong to the respective telecommunication connection.
  • substantially only means that only queue elements formed from packets of a corresponding telecommunication connection (but not of other connections) are transmitted via each queue.
  • processor configuration instructions and status information may be transmitted via the queue.
  • this configuring means that the processor is informed at which memory address the queues associated with the connections and served by it can be found.
  • all queues and processors share a common SAR circuit.
  • Each queue can in practice be implemented as a ring buffer pair or a linked list.
  • the SAR circuit places in each queue only packets which belong to the connection corresponding to it. If a processor serves several connections, the processor also processes several queues.
  • An advantage of the method and the system of the invention is that the processors do not have to spend much time arranging the queues, and the equipment becomes readily scalable for large numbers of connections and processors. Avoiding redundant processing also reduces power consumption.
  • the memory capacity required by the queues is reduced since no need exists to store in any queue packets which will not be processed.
  • a shared SAR circuit is fitted for several processors, which reduces the number of components and the price of the system. The invention thus enables several processors to be connected behind a shared SAR circuit.
  • FIG. 2 shows how several connections are served by several processors in accordance with the invention.
  • a shared SAR circuit arranges packets which belong to all connections C A to C E into queues Q1 to Q2 on the basis of their header in such a manner that a separate queue is formed in the memory space of the SAR circuit for each connection C A to C E .
  • the SAR circuit places in each queue Q1 to Qn only packets which belong to a corresponding connection C A to C E .
  • the queues Q1 to Qn can be provided in a shared physical memory. A problem is then presented, however, by collisions caused by several processors simultaneously writing in the same memory. Even if the queue of each processor was located in a separate storage area, the processor would be compelled to use the same data and/or address bus simultaneously.
  • the queues Q1 to Qn can be simple ring buffer pairs in which the writing element (the SAR circuit or the processor) maintains the write address of a next location, rewrites the packet to this address and increments the write address.
  • the reading element (the processor or the SAR circuit, correspondingly) reads the packet from the read address of the location to be read next and increments this address.
  • a situation in which the same processor serves several connections is shown in connection with a second processor of Figure 2.
  • the processor PROC2 reads from and writes to two queues Q2 ⁇ and Q2 2 .
  • a separate queue is provided for each connection C A to C E , however.
  • the SAR circuit can be configured to divide the payload of one ATM cell into two packets to a corresponding queue Q1 to Qn.
  • the SAR circuit can be configured to form each packet of the queue from the payload part of several ATM cells.
  • the queues Q1 to Qn can be implemented as ring buffers, for example.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Cette invention a trait à une technique, à un dispositif et à un circuit à segmentation et réassemblage permettant à plusieurs processeurs (PROC1-PROCn) de prendre en charge plusieurs connexion de télécommunication à commutation par paquets (CA-CE). Un processeur est sélectionné dans la pluralité de processeurs (PROC1-PROCn) pour chaque connexion de télécommunication (CA-CE) à prendre en charge. Sur chacune de ces connexions (CA-CE) une information est transmise en paquets à partir desquels sont constitués des éléments (A-E) d'au moins une file d'attente (Q1-Qn). Une file d'attente distincte (Q1-Qn) est constituée pour chaque connexion de télécommunication (CA-CE) à prendre en charge. Le circuit susmentionné ne transporte que des éléments de file d'attente (A-E) formés à partir des paquets de la connexion de télécommunication respective (CA-CE) via chaque file vers le processeur correspondant (PROC1-PROCn).
PCT/FI1998/000816 1997-10-21 1998-10-20 Optimisation de ressources dans un systeme multiprocesseurs pour reseau a commutation par paquets WO1999021326A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU95439/98A AU9543998A (en) 1997-10-21 1998-10-20 Resource optimization in a multiprocessor system for a packet network

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI974020A FI974020A0 (fi) 1997-10-21 1997-10-21 Optimering av resurser i ett paketnaetsflerprocessorsystem
FI974020 1997-10-21

Publications (2)

Publication Number Publication Date
WO1999021326A2 true WO1999021326A2 (fr) 1999-04-29
WO1999021326A3 WO1999021326A3 (fr) 1999-07-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1998/000816 WO1999021326A2 (fr) 1997-10-21 1998-10-20 Optimisation de ressources dans un systeme multiprocesseurs pour reseau a commutation par paquets

Country Status (3)

Country Link
AU (1) AU9543998A (fr)
FI (1) FI974020A0 (fr)
WO (1) WO1999021326A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1326475A1 (fr) * 2001-12-21 2003-07-09 Agere Systems Inc. Procédé et dispositif pour exécuter plusieurs fonctions en utilisant plusieurs dispositifs de réassemblage des packets et plusieurs mémoires

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414702A (en) * 1992-10-20 1995-05-09 Kabushiki Kaisha Toshiba Packet disassembler for use in a control unit of an asynchronous switching system
US5428609A (en) * 1994-01-03 1995-06-27 At&T Corp. STM-to-ATM converters
EP0763915A2 (fr) * 1995-09-18 1997-03-19 Kabushiki Kaisha Toshiba Dispositif et méthode de transfert de paquets, appropriés pour un grand nombre de portes d'entrée
WO1997025803A1 (fr) * 1996-01-11 1997-07-17 Cisco Systems, Inc. Procede et appareil d'attribution dynamique de tampons dans un reseau numerique de telecommunications
WO1997025831A1 (fr) * 1996-01-11 1997-07-17 Cisco Systems, Inc. Mise en file d'attente et prise en charge de trames par voie dans le sens de sortie d'un reseau de telecommunications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414702A (en) * 1992-10-20 1995-05-09 Kabushiki Kaisha Toshiba Packet disassembler for use in a control unit of an asynchronous switching system
US5428609A (en) * 1994-01-03 1995-06-27 At&T Corp. STM-to-ATM converters
EP0763915A2 (fr) * 1995-09-18 1997-03-19 Kabushiki Kaisha Toshiba Dispositif et méthode de transfert de paquets, appropriés pour un grand nombre de portes d'entrée
WO1997025803A1 (fr) * 1996-01-11 1997-07-17 Cisco Systems, Inc. Procede et appareil d'attribution dynamique de tampons dans un reseau numerique de telecommunications
WO1997025831A1 (fr) * 1996-01-11 1997-07-17 Cisco Systems, Inc. Mise en file d'attente et prise en charge de trames par voie dans le sens de sortie d'un reseau de telecommunications

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1326475A1 (fr) * 2001-12-21 2003-07-09 Agere Systems Inc. Procédé et dispositif pour exécuter plusieurs fonctions en utilisant plusieurs dispositifs de réassemblage des packets et plusieurs mémoires
US8782287B2 (en) 2001-12-21 2014-07-15 Agere Systems Llc Methods and apparatus for using multiple reassembly memories for performing multiple functions

Also Published As

Publication number Publication date
FI974020A0 (fi) 1997-10-21
WO1999021326A3 (fr) 1999-07-29
AU9543998A (en) 1999-05-10

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