WO1999020006A2

WO1999020006A2 - Single-chip audio circuits, methods, and systems using the same

Info

Publication number: WO1999020006A2
Application number: PCT/US1998/020898
Authority: WO
Inventors: Ronald D. Malcolm, Jr.; Jeff Klaas; Mark Gentry; Phillip Matthews
Original assignee: Crystal Semiconductor Corp.
Priority date: 1997-10-14
Filing date: 1998-10-01
Publication date: 1999-04-22
Also published as: AU9785498A; WO1999020006A3

Abstract

A single chip audio system (100) includes a bus interface (101), digital to analog converters (110), an analog mixer (115), and anolog spatial enhancement circuitry (7500). Digital to analog converters (110) convert digital audio data received through bus interface (101) into analog signals. Analog mixer (115) mixes signals received from digital to analog converters (110) with an analog signal received from an external source. Analog spatial enhancement circuitry (7500) enhances first and second mixed analog signals output from analog mixer (115).

Description

SINGLE-CHIP AUDIO CIRCUITS, METHODS, AND SYSTEMS USING THE SAME BACKGROUND OF THE INVENTION

The present invention relates in general to digital data processing and in particular to single-chip audio circuits, methods, and systems using the same.

DESCRIPTION OF THE RELATED ART The ability to process audio information has become increasingly important in the personal computer (PC) environment. Among other things, audio is important in many multimedia applications, such as gaming and telecommunications. Audio functionality is therefore typically available on most conventional PCs, either in the form of an add-on audio board or as a standard feature provided on the motherboard itself. In fact, PC users increasingly expect not only audio functionality but high quality sound capability.

The key components in most digital audio information processing systems convert input analog audio information into a digital format for processing processor, support sample rate conversion, SoundBlaster compatibility, wavetable synthesis, or DirectSound acceleration. convert outgoing signals from digital to analog format for eventual audible output to the user, and mix analog and/or digital data streams. In conventional systems, these functions must be provided through multiple chip solutions which make board design and fabrication more complex and expensive.

Thus, to meet the demands of increasingly sophisticated computer users, the need has arisen for new circuits and methods for implementing single-chip audio systems and systems using the same. Among other things, such circuits and methods should provide for the implementation of systems for use with high quality sound systems and should support the latest sound processing standards and game designs.

SUMMARY OF THE INVENTION

A single chip audio system includes a bus interface, digital to analog converters, analog mixer, and analog spatial enhancement circuitry. Digital to analog converters convert digital audio data received through bus interface into analog signals. The Analog mixer mixes signals received from digital to analog converters with an analog signal received from an external source.

Analog spatial enhancement circuitry enhances first and second mixed analog signals output from analog mixer. The principles of the present invention substantially meet the demand of increasingly sophisticated computer users for audio subsystems which produce high quality sound. Additionally, the application of the principles of the present invention allows for the provision of such features as stereo full-duplex coding/decoding, CD differential input, mono microphone input, a headphone output, as well as digital connections to a companion audio controller, as desired. BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGURE 1 A is a diagram of an audio codec according to the principles of the present invention;

FIGURE IB is a diagram of an information processing system employing the audio codec of FIGURE 1A; FIGURE 2 is a diagram providing a general overview of the bus structure and principle registers of the codec in FIGURE 1A;

FIGURE 3 is a functional block diagram of the codec microcontroller core;

FIGURE 4 is a diagram of the microcontroller memory map;

FIGURE 5 is a diagram of the mapping of the program RAM space: FIGURE 6 is a diagram of the microcontroller External RAM data definition;

FIGURE 7 is a diagram illustrating the timing of a Request/Grant handshake mechanism;

FIGURE 8 is a diagram of the bitfields of Port 3 Bit Definitions;

FIGURE 9 is a diagram providing an overview of the circuitry supporting a Plug & Play (PnP) interface to an external ISA bus; FIGURE 10 is a diagram emphasizing the configuration/interface logic for a PnP compatible device;

FIGURE 10B is a diagram illustrating the typical functional elements of an LFSR device, including a series of storage/shift elements and logic;

FIGURE 10C is a diagram of the LSFR checksum circuitry; FIGURE 1 1 is a diagram illustrating Plug and Play operating states and corresponding commands; FIGURE 12A is a diagram of the bitfields of the Plug & Play Address-Register at microcontroller Address 0x10;

FIGURE 12B is a diagram of the bitfields of the Plug & Play Write_Data_Port at microcontroller Address 0x1 1 ; FIGURE 12C is a diagram of the bitfields of the Plug & Play Read_Data_Register at microcontroller Address 0x12;

FIGURE 12D is a diagram of the bitfields of the Plug & Play State Register at microcontroller Address 0x13;

FIGURE 12E is a diagram of the bitfields of the Plug & Play Control/Status register at microcontroller Address 0x14;

FIGURE 12F is a diagram of the bitfields of the Sound System Base Address Low at microcontroller Address 0x15;

FIGURE 12G is a diagram of the bitfields of the Sound System Base Address High register at microcontroller Address 0x16; FIGURE 12H is a diagram of the bitfields of the Control Base Address Low register at microcontroller Address 0x17;

FIGURE 121 is a diagram of the bitfields of the Control Base Address High register at microcontroller Address 0x18;

FIGURE 12J is a diagram of the bitfields of the Sound Blaster Base Address Low register at microcontroller Address 0x19;

FIGURE 12K is a diagram of the bitfields of the Sound Blaster Base Address High register at microcontroller Address 0x1 A;

FIGURE 12L is a diagram of the bitfields of the Synthesizer Base Address Low register at microcontroller Address Ox IB; FIGURE 12M is a diagram of the bitfields of the Synthesizer Base Address High register at microcontroller Address OxlC;

FIGURE 12N is a diagram of the bitfields of the MPU-401 Base Address Low register at microcontroller Address 0x1 D;

FIGURE 12O is a diagram of the bitfields of the MPU-401 Base Address High register at microcontroller Address Ox IE;

FIGURE 12P is a diagram of the bitfields of the Game Port Base Address Low register at microcontroller Address Ox IF;

SUBSTTTUTE SHEET (RULE 26) FIGURE 12Q is a diagram of the bitfields of the Game Port Base Address High register at microcontroller Address 0x20;

FIGURE 12R is a diagram of the bitfields of the CDROM Base Address Low register at microcontroller Address 0x21 ; FIGURE 12S is a diagram of the bitfields of the CDROM Base Address High register at microcontroller Address 0x22;

FIGURE 12T is a diagram of the bitfields of the Synthesizer Interrupt Select register at microcontroller Address 0 x 23;

FIGURE 12U is a diagram of the bitfields of the Sound Blaster Interrupt Select register at microcontroller Address 0x24;

FIGURE 12V is a diagram of the bitfields of the Sound System Interrupt Select register at microcontroller Address 0x25;

FIGURE 12W is a diagram of the bitfields of the MPU-401 Interrupt Select register at microcontroller Address 0x26; FIGURE 12X is a diagram of the bitfields of the CDROM Interrupt Select register at microcontroller Address 0x27;

FIGURE 12Y is a diagram of the bitfields of the Control Interrupt Select register at microcontroller Address 0x28;

FIGURE 13 is a diagram defining the Plug and Play Port; FIGURE 14A is a diagram of the bitfields of the Sound Blaster DMA Channel Select registers at microcontroller address 0x29;

FIGURE 14B is a diagram of the bitfields of the Sound System Playback/Capture DMA Channel Select registers at microcontroller address 0x2A;

FIGURE 14C is a diagram of the bitfields of the Sound System Capture DMA Channel Select register at microcontroller address 0x2;

FIGURE 14D is a diagram of the bitfields of the CDROM DMA Channel Select register at microcontroller Address 0x2C;

FIGURE 15A is a diagram of the bitfields of the Alternate CDROM Base Address Low register at microcontroller Address 0x2D; FIGURE 15B is a diagram of the bitfields of the Alternate CDROM Base Address High registers at microcontroller Address 0x2E; FIGURE 15C is a diagram of the bitfields of the Physical Device Activation Register at microcontroller Address 0x2F;

FIGURE 15D is a diagram of the bitfields of the Modem Base Address Low register at microcontroller Address 0x30;

FIGURE 15E is a diagram of the bitfields of the Modem Base Address High register at microcontroller Address 0x30;

FIGURE 15F is a diagram of the bitfields of the Alternate CDROM Mask Register at microcontroller Address 0x32;

FIGURE 15G is a diagram of the bitfields of the Modem Mask Register at microcontroller Address 0x33;

FIGURE 15H is a diagram of the bitfields of the Miscellaneous Control Bits register at microcontroller Address 0x34;

FIGURE 151 is a diagram of the bitfields of the Modem Interrupt Select register at microcontroller Address 0x35;

FIGURE 15J is a diagram of the bitfields of the Physical Device Activity Register at microcontroller address = 0x36;

FIGURE 16 is a diagram of the bitfields of the Wavetable and Serial Control Register at microcontroller address 0x40;

FIGURE 17 is a diagram of the bitfields of the reserved register at address 0x41 ;

FIGURE 18 is a diagram of the bitfields of the Port 3 Shadow Register at microcontroller address 0x42;

FIGURE 19 is a diagram emphasizing the circuitry of the EEPROM interface;

FIGURE 20 is a diagram which depicts a flow chart of a detect/load EEPROM sequence;

FIGURE 21 A is a diagram which depicts the fields of address mask register/alternate CDROM base address register (Byte 4) ; '

FIGURE 2 IB is a diagram which depicts the bitfields of Address Mask Register Modem (Byte 5);

FIGURE 21 C is a diagram which depicts the Miscellaneous Configuration Bits, Byte 6;

FIGURE 2 ID is a diagram which defines the bitfields of the Misc Configuration Bits, Byte 7;

FIGURE 21E is a diagram which depicts the Global Configuration, Byte 8 and is copied to 0x4003 on powerup; FIGURE 22A is a diagram which illustrates the timing relationship between the clock and data;

FIGURE 22B is a diagram which depicts an EEPROM device read access;

FIGURE 23 is a diagram of the Plug and Play interface;

FIGURE 24A is a diagram of the bitfields of ISA DATA READ/ MIXER LATCH register at microcontroller address 0x00;

FIGURE 24B is a diagram of the bitfields of the Sound Blaster Data Latch register at microcontroller address 0x01 ;

FIGURE 24C is a diagram of the bitfields of the MPU-401 Receive Data Latch at microcontroller address 0x02;

FIGURE 24D is a diagram of the bitfields of the STATUS REGISTER at microcontroller Address 0x03;

FIGURE 24E is a diagram of the Reserved Registers at microcontroller Addresses 0x04 through 0x07;

FIGURE 24F is a diagram of the bitfields of the Reset Sound Blaster Busy 2 at microcontroller Address 0x08;

FIGURE 24G is a diagram of the bitfields of the Reset Sound Blaster Busy 2 register at microcontroller address 0x00;

FIGURE 241 is a diagram of the bitfields of the Sound Blaster ADPCM Data Latch at microcontroller Address OxC;

FIGURE 24J is a diagram of the bitfields of Set Sound Blaster Busy 1 at microcontroller Address MD;

FIGURE 24K is a diagram of the bitfields of the Sound Blaster DMA Request Register at microcontroller Address ME which is in response to a write of a DMA command to the Sound Blaster Command Register;

FIGURE 24L is a diagram of the bitfields of the Sound Blaster Interrupt Request Register at microcontroller Address OxOF;

FIGURE 25A is a diagram of the bitfields of the Miscellaneous Control Register (at control base +0);

FIGURE 25B is a diagram of the bitfields of the Hardware Control Register;

FIGURE 25C is a diagram of the bitfields of the Power Down Control Register; FIGURE 25D is a diagram of the bitfields of the bitfields of the Control Address/Index Register;

FIGURE 25E is a diagram of the bitfields of the Control Data Register; FIGURE 25F is a diagram of the bitfields of the Command Register: FIGURE 25G is a diagram of the bitfields of the Program RAM Access End Register:

FIGURE 25H is a diagram of the bitfields of the Status Register; FIGURE 251 is a diagram of the bitfields of the Miscellaneous Control register; FIGURE 25 J is a diagram of the bitfields of the Version/ID at Control Index register: FIGURE 25K is a diagram of the bitfields of SRS Control Register; FIGURE 25L is a diagram of the bitfields of 3D Sound Control Register;

FIGURE 25M is a diagram of the bitfields of the S/PDIF Control Register; FIGURE 25N is a diagram of the bitfields of the S/PDIF Channel Status Data register; FIGURE 250 is a diagram of the bitfields of the S/PDIF Channel Status Data register l ; FIGURE 25P is a diagram of the bitfields of the FAB Port ID register;

FIGURE 25Q is a diagram of the bitfields of the Wavetable and Serial Port register;

FIGURE 25R is a diagram of the bitfields of the Left Output Master Volume register;

FIGURE 25S is a diagram of the bitfields of the Right Output Master Volume;

FIGURE 26 is a diagram emphasizing the Codec Interface; FIGURE 27A is a diagram of the bitfields Index Address Register;

FIGURE 27B is a diagram of the bitfields of Indexed Data Register:

FIGURE 27C is a diagram of the bitfields of Status Register;

FIGURE 27D is a diagram of the bitfields of Capture I/O Data Register;

FIGURE 27E is a diagram of the bitfields of Playback I/O Data Register; FIGURE 27F is a diagram of the bitfields of Left ADC Input Control Register;

FIGURE 27G is a diagram of the bitfields of Right ADC Input Control register;

FIGURE 27H is a diagram of the bitfields of Left Auxiliary #1 Input Control Register;

FIGURE 271 is a diagram of the bitfields of Right Auxiliary #1 Input Control Register:

FIGURE 27J is a diagram of the bitfields of Left Auxiliary #2 Input Control Register; FIGURE 27K is a diagram of the bitfields of the Right Auxiliary #2 Input Control

Register;

FIGURE 27L is a diagram of the bitfields of Left DAC Output Control Register; FIGURE 27M is a diagram of the bitfields of Right DAC Output Control Register;

FIGURE 27N is a diagram of the bitfields of Fs and Playback Data Format Register;

FIGURE 270 is a diagram of the bitfields of Interface Configuration Register;

FIGURE 27P is a diagram of the bitfields of the Pin Control Register: FIGURE 27Q is a diagram of the bitfields of the Error Status and Initialization Register;

FIGURE 27R is a diagram of the bitfields of ODE and ID Register:

FIGURE 27S is a diagram of the bitfields of Loopback Control Register;

FIGURE 27T is a diagram of the bitfields of Playback Upper Base Register;

FIGURE 27U isa a diagram of the bitfields of Playback Lower Base Register; FIGURE 27V is a diagram of the bitfields of Alternate Feature Enable I Register;

FIGURE 27W is a diagram of the bitfields of Alternate Feature Enable II Register;

FIGURE 27X is a diagram of the bitfields of Left Line Input Control Register;

FIGURE 27Y is a diagram of the bitfields of Right Line Input Control Register;

FIGURE 27Z is a diagram of the bitfields of Timer Lower Base Register: FIGURE 27AA is a diagram of the bitfields of Timer Upper Base Register;

FIGURE 27AB is a diagram of the bitfields of Alternate Sample Frequency Select Register;

FIGURE 27 AC is a diagram of the bitfields of Alternate Feature Enable III Register;

FIGURE 27AD is a diagram of the bitfields of Alternate Feature Status Register; FIGURE 27AE is a diagram of the bitfields of Mono Input and Output Control Register:

FIGURE 27AF is a diagram of the bitfields of Left Output Attenuation Register;

FIGURE 27AG is a diagram of the bitfields of Capture Data Format Register;

FIGURE 27AH is a diagram of the bitfields of the Right Output Attenuation Register;

FIGURE 27AI is a diagram of the bitfields of Capture Upper Base Register; FIGURE 27AJ is a diagram of the bitfields of the Capture Lower Base Register;

FIGURE 27AK is a diagram of the bitfields of the Left Alternate FM Input Control Register;

FIGURE 27AL is a diagram of the bitfields of the Right Alternate FM Input Control Register; FIGURE 27AM is a diagram of the bitfields of the Left Mic Input Control Register;

FIGURE 27AN is a diagram of the bitfields of the Right Mic Input Control Register;

FIGURE 27AO is a diagram of the bitfields of Control Register; FIGURE 27AP is a diagram of the bitfields of Control Register;

FIGURE 27AQ is a diagram of the bitfields of the Left FM Volume Control Register:

FIGURE 27AR is a diagram of the bitfields of Right FM Volume Control Register;

FIGURE 27AS is a diagram of the bitfields of Left DSP Serial Port Volume Control Register;

FIGURE 27AT is a diagram of the bitfields of Right DSP Serial Port Volume Control Register;

FIGURE 27AU is a diagram of the bitfields of Right Digital Loopback Volume Control Register; FIGURE 27 AV is a diagram of the bitfields of DAC, SRC Control Register;

FIGURE 27AW is a diagram of the bitfields of Capture Sample Rate Control Register;

FIGURE 27AX is a diagram of the bitfields of Playback Sample Rate Control Register;

FIGURE 27AY is a diagram of the bitfields of Left PCM Audio Volume Control Register; FIGURE 27AZ is a diagram of the bitfields of the Right PCM Audio Volume Control

Register;

FIGURE 27BA is a diagram of the bitfields of the Left Wavetable Volume Control Register;

FIGURE 27BB is a diagram of the bitfields of Right Volume Control Register; FIGURE 28 is a diagram illustrating the timing of context switch mechanism;

FIGURE 29 is a diagram of the External Peripheral Port;

FIGURES 30A and 3 OB are diagrams illustrating exemplary read/write operations through the external peripheral port:

FIGURE 31 illustrated the synthesizer and CDROM interface; FIGURE 32 emphasizes the clocking scheme for the device

FIGURE 33 is a diagram of the Game Port which provides an interface to a standard personal computer type joystick;

FIGURE 34 is a diagram illustrating the speed control variation:

FIGURE 35 is a timing diagram illustrating the joystick port timing; FIGURE 36A is a diagram of the Joystick control circuitry;

FIGURE 36B is a diagram of the Joystick Digital Assist circuitry;

FIGURE 37A is a diagram of the bitfields of the Digital Assist Control/Status Register: FIGURE 37B is a diagram of the bitfields of Joystick Trigger/Xl Position Data Low Byte;

FIGURE 37C is a diagram of the bitfields of the XI Position Data High Byte;

FIGURE 37D is a diagram of the bitfields of the Yl Position Data Low Byte; FIGURE 37E is a diagram of the bitfields of the Yl Position Data High Byte;

FIGURE 37F is a diagram of the bitfields of the X2 Position Data Low Byte;

FIGURE 37G is a diagram of the bitfields of the X2 Position Data High Byte;

FIGURE 37H is a diagram of the bitfields of the Y2 Position Data Low Byte;

FIGURE 371 is a diagram of the bitfields of the Y2 Position Data High Byte; FIGURE 38 is an additional timing diagram illustrating the operation of joystick interface;

FIGURE 39 is a diagram of one channel of the input mixer (the second channel is identical);

FIGURE 40 is a diagram of one channel of the output mixer (the second channel is also identical);

FIGURE 41 is a diagram of the mono audio channel;

FIGURE 42 is a diagram of the digital audio processing subsystem;

FIGURE 43 is a diagram of the digital audio mixer;

FIGURE 44 is a diagram illustrating the attenuation scheme for the Digital to Analog Converter Volume Control;

FIGURE 45 is a more detailed diagram of the FM synthesis block 124;

FIGURE 46A is a diagram of the bitfields of the Status Register;

FIGURE 46B is a diagram of the bitfields of the Test Register;

FIGURE 46C is a diagram of the bitfields of the Timer #1 Register; FIGURE 46D is a diagram of the bitfields of the Timer #2 Register;

FIGURE 46E is a diagram of the bitfields of the Timer #1,#2 Control Register;

FIGURE 46F is a diagram of the bitfields of the 4-Operator Mode Register

FIGURE 46G is a diagram of the bitfields of the Expansion Register:

FIGURE 46H is a diagram of the bitfields of the Keyboard Split Register; FIGURE 461 is a diagram of the bitfields of the Power Management Register;

FIGURES 46J is a diagram of the bitfields of the Tremolo Effect Register;

FIGURES 46K is a diagram of the bitfields of the Vibrato Effect Register;

10

SUBSTITUTE SHEET (RULE 25) FIGURE 46L is a diagram of the bitfields of the Non-percussive/Percussive Sound Register:

FIGURE 46M is a diagram of the bitfields of the Rate Key Scale Register;

FIGURE 46N is a diagram of the bitfields of the Frequency Multiplier Register; FIGURE 460 is a diagram of the bitfields of the Total Level Register:

FIGURE 46P is a diagram of the bitfields of the Level Key Scale Register:

FIGURE 46Q is a diagram of the bitfields of the Attack Rate

FIGURE 46R is a diagram of the bitfields of the Decay Rate Register;

FIGURE 46S is a diagram of the bitfields of the Release Rate Register; FIGURE 46T is a diagram of the bitfields of the Sustain Level Register;

FIGURES 46U is a diagram of the bitfields of the F-Number Register;

FIGURE 46V is a diagram of the bitfields of the Block;

FIGURE 46 W is a diagram of the bitfields of the Key On;

FIGURE 46X is a diagram of the bitfields of the Rhythm; FIGURE 46 Y is a diagram of the bitfields of the Rhythm Instrument Selection;

FIGURE 46Z is a diagram of the bitfields of the Algorithm Selection;

FIGURES 46 AA are a diagram of the bitfields of the Feedback Modulation:

FIGURE 46AB is a diagram of the bitfields of the Output Channel Selection;

FIGURE 46AC is a diagram of the bitfields of the Register Settings; FIGURE 47 is a diagram representing the implementation of two audio processing algorithms;

FIGURE 48 is a diagram representing the implementation of the algorithms in the 4 operator audio processing mode;

FIGURE 49 is a functional block diagram of the stereo processor portion a selected DSP; FIGURE 50A is a diagram of the zero cross volume control circuitry:

FIGURE 50B is a diagram showing further detail of the zero cross volume control circuitry of FIGURE 50A;

FIGURE 51 is a diagram of the hysteresis circuitry for power-on of the VCO;

FIGURE 52A is a diagram of the bitfields of the SRS Control Register: FIGURE 52B is a diagram of the bitfields of the 3D Sound Control at Control Index

Register:

FIGURE 53 is a diagram depicting the operation of the serial port during mode 1 : FIGURE 54 is a diagram depicting the operation of the serial port during mode 2: FIGURE 55 is a diagram depicting the operation of the serial port during mode 3: FIGURE 56 is a diagram depicting the operation of the serial port during mode 4; FIGURE 57 is a diagram illustrating a typical block/frame for S/PDIF data; FIGURE 58 is a diagram of the typical serial subframe;

FIGURE 59 is a diagram of the coupling between the Codec and a wavetable synthesizer; FIGURE 60 is a diagram of the timing of the exchange of data between the codec and the wavetable synthesizer;

FIGURE 61 is a test bit chart describing this mode; FIGURE 62 is a diagram of microcontroller memory map in Test Mode;

FIGURE 63 is a diagram of the pinout of the codec device; FIGURE 64A is a diagram of the external microphone circuit; FIGURE 64B is a diagram of an example of a phantom power microphone circuit; FIGURE 65 is a diagram of a circuit that may be used to drive the Line Out and Headphones;

FIGURE 66 is a diagram of an alternate mixer section 6400;

FIGURE 67A is a diagram of the control register holding the Version and ID bets in an alternate embodiment;

FIGURE 68 is a diagram of the bitfields of the FAB Port ID Register in alternate embodiments;

FIGURE 69A is a diagram of the bitfields of the Command Register in alternate embodiments;

FIGURE 69B is a diagram of the bitfields of the Program RAM Access End Register in alternate embodiments; FIGURE 70 is a diagram of the PnP status register configuration when Crystal Key 2 is employed;

FIGURE 71 A is a diagram of the bitfields of the Miscellaneous Control Register in alternate embodiments:

FIGURE 71 B is a diagram of the bitfields of the Power Down Control Register 1 in alternate embodiments;

FIGURE 71 C is a diagram of the bitfields of Power Down Control Register 2 in alternate embodiments; FIGURE 72 is a diagram defining the register location for the watchdog timer status bit;

FIGURE 73 is a diagram of the bitfields of the interrupt select register:

FIGURE 74 is a diagram of the modem mask register in alternate embodiments;

FIGURE 75A is a diagram of the analog stereo expansion circuitry in alternate embodiments;

FIGURE 75B is a diagram illustrating the frequency response of the analog expansion circuitry of FIGURE 75 A;

FIGURES 75C and 75D are diagrams of the 3D Sound Serial Interface Control and 3D Sound Control register, respectively; FIGURE 76 is a diagram representing the serial interface connection of an accelerator/

ZVPORT with an alternate embodiment of the codec;

FIGURE 77 shows the connection of wavetable synthesizer 134 with the alternate embodiment of the codec;

FIGURE 78 is a diagram of the timing for the Internal SCLK Mode, where 16-Bit Data is shown;

FIGURES 79A and 79B and diagrams of the I²S data format;

FIGURE 80 is a diagram illustrating the ZV Port Audio Interface timing;

FIGURE 81 is a diagram emphasizing one digital audio path for the alternate embodiments; FIGURE 82 depicts the bitfields of the 3D Sound/Serial Interface Control Register:

FIGURE 83 and 84 are diagrams showing Codec registers 117 and 123 in the alternate embodiments;

FIGURE 85 is a diagram of the modified codec register 126 in an alternative embodiment in which the mono support logic has been eliminated; FIGURE 86 is a diagram of a modified control register C 18;

FIGURE 87 is a diagram depicting miscellaneous control bits in alternate embodiments;

FIGURE 88 is a diagram of the Global Status Register in alternate embodiments;

FIGURE 89 is a diagram of the bitfields of the Global Configuration EEPROM Byte 2; and FIGURE 90 is a diagram of the bitfields of the DMA SP,iRQ EEPROM Byte.

13

SUBSTTTUTE SHEET (RULE 26) DESCRIPTION OF THE PREFERRED EMBODIMENTS

The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGURES 1- 90 of the drawings, in which like numbers designate like parts. Unless otherwise noted, hexadecimal notation is indicated by Ox???? or ????. Byte ordering of words is - high byte, low byte.

FIGURE 1A is a functional block diagram of an audio codec 100 according to the principles of the present invention.

The input and output of data and control signals between codec 100 and an external ISA bus is effectuated through an I/O bus interface 101. Configuration and control block within I/O bus interface 101 allows a host, via the ISA bus, to configure codec 100 for selected operating modes, and in particular those required by the Plug and Play standard. Additionally, interface

101 allows a host on the ISA bus to set-up I/O base addressing to codec 100, define the codec

100 to ISA bus interrupt mapping, and define the DMA channel mapping for the codec 100 memory space. Along with a microcontroller 103, bus interface supports Plug & Play 1.0 as specified by Microsoft and Intel. In particular, Plug & Play is supported generally by the circuitry shown at 106. Circuitry 106 includes configuration and control block 102 discussed above, specific logic circuitry required for the interface 107, including the codec register interface 107 and decoder 108. Circuitry 107 and 108 allow the host to configure codec operations such as the input and output mixing functions.

Microcontroller 103. which includes an Intel™ 8052 core. 10 Kbytes of ROM and 1 Kbyte of RAM. also supports the Sound Blaster and MPU-401 standards. MPU-401 standard data interfaces with microcontroller 103 through dedicated interface 104 and port MIDI. For example, data may be exchanged between port MIDI and microcontroller 103 using the 8052 UART standard protocol. Interface 104 also includes logic circuitry required for hardware handshaking of data to and from microcontroller 103 and the ISA bus.

Joystick logic block 105 includes a timer-like interface to the joystick port. External Peripheral EPROM block 109 provides general purpose 8-bit data path control for interfacing to external devices such as a CDROM, modem, or synthesizer chip utilizing /XIOW, /XJ.OR. ><7:0>, XA <2:0> +/BRESET ports.

The codec portion of codec 100 includes digital to analog converters which convert to analog form, digital data such as serial audio data received through the SERIAL PORT, parallel sound data received through data port SD<7:0> to interface 101, or synthesizer data generated on chip by an FM synthesizer (discussed below).

The Codec functionality is based on D/A converters 110 and A/D converters 1 11 utilizing switch-capacitor filters and delta sigma modulators, respectively. The sampling frequency at which the A/D and D/A converters (111 and 110) operate is fixed at 44.1 kHz. The delta-sigma modulator for the A/D conversion is implemented with a third order algorithm. The filter for the

D/A conversions is a second order switched capacitor filter, with 128 FS oversampling.

Prior to digital to analog conversion by DACs 1 18, Sample Rate Converters 1 12 convert the digital interface sampling rate of the data received from the ISA bus (normally 5.51 kHz to 50.4 kHz) to 44.1 kHz at the inputs to D/A converters 110.

Similarly, analog data from the mixer function, also described below, undergo reverse sample rate conversion. Sample Rate Converters 113 convert the output sampling rate from A/D converters 111 from 44.1 kHz to between 5.51 kHz and 50.4 kHz for output to the ISA bus. Only one 16.9344 MHz clock is needed with this Sample Rate Conversion scheme. Independent sample rates for the A/D and D/A converters is also supported.

The Mixer functionality is implemented with 6-channel INPUT Mixers 1 14a and 114b and 6-channel OUTPUT Mixers 1 15a and 1 15b. The input mixers allow data output from DACs 110 to be mixed with direct audio data from the left and right input lines LLINE and RLINE, the left and right auxiliary lines (LAUX1, RAUX1. LAUX2, RAUX2) and the microphone inputs (LMIC. RMIC). the mixed signal eventually re-converted for delivery to the ISA bus. The output data mixing function allows for selective mixing of the data output from DACs 1 10 with analog sound data received directly from the line in left and right (LLINE, RLINE) inputs, the auxiliary lines (LAUX1, RAUXl and LAUX2, RAUX2) or the microphone line (MIC). Output from the output mixer function is output directly through left, right and middle lines out (LOUT, ROUT, MOUT). The AUX2 input port which is typically used for CD-ROM, features a differential input

(VEM) to eliminate ground loop noise. The Microphone stereo inputs can also be configured as mono differential inputs.

An FM Synthesis Engine 124 is also provided. The digital output of FM Synthesis Engine 124 is converted to analog by the Codec function, described above. Joystick logic block 105 implements a standard interface to two joysticks. The second joystick pins are dual function in that the pins may be switched over to support Serial Port Interface 1 17. Special Digital Assist hardware has also been included to eliminate the need for the Host to poll the joystick data.

Audio Codec 100 incorporates DSP engine 1 18 to implement the industry standard SRS

"3D" and QSound "3D" Stereo audio algorithms. As will be discussed further below, data is input to and output from the mixing function through First-In-First-Out registers (queue) 121. Linear processing Circuitry 120 allows for standard μlaw, A-law and ADPCM linear processing on both data being input to DACs 110 data and output from A to D converters 1 1 1.

Synthesis interface 123 allows codec 100 to interface with an external conventional wavetable synthesizer. Sound Blaster (SB) and Windows Sound System (WSS) registers are generally shown at 127, all of which are discussed more fully below. Generally, these registers allow the host to set-up for industry sound protocols such as Sound Blaster and Microsoft

Windows Sound System.

S/PDIF circuitry 1 19 supports digital data output from Serial Port formatted to the Sony Phillips Digital Interface Format. S/PDIF data can be input directly for transfer to the ISA bus. via sample rate converters 113 or sent to the mixer functions through DACs 1 10. through serial port 1 17 discussed above.

FIGURE IB is a diagram of one of a number of possible system applications for codec

100. In this case an audio accelerator 125, such as a Crystal Semiconductor CS461x audio accelerator, receives and accelerates audio from a PCI bus 126. Accelerator 125 also provides in this example a direct interface to Codec 100 for SPDIF and/or I²S formatted audio data.

Accelerator 125 exchanges data with codec 100 through a Legacy link 127. The accelerator interface of codec 100 will be discussed in detail below.

Codec 100 receives data, such as Plug & Play (PnP) audio data, directly from an ISA bus 130. This data, as well as any internally generated FM synthesizer data, are passed on to the analog mixing and codec functions of codec 100. These functions also directly interface with such external devices as a joystick. MIDI source. CD player, microphone or external speakers.

As discussed below, codec 100 also has provisions for interfacing with an external wavetable synthesizer. FIGURE 2 is a diagram providing a general overview of the bus structure and principle registers of Codec 100. Codec 100 is based upon three buses: bus 201 (the E_BUS); bus 202 (the

I_BUS); and bus 203.

16

SUBSTTTUTE SHEET (RULE 26) In FIGURE 2. the codec functionality is generally shown at 204. Codec 204 is associated with Codec registers 205. Microcontroller 103 is associated with microprocessor written registers 206. which also store miscellaneous status bits. Registers 207 are the ISA bus written registers and also store miscellaneous status bits. The control base registers C0-C7 and three indirect registers are shown generally at 208.

Generally shown at 209 are the C8 control base register and digital joystick registers.

FIGURE 3 is a functional block diagram of microcontroller core 103. Microcontroller core 103 is based on an Intel™ 8052 microcontroller. Core 103 is used in conjunction with 10 Kbytes of external ROM 301 and 1 Kbytes of external RAM 302. The timing bases from which microcontroller 103 operates are established from external clocks by clock generation circuitry 303 and timing and control circuitry 304. Interrupts are timed by interrupt serial port timers within NSFR registers/ timers 305.

SFR/ timers 305 also support two 8-bit I/O ports SFRAB and SFRDB. In addition to the external memory, microcontroller 103 also includes two 56-bytes of random access memory (RAM) 306.

The instruction control and processing portion of core 103 includes instruction register 307, DPT register 308, program counter 309, program counter incrementor 310, buffer 31 1, program address register 312, stack pointer 313 and B register 314.

The data processing portion of core 103 includes an accumulator 315, temporary storage registers 316a and 316b, and ALU 317 and PSW circuitry 318.

I/O interface 319 allows process microcontroller 103 to communicate with ISA interface 101, external ROM 301 and external RAM 302.

Core 103 operates on a 2-phase non-overlap clock with an effective clock rate of 33.8688 MHz (2 x 16.9344 MHz) or 32.768 MHz (2 x 24.576/1.5). The Core 103 and Codec functions are synchronized to minimize noise generation. The clock is generated by clock generation circuitry 303 from either the 16.9344 MHz or the 24.567 MHz crystal depending on the currently defined sample rate (oscillator 120, FIGURE 1). In order to minimize clock switching disturbances, the microcontroller clock is set equal to the 16.9344 MHz crystal frequency or the 24.576 MHz crystal frequency divided by 1.5 (16.384 MHz). Clock generator circuitry 303 and timing and control circuitry also provide a second timer

("Timer2") for MIDI baud rate generation. The MIDI baud rate is defined as 31.25 kHz +/- 1 %. Hence, the frequency variation of the microprocessor clock, as different crystals are selected, violates the MIDI baud rate specification. Therefore the 16.9344 MHz crystal is always used as the clock input to Timer 2. This requires that the 16.9344 MHz crystal always be running when MIDI is in use and the Timer 2 clock be input on the external timer input pin (EXTCLK2). Because microcontroller 103 samples the timer 2 clock input with a clock that is 1/12 of the processor clock, the 16.9344 MHz crystal is divided by 17 and fed to the timer 2 input. Timer

2 is then used to perform a divide by 32 to obtain the proper MIDI baud rate of 16.9344 MHz/(32* 17)=31129 kHz, which is within the +/- 1% specification.

FIGURE 4 is a diagram of the microcontroller 103 memory map. As shown in FIGURE 4, microcontroller 103 includes three separate memory spaces as follows: ROM, Internal RAM, and External RAM.

10 Kbytes of the microcontroller 103 64 Kbyte ROM space (at addresses 0000H to 27 FFH) are used to store the program code for microcontroller 103. After power-on reset, microcontroller 103 will start executing instructions from location 0OOOH.

A PnP (Plug and Play) Serial ID is reported to a host processor during a PnP ISOLATION operation, discussed below, and is dependent on the following: Whether a Host Load with

PNP_UPDATE command has occurred or an EEPROM is present at Port 109, the resource data sent via a Host Load ("host shoot") or EEPROM, or the value seen in register 125 by Codec 100.

A default PnP Serial ID in ROM 301 identifies, among other things, the vendor part number, vendor ROM ID number, program code version and ROM resident LSFR. A default ROM image of PnP data including the default PnP serial ID is copied from

ROM 301 to RAM 302 at powerup, before an external EEPROM coupled to port 109 is detected.

The image in RAM 302 is used as the operating program code. If no EEPROM is present on port

109 and no host resource shoot has been performed, the PnP resource data that was copied from

ROM to RAM is used. Specifically, the PnP serial ID copied from ROM is used if no EEPROM is present or no host resource shoot has taken place.

The Default ROM PnP Image is defined in TABLE 1.

If an EEPROM is detected, the EEPROM resource data is copied over the default ROM image in RAM. Firmware then examines the EEPROM serial ID (in RAM) for the OxOE, 0x63 Vendor EISA ID in the first two serial ID bytes. If these two bytes are not found, the RAM serial ID remains the same as the EEPROM serial ID.

If the first two bytes of EEPROM serial ID are OxOE, 0x63. then the contents of register 125, are used to determine the 'Vendor Part ID' portion of the PnP serial ID.

18

SUBSTITUTE SHEET (RULE 25) For a host resource shoot followed by a PNP_UPDATE command, the serial ID is examined for a OxOE, 0x63 in the first two bytes. As in the EEPROM case, if these two byte are. not found, the RAM serial ID (host shoot) remains unchanged.

If the first two bytes of the host shoot serial ID are OxOE, 0x63, then the contents of register 125 are used to determine the 'Vendor Part ID' portion of the PnP serial ID. The serial

ID is examined and changed if necessary during the PNP-UPDATE command.

If the firmware causes an update the PnP Serial ID based on the criterion above, register

125 will be read and the table scanned for a matching value in the lower five bits. If no match is found, no change will be made. If a match is found, the Vendor Part ID will be replaced with the table value, the OEM ID and serial number are preserved and a new LSFR checksum is calculated.

To facilitate segregation of EEPROM based code shoots among the various past and future pin compatible devices, a 'Family Byte' has been created/defined. If the EEPROM supplied Family Byte does not match the ROM expected value, the EEPROM firmware RAM patch will be ignored. The resource data, however, will be loaded normally. This byte allows the firmware to ignore patch code intended for a different release when the EEPROM has not been updated.

EEPROM Hardware configuration byte 9, RAM location 0x4004, is used by the firmware to match EEPROM code shoots to ROM firmware releases. This byte is compared to a stored ROM value for a given ROM release. If the bytes do not match, the EEPROM image load is terminated by the firmware at 0x417F, after the resource data (0x417F is the top of resource data and 0x4190 is the beginning of the firmware RAM patch table).

Support for a Digitally Assisted Joystick is included in the firmware. This feature will be discussed further below with regards to the detailed description of the Game Port. A set of commands is issued by the Host initiates actions to be taken by the microcontroller 103. The

Host port is through joystick base + 7, but the ROM firmware will mirror this port at joystick base + 6.

Codec 100 includes a set of defined pins (Up, Down, Mute) which may be used with external switches to control the overall audio level driven out the line outputs. Microcontroller 103 is used in conjunction with Master Volume control registers 127 A and 129 A 205 to effectuate the desired audio level set by the external switches. The Master Volume Control provides a dynamic Range of +12dB to -36dB. The Master Volume Control will be discussed in detail in conjunction with the Codec Interface.

The Features Byte/REVISION Byte at 0x41BF indicates major feature sets of the embedded microcode. Each bit in this byte represents a feature or feature set. This byte is written 0x22 on powerup. This byte definition changes definition with each chip family.

The Firmware Revision Number Byte indicates the current revision of the embedded microcode patch.

FIGURE 5 is a more detailed diagram of the mapping of the program RAM spacing within RAM 302. In view of FIGURE 5, the program RAM of Codec 100 can now be discussed in detail.

In addition to the ROM memory 301, 1.5 Kbytes of Program RAM 302 are included for microcontroller code changes and as a storage area for Plug and Play configuration data. Because microcontroller 103 instructions may only be executed from ROM addressable memory (read only), the Program RAM is mapped into the microcontroller 103 ROM 301 address space. In order to allow the Program RAM to be written via microcontroller 103, the Program RAM is directly mapped into the microcontroller 103 external RAM memory space. In this way the Program RAM may be accessed (read/write) via microcontroller 103 MOVX instructions as well as read during ROM instruction fetches. Changes may be made via the ISA Interface by loading new code into the Program (Instruction) RAM area and then changing the subroutine vector location to correspond to the new code location.

On power-up the microcontroller 103 will load Codec 100 configuration data. Plug-n-Play resource data, and RAM patch code, from external EEPROM into the Program RAM. The data stored in the Program RAM is then used to configure Codec 100 internal hardware.

The fact that the configuration and resource requirements are determined via data that is stored in Program RAM allows the configuration and resource signature of Codec 100 to modified by the host. The host downloads updated configuration and resource data through the Codec 100 RAM Access Register, discussed further below.

The method by which the Program RAM is accessed by the microcontroller 103 is defined as follows. Strategically placed within the ROM code are a set of instructions. These instructions cause the microcontroller 103 to store an identifier in microcontroller 103 register

R7 and a subroutine CALL to address 0x41C0 is made. Address 0x41C0 is located in the

Program RAM patch area. Once the CALL is made to 0x41C0, patch RAM routines may read microcontroller 103 register R7 to identify where in the ROM code that the CALL to address 0x41C0 was made. In this way ROM coded routines may be replaced or modified in function by Program RAM resident patch code.

To prevent accidental execution of invalid code, when loading the Program RAM via the host, the Program RAM must be loaded in segments. The very last segment must be a one byte load to address 0x41 CO.

Multiple Patch RAM entry points from ROM in locations from 0x4190 to 0x41 CO. Initialization code fills all these locations with a RET (0x22) instruction. At strategic points in the ROM code, these entry points are called with the mRAMx macro (macro RAM) where 'x' refers to the particular entry point.

The following is an example of an mRAM macro. These macros are placed in the code source to allow RAM based code changes.

Multiple CALLs can be made to the same mRAM entry point as each use of the particular mRAMx has a unique value in R7.

If patches have not been loaded. RAM locations 0x4190 through 0x41C0 will contain a 0x22. After a patch is loaded, addresses 0x4 IBD through 0x41BF contain Firmware Revision data and 0x41C0 will contain a value other than 0x22. Upon a RESET or SW RESET command, the region from 0x4190 to 0x41C0 will be filled with a RET (RAM entry) opcode (0x22). The RAM entry points are identified in TABLE 2. The CALLing points, scattered throughout the ROM, CALL RAM and return. Once a host based (or EEPROM) load image is written to RAM. the code effectively vectors to the patch code when the entry point is called. A JUMP_TO_ROM command is used before loading RAM via the control port to insure code is not loaded over code that is currently executing from RAM (from a previous load).

Codec 100 will detect an existing configuration/code load sequence by identifying a RAM load starting at memory location 2090h. Codec 100 will then insure that configuration data is moved to the new RAM area. REVC Sound Blaster code is ignored. PnP resource data RAM writes to address 2090h are captured by the Codec 100 and translated and written to address 400Ch for resource data compatibility.

The Program Ram is accessible from ISA Bus interface 101 via a Program RAM Access Register (Control_Base+5) and a Program RAM Access End Register (Control_Base+6). When either the Codec 100 Program RAM Access Register or Program RAM Access End Register is read or written by the ISA Bus, an interrupt is generated to the microcontroller 103. The microcontroller 103 reads the data and processes it. These registers locations are discussed below with regards to the Central Register.

Commands and data are written to a Program RAM Access Register. The data may be a command, command parameter data, or data to be loaded into RAM. The Codec 100 supports additional commands other than those specific to RAM access. The Program RAM Access End

Register is used to terminate the command/data transfer sequence. Each Program RAM read or write sequence must be terminated with a write to the Program RAM Access End Register.

A command is executed by writing the command data value to the Program RAM Access Register. The available commands, which are also discussed in conjunction with the Control

Register description, are as follows:

DISABLE_PNP,

DISABLE_CSC,

UPDATE_PNP (0x5A), RAM_LOAD (OxAA),

FINISH,

RESUME,

RAM_PTR_LOAD,

HOLD, GO,

JUMP_TO_ROM,

SET_READ_ROM_FLAG,

SET_ACC_ΓNT_FLAG.

A typical sequence to load the Program RAM is as follows: 1. The Codec 100 base I/O address is configured so that the Program Access

Registers are accessible: a. the host sends 32 byte "Key" sequence: and b. the Codec 100 base I/O address is configured by the host writing the following 8-bytes to address 0x279: 0x15, 0x02, 0x47. 0x_base address high byte. 0x_base address low byte, 0x33,0x01.0x79.

2. The host downloads the data to Program RAM: a. the host sends a RAM_LOAD command by writing a OxAA to

Codec 100 base address +5; b. the host sends a starting download address (0x4000) by writing low byte starting RAM address (0x00) to Codec 100 base +5 and writing high byte starting RAM address (0x40) to Codec 100 base +5; and c. the host downloads the data by writing successive bytes to Codec 100 base +5.

3. The host terminates Program RAM download by executing a write of 0x00 to Codec 100 address base +6.

4. The host instructs Codec 100 to update configuration by sending UPDATE_PNP command and writing 0x5A to Codec 100 base address +5.

The External microcontroller RAM area is used for communication to devices external to microcontroller 103. This includes Sound Blaster/MPU-401 /wavetable registers and the Program RAM. FIGURE 3 emphasizes the interface between microcontroller 103 and external RAM 302 and Codec 100 external registers. The IOHAD[7:0] and XDBAL[7:0] address outputs from microcontroller 103 core are decoded with read/write (RD/WR) circuitry to generate strobes and read enables. Additionally, XDBAL[5:0], and IOHAD[6] are decoded to generate device decodes for all microcontroller 103 externally accessible registers. Bits XDBAL[7:0], IOHAD[3:0], and IOHAD[6] are used in accessing the Program RAM. The XDB[7:0] output from microcontroller 103 core is a bi-directional data bus over which data flows between microcontroller 103 and external devices.

As noted above, in Codec 100 internal microcontroller 103 is used to support any number of functions. These include: PnP, Sound Blaster, MPU-401, and Control Port commands. Microcontroller 103 interrupt capability (Block 305, FIGURE 3) is used to call microcontroller 103 when specific ISA Bus host accesses have occurred. The INTO interrupt input to microcontroller 103 is used for the Plug-n-Play and Crystal

Key. Microcontroller 103 INT1 interrupt is used for Sound Blaster, MPU-401. and Control Port commands. Timer interrupt TRO is used for Sound Blaster ADPCM. (These signals are shown as inputs to block 305 of FIGURE 3.)

Because microcontroller 103 requires on the order of 2usec to respond to an interrupt, the interrupting ISA Bus access is held via a signal IOCHRDY until microcontroller 103 acknowledges the interrupt request. In this way microcontroller 103 acknowledges each interrupt is unique.

During Plug-n-Play sequences, the INTO input to microcontroller 103 is forced active whenever a "Plug-n-Play Key" or "Vendor Key" is received.

In order for microcontroller 103 to be able to identify specific host accesses to Sound Blaster, MPU-401, and the Control Ports, Port 1 of microcontroller 103 is used to specify an 8-bit

Interrupt Identification byte, the bitfields of which are shown in FIGURE 6 and described as follows:

SBD Sound Blaster data available bit.

LD1-LD0 Specify one of four logical devices. (These logical devices are not related to Plug-n-Play logical devices.)

A2-A0 ISA Bus address bits SA2, SA1 , SAO respectively.

R/W Indicates current ISA cycle type. 0= Write, l=Read

SBW Sound Blaster write busy bit

TABLE 3 describes the interrupts for the Sound Blaster and Sound System modes (where INTO. INT1 , and TRO are inputs to circuitry 305, FIGURE 3).

When a ISA bus Sound Blaster ADPCM DMA write occurs, the INTO interrupt is generated to microcontroller 103. Microcontroller 103 responds by reading the data from external microcontroller 103 address OxOC.

Significant Sound Blaster performance gains are realized by mapping Codec registers 107 directly into microcontroller 103 SFR address space. This change allows microcontroller 103 independent access to the codec registers (i.e. mixer functions) while DMA data is transferred to and from the FIFO's (discussed later).

TABLE 4 specifies the mapping of codec registers into the microcontroller 103 SFR address space. The codec register R0 is only implemented to support the MCE and TRD bits. All other bits in register R0 are don't cares. Codec registers R2 and R3 function normally.

Codec 100 normally does not allow access to Codec registers 107 by the ISA Bus and microcontroller 103 at the same time. However in the case of Sound System operation with

24

SUBSTITUTE SHEET (RULE 25) master volume control. Sound System accesses can occur simultaneously with microcontroller

103 access to the master volume control registers I27A and I29A (Codec Registers 205.

FIGURE 3). To address this problem a Request/Grant handshake mechanism has been developed. The timing is shown in the diagram of FIGURE 7. Two microcontroller 103 accessible bits are defined as a codec access REQUEST and

GRANT. These bits are reset to zero via RESDRV and software reset via bits PM1 , PM0.

Microcontroller 103 sets the REQUEST bit to a one when it requires access to any codec register

205 (I27A. 129 A) and when the Context Switch status is in Sound System mode. Once this bit is set the GRANT bit will be generated immediately if no ISA bus access to any codec register is in progress. Otherwise, if an ISA bus access to any codec register is in progress then the generation of GRANT will be delayed until the current ISA bus cycle has finished.

Once the GRANT bit is set, any further ISA Bus cycles to any. codec registers are held off via the IOCHRDY signal. Microcontroller 103 is then free to access registers Codec 127A and 129A without contention with the ISA Bus codec register accesses. Once microcontroller 103 has finished its access, it clears the REQUEST bit. The clearing of the REQUEST bit also clears the GRANT bit which in turn releases IOCHRDY. The current ISA Bus codec access being held is then allowed to complete.

The REQUEST/GRANT bits are mapped into microcontroller 103 Port 3 register. For test purposes the bits available on Port 3 are also available at microcontroller 103 external address 0x42. All bits are read only except for the REQUEST bit which is read/write. The mapping of the Port 3 bits at microcontroller 103 external address of 0x42 allows external chip access via Test Mode 4 (discussed below). The function of these bits can thus be verified with and without microcontroller 103 operation.

Port 3 Bit Definitions are shown in FIGURE 8 and can be described as follows: P3.3 - REQUEST - Read Write.

This is set to a one when microcontroller 103 is updating codec registers and there is possible contention with ISA bus accesses (Sound System mode). After polling for GRANT=1 , microcontroller 103 may access codec registers as needed. After microcontroller 103 has finished its codec accesses, the REQUEST bit should be set to zero to re-enable ISA access to the codec registers. P3.4 - GRANT - Read Only.

This bit is polled by microcontroller 103 after setting the REQUEST bit=l. When

GRANT is equal to one, microcontroller 103 may access codec registers without contention with the ISA bus. When GRANT=1 and subsequent ISA codec accesses are held off via IOCHRDY until the REQUEST bit is set to zero by microcontroller 103.

In Codec 100, microcontroller 103 is used to perform and control a variety of functions. The microcontroller 103 controls these functions through a number of registers that are mapped into microcontroller 103 external memory space. These registers are shown generally at 107 FIGURE 1. An external device memory map is provided in TABLE 5. FIGURE 9 is a diagram providing an overview of the circuitry of Codec 100 supporting

Plug & Play (PnP) interface 106 to external ISA bus 130. Included within ISA Interface 101 is an interface to microcontroller 103 core (including control logic 901, data buffer 902. and address latch 903), an interface to Codec 204, and configuration logic 904 that is Intel/Microsoft "Plug & Play" (PnP) compatible. ISA interface 101 also generally includes data buffers 905, circuitry 906 for generating signal IOCHRDY from wait state status information, DMA mapping logic 907 and Interrupt Mapping logic 908.

Codec 100 operates in conjunction with a number of other associated Plug & Play devices 909 also mapped to the ISA Bus. Each block 909 has associated with it a set of resource requirements and associated configuration registers, organized into groups called physical devices. TABLE 6 lists the maximum resource requirements for each physical device. The

Intel/Microsoft Plug & Play specification organizes devices into logical groupings (logical devices) comprised of one or more physical devices.

The Plug & Play Specification 1.0a describes a hardware and software mechanism whereby ISA cards are isolated, identified, and then optimally allocated within a system's resource environment. To be Plug & Play compatible, each interface to the ISA bus, such as ISA

Interface logic 101, must respond appropriately to a defined sequence of configuration commands. In Codec 100, microcontroller 103, in conjunction with logic is used to implement the various Plug & Play commands and responses. The end result of a Plug & Play configuration sequence is that the I/O base address decodes, DMA channel selects, and interrupt selects for the various Codec 100 circuit blocks are programmed to specific values.

FIGURE 10 is a diagram emphasizing the configuration/interface logic for a PnP compatible device, for example Plug and Play Interface 106 of Codec 100. Configuration interface 106 includes an address decoder 1001 which receivesaθβnt30l.bιts and 12 address bits from the ISA bus, an address register 1002, linear feedback shift register 1003, plug and play (PnP) registers 1004, output enable circuitry 1005 and register output selector 1006. PnP registers include card control register 1004a, logical device control register 1004b and logical device configuration register 1004c. The theory of Plug and Play operation can now be described in conjunction with FIGURE 10A, and the associated functional diagram of FIGURE 1 1 , assuming Codec 100 is the PnP compatible device under configuration.

After a power-up sequence or hardware reset via RESDRV, Codec 100 is in the Wait_for_Key state. In this state Plug & Play devices monitor writes to address 0x279. Specifically, Linear Feedback Shift Register (LFSR) 1003 is used in hardware to detect a matching byte sequence. If at any time the data written to address 0x279 does not match the LFSR then the LFSR is reset. The cycle continues until an Initialization Key is received. Once the "Key" has been received, microcontroller 103 writes address 0x13 (the P&P State Register) to a 0x1 so that the configuration logic is now in the "Sleep State." FIGURE 10B is a diagram generally illustrating the functional elements of LFSR 1003, including a series of storage/shift elements 1201 and logic 1202. LFSR 1003 also includes logic that enables an additional key sequence to be detected. This additional key sequence is referred to as the "Vendor Key". This Key allows the Plug & Play logic to be bypassed so that Plug & Play configuration registers 1004 may be programmed directly. Plug & Play Key Sequence

6A, B5, DA, ED, F6, FB, 7D, BE

DF, 6F, 37, IB, 0D, 86, C3, 61

B0, 58, 2C, 16, 8B, 45, Al, Dl

E8, 74, 3A, 9D, CE, E7, 73, 39

Vendor Key Sequence

96, 35, 9A, CD, E6, F3, 79, BC

5E, AF, 57, 2B, 15, 8A, C5, E2

FI, F8, 7C, 3E, 9F, 4F, 27, 13

09, 84, 42, Al, DO, 68, 34, 1A In the Sleep State, a P&P device, such as circuitry 1904 waits for a Wake[CSN] command with write data set to 0x00. All accesses to P&P registers 1004 in this state (0x279,0xA79) cause the logic to force IOCHRDY low (hold current bus cycle) and set an appropriate bit in microcontroller Port 1. Once microcontroller 103 reads either address 0x10 or 0x11, the Port I bit is cleared and IOCHRDY is released. After the Wake[CSN] is detected microcontroller 103 sets a serial identifier/resource data pointer to the beginning and writes a 0x2 to microcontroller 103 address 0x13 to transition the logic to the Isolation State.

The first time a Plug&Play device, such as Codec 100, enters the Isolation State, the Read_Data port address is set using a Set_RD_DATA port command. Codec 100 hardware detects this command and latches the Read_Data port address into a register 2004C and uses it to decode accesses to the Read_Data port 901.

Next, 72 pairs of reads are performed to a PnP Serial Isolation register within registers 1004c. The Serial Isolation register holds a 72-bit serial identifier. The 72-bit Serial Identifier is used in identifying and isolating individual Plug & Play devices. Microcontroller 103 uses the transition to the Isolation State to retrieve the first bit of the 72-bit serial identifier and writes this bit to microcontroller address 0x14 bit 0.

The isolation sequence proceeds as follows. If the current bit, of the 72-bit serial identifier, is a one then the logic forces a 0x55 onto the ISA data bus when Read_Data port 910 is read. When Read_Data port 910 is read a second time, then the logic forces a OxAA onto the ISA Data bus. After the Read_Data port is read the second time microcontroller 103 is notified via a bit to Port 1 and the next bit of the serial identifier is written to microcontroller 103 address 0x14 bit 0. This sequence continues until either the logic detects an isolation lose condition or all 72 bits have been read.

Otherwise, if the current bit is a zero, the configuration logic tri-states the ISA data bus buffer and monitors the data on the ISA data bus during a read of the Read_Data port 910. If the logic detects that another P&P device is driving the ISA data bus (i.e. detects a 0x55, OxAA sequence) then the ILS (Isolation lose) bit is set in microcontroller 103 Command/Status register. Upon microcontroller 103 being notified of an Isolation lose the logic is then transitions back to the Sleep State (microcontroller 103 address 0x13=01). If Codec 100 does not lose isolation during the current isolation sequence then a CSN

(Card Select Number) is assigned by the PnP host software. The CSN is a unique value that is assigned to each isolated Plug & Play device. The CSN is used by the host to select individual Plug & Play devices during configuration. Microcontroller 103 stores this CSN in memory and uses it when detecting a Wake[CSN] command. The assigning of the CSN number causes microcontroller 103 to transition to the Configuration State which in turn causes microcontroller 103 to write address 0x13 to a 0x3. Card resource data may only be read while in the Configuration State. A card may get to the Configuration State by one of two methods: in response to "winning" the serial isolation protocol and having a CSN assigned, as discussed above, or in response to receiving a Wake [CSN] command that matches the card's CSN. Only one Plug & Play device is in the Config State at one time. In this state, resource data are retrieved and the host software uses this information to program the corresponding configuration register 2004c. Once the resource data has been accessed then the configuration register 2004c is written and each logical device is activated.

In Codec 100 all accesses to PnP registers 2004 in the Configuration State (write 0x279, write 0xA79, read Read_Data port except resource data reads) result in IOCHRDY being forced low (hold current bus cycle) and the setting ofa bit in microcontroller Port 1 (FIGURE 3, at 101 ).

Once microcontroller 103 reads either address 0x10, 0x1 1, or writes 0x12, respectively, then the particular Port 1 bit is cleared and IOCHRDY is released.

During resource data reads a polled handshake mechanism is used. Logic in Codec 100 outputs a ready indicator when a read from the PnP status register occurs. This ready bit is initially set "not ready" until microcontroller 103 outputs the first byte of a resource data read.

The bit then remains ready until an ISA bus cycle occurs to read the byte. The occurrence of the ISA bus resource data read resets the ready bit to its "not ready" condition. A bit located on Port I (RDR Pl-3 set = one) is used to indicate to microcontroller 103 when the resource data byte has been read. Microcontroller 103 then outputs the next resource byte (microcontroller 103 address-Ox 12) and the RDR bit is reset to zero. Configuration register data are written one logical device at a time. The individual logical device is selected by the Plug&Play Configuration Manager by writing the logical device number to PnP address-0x7. Microcontroller 103 detects this and enables access to the appropriate logical device configuration registers. After all logical devices have been configured logical device activation occurs one logical device at a time. Microcontroller 103 detects this and then sets the appropriate bit in the Logical Device Activate Register (microcontroller 103 address=0xlF). Each logical device is now enabled onto the ISA bus and should respond to the I/O address range, DMA channel, and interrupts that have been defined.

Plug-n-Play requires that the Plug-n-Play device contain data that indicates what system resources it requires. These resources may include memory space, I/O space, DMA channels. or Interrupts. In the case of Codec 100 the resources include a number of system I/O spaces.

DMA channels, and Interrupts. Codec 100 supports two methods (EEPROM loaded, or host downloaded) of storing resource data. Both of these methods are flexible in that the resource data can be customized to support particular requirements.

Plug and Play cards return read-only configuration information in two formats. The serial identifier is returned bit-wise by the Plug and Play devices in response to reads from the Serial

Isolation register. This information is returned in a serial format to facilitate the Plug and Play device selection algorithm described earlier. Plug and Play cards also provide resource data sequentially a byte at a time in response to reads from the Resource Data register. The resource configuration data completely describes all resource needs and options of the device and includes a header followed by a set of resource data structures which end with an End Tag:

The header holds the 72 serial identifier that is used during the Isolation sequence described earlier in TABLE 7. The 32-bit Vendor ID (Bytes 0-3) is an EISA Product Identifier (ID). This ID consists of:

(1) Bits[15:0] are a three character compressed ASCII EISA ID, (Compressed ASCII is defined as 5 bits per character, "00001 "="A" ... " 11010" - "Z". This field is assigned to each manufacturer by the EISA administrative agent); and

(2) bits[31 :16] define a manufacturer specific product number and revision. It is the responsibility of each vendor to select unique values for this field.

The purpose of this field is to serve as a unique board identifier that allows Plug and Play card selection through the isolation algorithm described earlier.

The 32-bit serial number (Bytes 4-7)is used only in the isolation process for selection of individual Plug and Play ISA cards. This unique number differentiates between multiple cards with the same Vendor ID when they are plugged into one system. If this feature is not supported then this field is returned as "FFFFFFFF." Lack of a unique serial number implies that only one instance of a Vendor ID can be supported in a system.

The checksum field (Byte 8) is used to ensure that no conflicts have occurred while reading the device identifier information. The checksum is generated by using LFSR mechanism 1007 shown in FIGURE IOC. LFSR 1007 includes a series of storage/shift elements 1008 and a pair of exclusive-OR (XOR) gates 1009 and 1010. The LFSR resets to 0x6A upon receiving the WAKE[CSN) command. The next shift value for the LFSR is calculated as LFSR[1] XOR LFSR[O] XOR Serial Data. The LFSR value is shifted right one bit at the conclusion of each pair of reads to the Serial Isolation register. The LFSR[7] is assigned the next shift value again described above.

As indicated above, Plug and Play resource data fully describes all resource requirements of a Plug and Play device as well as resource programmability and interdependencies. Plug and Play resource data are supplied as a series of "tagged" data structures. Two types are supported: large items and small items. The first byte defines the type and size and is followed by one or more bytes of actual information. Bit (7) of the first byte is used as the tag identifier to differentiate between small and large data types.

A Plug and Play logical device such as Codec 100 may use any number of resources and any combination of small item or large item data types. The general format is: ( 1 ) Plug and Play version number type;

(2) Identifier string resource type;

(3) Logical device ID resource type which identifies: a) Any compatible device ID resource type for this logical device; b) Resource data types to match what the function uses (IRQ, memory, I/O. DMA)-the order is not important; c) Any dependent functions needed if the Plug and Play card is configurable. The order of the resource data establishes the binding to the configuration registers; (Note: Step 3 is repeated for each logical device present on the Plug and Play card.); and (4) End tag resource type to indicate the end of resources for this Plug and Play card.

The order of resource descriptors is significant because configuration registers are programmed in the same order that descriptors are read. This may be important in some hardware implementations. Further, in the case of Dependent Functions it may be necessary to include null descriptors ("filler") in order to maintain the desired descriptor-to-register mapping regardless of which Dependent Function is programmed by the software.

The 3 -byte Plug & Play Version Number identifies the version of the Plug and Play specification with which the card is compatible. A vendor specific number is included and may be used by a device driver to verify the version of the card. TABLE 8 summarizes these version numbers.

The Identifier String is an ASCII string used to identify the card type or function. This string is displayed to the user during a Plug n Play sequence. Example: "Crystal Semiconductor Codec 100 Sound Chip." TABLE 9 summarizes the ASCII string fields and fields related thereto.

Each logical device must be defined in order for the operating system to be able to allocate resources and identify and load appropriate device drivers. For each logical device the following data structures are required: Logical Device ID

Configuration DMA IRQ

I/O Descriptors ANSI ID String

The following data structures are optional: Start Dependent Functions Best Configuration DMA IRQ

I/O Descriptors Acceptable Configuration DMA IRQ I/O Descriptors

Sub-Optimal Configuration DMA IRQ

1/0 Descriptors End Dependent Functions

Compatible Device ID The Logical Device ID provides a mechanism for uniquely identifying multiple logical devices embedded in a single physical board. The fields of the Logical Device ID are summarized in TABLE 10. The format of the logical device ID is identical to the Vendor ID field discussed above: (1) bits[15:0] - three character compressed ASCII EISA ID) and compressed ASCII is defined as 5 bits per character, "00001" = "A" ... " 1 1010" = "Z". This field must contain a valid EISA ID, although it is not required to have the same 3 letters as the Vendor ID); and

(2) bits[31 :16] - manufacturer-specific function number and revision. It is the manufacturer's responsibility to have unique bits[31 :16] for different functions.

This identifier may be used to select a device driver for the device. Because of this, Logical

Device IDs must be uniquely associated with a specific function. However, there is no need for the Logical Device ID itself to have a unique value, either on a card, or across cards. For instance, a card that implements two communications ports may use the exact same Logical Device ID for both. Similarly, two different products (different Vendor IDs) may both implement the same function, and therefore will use the same Logical Device ID for it. The

Logical Device ID is required on all cards. On single-function cards, the Logical Device ID may be the same as the card's vendor ID.

A compatible device ID provides the IDs of other devices with which the given Plug n Play device (e.g.. Codec 100) is compatible. The host operating system uses this information to load compatible device drivers if necessary. There can be several compatible device identifiers for each logical device. The order of these device IDs may be used by the operating system as a criteria for determining which driver should be searched for and loaded first. TABLE 11 summarizes the fields of the Compatible Device ID. As an example of the use of compatible IDs, consider a card vendor who ships a device with logical ID OxABCDOOOO. At a later date, this vendor ships a new device with a logical ID

OxABCDOOOl . This new device is 100% compatible with the old device but also has added functionality. For this device, the vendor could include the Compatible device ID OxABCDOOOO.

In this case, the exact driver for OxABCDOOOl will be loaded if it can be located. If the driver for OxABCDOOOl can not be found, the driver for device OxABCDOOOO will be loaded for the device. The IRQ data structure indicates that the Plug n Play device uses an interrupt level and supplies a mask with bits set indicating the levels implemented in the device. For a standard ISA implementation there are 16 possible interrupt levels so a two byte field is used. This structure is repeated for each separate interrupt level required. TABLE 12 summarizes the fields of the IRQ data structure.

The DMA data structure, summarized in TABLE 13, indicates that the PnP device uses a DMA channel and supplies a mask with bits set indicating the channels actually implemented in this device. This structure is repeated for each separate channel required.

Each logical device requires a set of resources. This set of resources may have interdependencies that need to be expressed to allow arbitration software to make resource allocation decisions about the logical device. Dependent functions are used to express these interdependencies. The data structure definitions for dependent functions are shown in

TABLE 14.

Start Dependent Function fields may be of length 0 or 1 bytes. The extra byte is optionally used to denote priority for the resource group following the Start DF tag. If the extra byte is not included, this indicates the dependent function priority is 'acceptable'. If the Priority byte is included, the priorities are defined in TABLE 15.

Note that if multiple Dependent Functions have the same priority, they are further prioritized by the order in which they appear in the resource data structure. The Dependent Function which appears earliest (nearest the beginning) in the structure has the highest priority, and so on.

TABLE 16 defines the structure for end dependent functions.

Note that only one End Dependent Function item is allowed per logical device. This enforces the fact that Dependent Functions are not nettable. There are two types of descriptors for I/O ranges. The first type of descriptor is a full function descriptor for programmable ISA cards defined in TABLE 31. The second type of descriptor is a minimal descriptor (Fixed Location I/O Descriptor) for ISA cards with fixed I/O requirements and use a 10-bit ISA address decode. The second type of descriptor is defined in TABLE 17. The first type of descriptor can also be used to describe fixed 1/0 requirements for ISA cards that require a 16-bit address decode (TABLE 18). This is accomplished by setting the range minimum base address and range maximum base address to the same fixed I/O value.

The vendor defined resource data type is for vendor use and is defined in TABLE 19.

34

SUBSTTTUTE SHEET (RULE 26) The End Tag, defined in TABLE 20. identifies an end of resource data. If the checksum field is zero, the resource data are treated as if it checksummed properly. Configuration proceeds normally.

As indicated above, Plug-n-Play organizes physical devices into groups of logical devices. A logical device may be comprised of up to four non-contiguous Memory Address ranges, eight non-contiguous I/O Address ranges, two Interrupts, and two DMA channels. Codec 100 only supports I/O, interrupts, and DMA.

Codec 100 has a fixed physical-to-logical device mapping summarized in TABLE 21. The Plug-n-Play resource data must match the Logical-to-Physical device mapping defined in TABLE 20. Controller 103 firmware translates Plug-n-Play logical device configuration cycles into writes of the appropriate hardware configuration registers.

To support environments in which Codec 100 is located directly on motherboards, a host load mechanism is used to download Plug-n-Play resource data to Codec 100. In this environment the Motherboard BIOS loads the resource data into Codec 100 prior to any Plug-n-Play activity taking place.

To download configuration and Plug-n-Play resource data Codec 100 Control logical device must first be mapped into the host 1/0 space. This is accomplished by sending the Plug-n-Play key sequence described above followed by an isolation and configuration sequence to configure the Control logical device. Once the Control logical device has been mapped then the Plug-n-Play resource data may be loaded into Codec 100 via the Control Port at Control base

+ 5.

For non-motherboard applications and external EEPROM is required to load configuration and resource data into Codec 100. On power-up microcontroller 103 checks for the existence of the EEPROM. If one is found then the EEPROM data, including Plug-n-Play resource data are down loaded from the EEPROM. A description of EEPROM formats that are supported by Codec 100 is discussed in detail below.

In Codec 100 Plug-n-Play compatibility is accomplished through the use of the internal microcontroller 103 and logic gates. Microcontroller 103 interfaces to the external logic through the use of memory mapped registers. These registers control the mapping of the various Codec 100 physical devices as well as provide a means to control the external logic during certain phases of Plug-n-Play sequences.

35

SUBSTTTUTE SHEET (RULE 26) As mentioned immediately above a set of registers is memory mapped into the microcontroller 103 address space. Microcontroller 103 accesses these registers through specific memory access instructions (MOVX). To facilitate hardware test modes of Codec 100, all Plug & Play configuration registers are reset to default values on power-up. These default values will remain intact only if microcontroller 103 is not operating; which is the case for Test Modes 3.

4, 5, and 6 (discussed below). In non-test mode (normal) operation of Codec 100, microcontroller 103 will modify all the configuration defaults to off/disabled states.

FIGURES 12A-12Y are diagrams of the bitfields of the ISA/PNP Configuration registers. FIGURE 12A is a diagram of the bitfields of the Plug & Play Address-Register at microcontroller 103 Address 0x10. This register stores the last 8-bit data value written to the

Plug & Play_Address Register (location 0x279).

FIGURE 12B is a diagram of the bitfields of Plug & Play Write_Data_Port at microcontroller 103 Address 0x11. When this address is read the current data on the ISA data bus is enabled onto the Codec 100 internal data bus. The read is in response to an ISA bus write to the Plug & Play Write_Data register location 0xA79. This register is written by microcontroller

103 during resource data reads.

FIGURE 12C is a diagram of the bitfields of the Plug & Play Read_Data_Register at microcontroller 103 Address 0x12. This register is written by microcontroller 103 in response to a read from the Plug & Play Read_Data_Port. FIGURE 12D is a diagram of the bitfields of the Plug & Play State Register at microcontroller 103 Address 0x13. These bits are updated by microcontroller 103 as a Plug & Play sequence progresses through its various states. The hardware requires these bits in order to effect the appropriate responses during a Plug & Play sequence. The decoding to PS0 and PS 1 fields is shown in Table 22. FIGURE 12E is a diagram of the bitfields of the Plug & Play Control/Status register at microcontroller 103 Address 0x14. This register is reset to zero when RESDRV is high. The decoding is as follows:

Isolation Lose ILS - this bit indicates that the Plug & Play hardware has lost isolation during the current isolation sequence; Serial Identifier/Sound Blaster Busy SID/SBB - this bit is written by microcontroller 103 during an isolation sequence and holds a serialized version of the 72-bit identifier. The hardware uses this bit to determine how the data bus should be driven (0x55/0xAA or tri-state) during a PnP Isolation sequence, as well as during Sound Blaster operation to enable/disable OR'ing of the current SB Busy with the codec playback DMA request; Enable E2PROM EEP - this bit when set to a one enables the Port 1 pins 6 and 7 onto the EDATA[0] and EA[0] pins; and

EA2 Function - when 0 will force XCTLO onto the EA2 pin. When this bit is = 1. then the normal EA2 function is output on the EA2 pin. FIGURE 12F is a diagram of the bitfields of the Sound System Base Address Low at microcontroller 103 Address 0x15. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the 12-bit Sound System Codec base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIGURE 12G is a diagram of the bitfields of the Sound System Base Address High register at microcontroller 103 Address Ox 16. This register is reset to zero when RESDRV is high and is used to specify the upper 4-bits of the 12-bit Sound System Codec base address. FIGURE 12H is a diagram of the bitfields of the Control Base Address Low register at microcontroller 103 Address 0x17. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the 12-bit Control base address. The number of consecutive locations decoded at this base address is fixed at eight bytes.

FIGURE 121 is a diagram of the bitfields of the Control Base Address High register at microcontroller 103 Address 0x18. This register is reset to zero when RESDRV is high and is used to specify the upper 4-bits of the 12-bit Control base address.

FIGURE 12J is a diagram of the bitfields of the Sound Blaster Base Address Low register at microcontroller 103 Address 0x19. This register is reset to zero when RESDRV is high and is used to specify the lower 4-bits of the 10-bit Sound Blaster base address. The number of consecutive locations decoded at this base address is fixed at sixteen bytes.

FIGURE 12K is a diagram of the bitfields of the Sound Blaster Base Address High register at microcontroller 103 Address 0x1 A. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Sound Blaster base address.

FIGURE 12L is a diagram of the bitfields of the Synth Base Address Low register at microcontroller 103 Address OxlB. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the 10-bit Synthesizer OPL3 base address. The number of consecutive locations decoded at this base address is fixed at four bytes. FIGURE 12M is a diagram of the bitfields of the Synth Base Address High register at microcontroller 103 Address OxlC. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Synthesizer OPL3 base address.

FIGURE 12N is a diagram of the bitfields of the MPU-401 Base Address Low register at microcontroller 103 Address Ox ID. This register is reset to zero when RESDRV is high and is used to specify the lower 7-bits of the 10-bit MPU-401 base address. The number of consecutive locations decoded at this base address is fixed at two bytes.

FIGURE 120 is a diagram of the bitfields of the MPU-401 Base Address High register at microcontroller 103 Address Ox IE. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit MPU-401 base address.

FIGURE 12P is a diagram of the bitfields of the Game Port Base Address Low register at microcontroller 103 Address Ox IF. This register is reset to zero when RESDRV is high and is used to specify the lower 5-bits of the 10-bit Game Port base address. The number of consecutive locations decoded at this base address is fixed at eight bytes. FIGURE 12Q is a diagram of the bitfields of the Game Port Base Address High register at microcontroller 103 Address 0x20. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Game Port base address.

FIGURE 12R is a diagram of the bitfields of the CDROM Base Address Low register at microcontroller 103 Address 0x21. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the I/O-bit CDROM base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIGURE 12S is a diagram of the bitfields of the CDROM Base Address High register at microcontroller 103 Address 0x22. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit CDROM base address. TABLE 23 describes the bit decodings for the interrupt select registers depicted in

FIGURES 12T-12Y, and discussed below, where IRQA-IRQE describe the interrupt pins enabled by the interrupt mapping value written into the given register.

FIGURE 12T is a diagram of the bitfields of the Synth Interrupt Select register at microcontroller 103 Address 0 x 23. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Synthesizer interrupt is mapped. FIGURE 12U is a diagram of the bitfields of the Sound Blaster Interrupt Select register at microcontroller 103 Address 0x24. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Sound Blaster interrupt is mapped.

FIGURE 12V is a diagram of the bitfields of the Sound System Interrupt Select register at microcontroller 103 Address 0x25. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Synthesizer interrupt is mapped.

FIGURE 12W is a diagram of the bitfields of the MPU-401 Interrupt Select register at microcontroller 103 Address 0x26. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the MPU-401 interrupt is mapped. FIGURE 12X is a diagram of the bitfields of the CDROM Interrupt Select register at microcontroller 103 Address 0x27. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the CDROM interrupt is mapped.

FIGURE 12Y is a diagram of the bitfields of the Control Interrupt Select register at microcontroller 103 Address 0x28. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Control interrupt is mapped.

Microcontroller 103 I/O port 1 (FIGURE 3) is a ISA bus monitoring port. The data present on the I/O port 1 pins indicates to microcontroller 103 what is happening on the ISA Bus as far as Plug & Play register accesses are concerned. Once Codec 100 has made a transition out of the Wait for-Key State then Port 1 is polled for Plug & Play register accesses. FIGURE 13 defines PnP Port 1, where:

AWR- Address Write Pending - when set to a one indicates that a write to the PnP Address Register(0x279) has occurred. When this bit is a one during Sleep and Configure states, IOCHRDY will be forced high, effectively holding the current ISA bus cycle until microcontroller 103 has accessed microcontroller 103 address Ox 10. This bit is cleared to zero upon a read of microcontroller 103 address

0X10.

DWR-Data Write Pending - when set to a one indicates that a write to the PnP

Data Write Register has occurred. When this bit is a one during Sleep and

Configure states, IOCHRDY WILL be forced high, effectively holding the current ISA bus cycle until microcontroller 103 has accessed microcontroller 103 memory address 0x11. This bit is cleared to zero upon a read of microcontroller 103 memory address Ox 11.

DRD-Data Read Pending - when set to a one indicates that a read from the PnP Read Data Port has occurred. This bit is cleared to zero upon a write to microcontroller 103 address 0x12 or during an Isolation sequence by a write to microcontroller 103 address 0x14.

KEY/RDR - Key Resource Data Read - When Codec 100 is in a WAIT_FOR_KEY state and a "PnP Key" or "Crystal Key" sequence (discussed above) is detected, microcontroller 103 is interrupted via INTO. This bit then indicates what "Key" was detected. KEY = 0 for "PnP Key" and KEY = 1 for

"Crystal Key". Alternately during a Resource Data Read sequence this bit when set to a one indicates that the current resource data byte has been read and that the ISA interface is ready for the next byte. This bit is cleared to zero upon a write to microcontroller 103 address 0x12. This bit is also set when a "Crystal Key Sequence" has been received.

For applications that do not require Plug-n-Play capability the "Crystal Key" backdoor mechanism may be used to program the configuration of Codec 100. Each Codec 100 logical device is configured one at a time. The configuration data must match or be a subset of the logical device definition described above. All commands including the "Crystal Key" sequence are written to the Plug-n-Play port at ISA Bus address 0x279. The following commands are used in performing a configuration sequence.

Typical Programming Sequence bypassing the PnP interface is as follows: Program Start: Send Crystal Key Select Logical Device

Program I/O Base 0 Program I/O Base I - if required Program I/O Base 2 - if required Program Interrupt - if required Program DMA 0 - if required Program DMA 1 - if required Activate Logical Device Select Logical Device Program I/O Base 0 - if required

Program I/O Base 1 - if required Program I/O Base 2 - if required Program Interrupt - if required Program DMA 0 - if required Program DMA 1 - if required

Activate Logical Device

Select Logical Device

Program I/O Base 0 - if required

Program 1 10 Base 1 - if required

Program I/O Base 2 - if required

Program Interrupt - if required Program DMA 0 - if required

Program DMA 1 - if required Activate Logical Device Activate Card Program End:

The instructions and commands in the foregoing exemplary programmed sequence can ribed as follows:

Send Crystal Key - The "Crystal Key" is not a command but a sequence of 32 bytes that are written in succession. When Codec 100 receives the correct sequence of 32 bytes the Plug-n-Play logic of Codec 100 transitions to the Configuration State. The configuration registers of Codec 100 may only be modified when Codec 100 is in the Configuration State. Program the CSN (Card Select Number) 0x6 - The CSN number for Codec 100 may optionally be programmed by executing this command. This command is executed by writing a 0x6 followed by the 8-bit CSN number. If this command is not used then the CSN number for Codec 100 will default to zero. Select Logical Device (Ox 15) - The configuration registers of Codec 100 are programmed one logical device at a time. This command is executed by writing a 0x15 followed by an 8-bit logical device number. Codec 100 supports eight physical devices (0:7) as previously noted.

IO Port Base Address 0 (0x47) - This command is executed by writing a 0x47 followed by a write of the low byte of the I/O base address, and a write of the high byte of the I/O base address. IO Port Base Address 1 (0x48) - This command is executed by writing a 0x48 followed by a write of the low byte of the I/O base address, and a write of the high byte of the I/O base address. IO Port Base Address 2 (0x42) - This command is executed by writing a 0x42 followed by a write of the low byte of the I/O base address, and a write of the high byte of the I/O base address. Interrupt Select 0 (0x2A) - This command is executed by writing a 0x22 followed by a write of the interrupt line to generate an interrupt on. Interrupt Select 1 (0x27) - This command is executed by writing a 0x27 followed by a write of the interrupt line to generate an interrupt on. DMA Select 0 (WA) - This command is executed by writing a 0x2A followed by a write of the DMA channel that is to be used. DMA Select 1 (0x25) - This command is executed by writing a 0x25 followed by a write of the DMA channel that is to be used.

Activate Logical Device (0x33) - This command is executed by writing a 0x33 followed by a byte of one to activate the currently selected logical device. Deactivate Logical Device (0x33) - This command is executed by writing a 0x33 followed by a byte of zero to deactivate the currently selected logical device. Activate Codec 100 (0x79) The configuration data are processed and transferred to the appropriate Codec 100 registers upon execution of this command. This command puts Codec 100 into the Wait_For_Key_State.

42

SUBSTTTUTE SHEET (RULE 26) Once a Plug & Play sequence has transpired, each logical device, including Codec 100, will have an I O base address assigned to it. This assigned base address is stored in the I/O base address register. ISA bus address bits A12...A0 are compared with the values stored in the I/O base address registers, and if a match is found, then the appropriate logical device is selected for access. Each physical device occupies a number of consecutive byte locations. TABLE 24 sets out the address decoding for a selected number of PnP devices, including Codec 100. For 9-bit decodes Al 1..A10 are assumed to be zero.

Because the ISA bus provides 16-bit address for I/O decoding, the Codec 100 10-bit and 12-bit decoded address ranges will alias into the upper addresses due to the fact that address bits [A15..A11] and [Al 5.. A 13] are not decoded. Normally this is not a problem, but it could be for some mother board manufacturers. In order to prevent the address decoding from aliasing, Codec 100 supports a mode where by the high order address bits (A 15. A 12) are input via CDROM interface 120. CDROM/Modem interface 120 is not available in this mode. The address bits A15..A12 are then decoded along with [Al 1..A10] to generate logical device selects for Sound System and Codec 100 registers. A valid logical device decode occurs when bits [A 15.. A 12] are equal to [0,0,0,0] and bits [A11..A0] match one of the current programmed base address registers. For all other address decodes, bits A15.A10 are decoded along with bits [A.9..A0] to generate device selects. A valid logical device decode occurs when [A15..A10] are equal to [0,0,0,0,0,0] and [A9..A0] match one of the current programmed base address registers. The 16-bit address decode function is selected by the XIOR pin being high at the time the

RESDRV pin transitions from a high to low.

Several user defined registers are available in the Card Level Vendor Defined area specified by Plug and Play ISA Specification Version 1.0a.

The RAM Access Register at address 0x28 will allow the host to access program RAM in the similar access through the Control Registers but using PnP ADDRESS, WRITE_DATA and READ_DATA ports instead of Control ports (Control Base + 5 and Control Base +6). All control port accessible commands are available with this access method. The JUMP_TO_ROM (57h) command should not be used through this PnP method nor should mixing of control port and PnP accesses be mixed, e.g. a PnP HOLD and a control port GO. A separate PnP JUMP TO ROM command is provided. The following is a typical sequence to access the RAM:

1 ) Write an 0x28 to the ADDRES S port; 2) Write a relevant function byte to the WRITE_DATA port (such as 0x55 for disable PnP, 0x56 for disable Crystal key, 0x5A for update, OxAA for RAM write/read, etc.) (For RAM write/read only, steps 3 and 4 are needed.);

3) Write a low byte and high byte of the RAM starting address to the WRITE_DATA port and then write/read the data to/from the

WRITE_D ATA/READ-DATA port; and

4) Finally execute a RAM END command to finish the RAM write/read. The RAM END Register 0x2 A allows the host to execute a RAM END by:

1 ) Writing an 0x2 A to the ADDRESS port; and 2) Then writing an 0x00 to the WRITE_D ATA port.

The RAM JUMP TO ROM Register 0x2B forces code jump to a tight loop in ROM:

1 ) Write an 0x2B to the ADDRESS port; and

2) Then write an 0x57 to the WRITE_DATA port.

The Chip "Black_out" Register 0x2F causes the chip to enter into "Black_out" state, which will shut down all activated logical devices, cause PnP and Crystal keys to be disabled and force the part go into WAIT_FOR_KEY state.

FIGURES 14A-14D are diagrams of the bitfields of the DMA Channel Select Registers, the bits in each of these registers operate as shown in TABLE 25, where DMA-A to DMA-D are the four available DMA channels enabled. FIGURE 14A is a diagram of the bitfields of the Sound Blaster DMA Channel Select registers at microcontroller 103 address 0x29. This register is reset to zero when RESDRV is high and is used to specify one of the four ISA DMA channels to which the Sound Blaster DMA signals is mapped.

FIGURE 14B is a diagram of the bitfields of the Sound System Playback/Capture DMA Channel Select registers at microcontroller 103 address 0x2A. This register is reset to zero when

RESDRV is high and is used to specify one of four the ISA DMA channels to which the Sound System Playback/Capture DMA signals is mapped

FIGURE 14C is a diagram of the bitfields of the Sound System Capture DMA Channel Select register at microcontroller 103 address 0x2. This register is reset to zero when RESDRV is high and is used to specify one of the four ISA DMA channels to which the Sound System

Capture DMA signal is mapped. FIGURE 14D is a diagram of the bitfields of the CDROM DMA Channel Select register at microcontroller 103 Address 0x2C. This register is reset to zero when RESDRV is high and is used to specify one of the four ISA DMA channels to which the CDROM DMA signal is mapped. FIGURES 15 A- 15 J are diagrams of the bitfields of miscellaneous registers.

FIGURE 15A is a diagram of the bitfields of the Alternate CDROM Base Address Low register at microcontroller 103 Address 0x2D. This register is reset to zero when RESDRV is high and is used to specify the lower 8-bits of the 10-bit CDROM base address. The number of consecutive locations decoded at this base address is fixed at four bytes. FIGURE 15B is a diagram of the bitfields of the Alternate CDROM Base Address High registers at microcontroller Address 0x2E. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit CDROM base address.

FIGURE 15C is a diagram of the bitfields of the Physical Device Activation Register at microcontroller 103 Address 0x2F. This register is used to enable specific physical devices after the configuration registers have been programmed. Each bit set equal to a one will enable the particular physical device as shown in TABLE 26. A value of zero will disable the corresponding physical device. When disabled, a particular physical device is physically disconnected (I/O base address, Interrupt and DMA) from ISA bus interface 101.

FIGURE 15D is a diagram of the bitfields of the Modem Base Address Low register at microcontroller 103 Address 0x30. This register is reset to zero when RESDRV is high and is used to specify the lower 8-bits of the 10-bit Modem base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIGURE 15E is a diagram of the bitfields of the Modem Base Address High register at microcontroller 103 Address 0x30. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Modem base address.

FIGURE 15F is a diagram of the bitfields of the Alternate CDROM Mask Register at microcontroller 103 Address 0x32. The CDROM Address Mask Register provides a means to vary the number of consecutive byte locations that a secondary CDROM I/O decode may occupy.

Each mask bit is used to prevent specific address bits from being decoded in generating the secondary CDROM I/O decode. The valid bit combinations are as shown in TABLE 27.

FIGURE 15G is a diagram of the bitfields of the Modem Mask Register at microcontroller 103 Address 0x33. The Modem Address Mask Register provides a means to vary the number of consecutive byte locations that the modem decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the modem I/O decode. The valid bit combinations are as shown in TABLE 28.

FIGURE 15H is a diagram of the bitfields of the Miscellaneous Control Bits register at microcontroller 103 Address 0x34. A description of these bits is as follows:

PCDLNT - Polarity CDROM Interrupt specifies polarity of CDROM interrupt input:

0 = CDROM interrupt is active low; and

1 = CDROM interrupt is active high. PSINT - Polarity Synthesizer Interrupt specifies the polarity of synthesizer interrupt input:

0 = synthesizer interrupt is active low; and

1 = synthesizer interrupt is active high.

PMINT - Polarity Modem Interrupt specifies the polarity of modem interrupt input:

0 = modem interrupt is active low; and

1 = modem interrupt is active high. XBUF - Transceiver buffer control:

XBUF = 0 Codec drives data bus on reads of CDROM addresses; and XBUF = 1 Codec tri-states data bus on reads of CDROM addresses.

SD7DE - SD7 Disable:

SD7DE 0 = SD7-SD0 driven during reads of CDROM Alternate Base + 1 SD7DE 1 = SD7 tri-stated, SD6-SD0 driven during reads of CDROM Alternate Base +1. FIGURE 151 is a diagram of the bitfields of the Modem Interrupt Select register at microcontroller Address 0x35. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Modem interrupt is mapped.

FIGURE 15 J is a diagram of the bitfields of the Physical Device Activity Register at microcontroller address = 0x36. Each bit indicates that an ISA Bus access (read or write)to a particular physical device has occurred. The bit is set upon an ISA read or write access to one of eight physical devices as shown in TABLE 29. All bits are reset to zero upon an

46

SUBSTTTUTE SHEET (RULE 26) microcontroller 103 read of the register. In addition any DMA activity to the codec (PDACK,CDACK=0) also sets the Sound System (DAO) and Sound Blaster (DA6) bits.

FIGURE 16 is a diagram of the bitfields of the Wavetable and Serial Control Register at microcontroller address 0x40. This register Reset to zero when RESDRV = 1. The specific bitfields can be described as follows:

SBSP Sound Blaster Swap Playback - when this bit is set to a zero the current ordering of samples for DMA playback are swapped, relative to the current defined format.

This bit affects only 8-bit playback in Sound Blaster mode.

SBSC Sound Blaster Swap Capture - when this bit is set to a one, the current ordering of samples for DMA capture are swapped, relative to the current defined format.

This bit affects only 8-bit capture in Sound Blaster mode, res Reserved

WTEN Wave Table Enable - When this bit is set to a one, the XD7:XD5 pins are switched to support a digital wavetable interface. When this bit is a zero the XD7:XD5 pins operate normally. TABLE 30 describes the decoding of the WTEN bit.

SPS Serial Port Switch - When this bit is set to a one, and the SPE bit in register 116 is set to a one, the DSP serial port pins are switched from the second joystick pins to the XD pins. If SPS is a zero and the SPE bit in register 116 is set to a one the DSP serial port pins are routed to the second joystick pins. If the SPE bit in register 116 is a zero then the serial port pins do not appear anywhere. TABLE 31 describes the functioning of the SPS bit.

MCLKDIS When this bit is set to a one, and the wavetable serial interface is enabled by WTEN = 1 , the MCLK pin to the wavetable device is synchronously forced to zero. MCLK will remain a zero until MCLKDIS is set to zero. At this time MCLK will synchronously be enabled. BRESET When this bit is set to a one the BRESET pin is forced to zero. This is to allow microcontroller 103 and host control of external devices connected to the BRESET pin.

FIGURE 17 is a diagram of the bitfields of microcontroller address 0x41. (Reset to 0x00). The bitfields are decoded in TABLE 32 as follows:

47

SUBSTTTUTE SHEET (RULE 26) FIGURE 18 is a diagram of the bitfields of the Port 3 Shadow Register at microcontroller address 0x42. The bitfields of this register function as follows:

P3.0 - UP - This bit follows the state of Codec 100 UP pin when VCEN is set. P3.1 - DOWN - This bit follows the state of Codec 100 Down pin when VCEN is set. P3.2 - MUTE - This bit follows the state of Codec 100 Mute pin when VCEN is set.

P3.3 - REQUEST - This field is set to a one to update codec registers that may be in contention with ISA bus accesses (WSS mode). After polling for GRANT =1, microcontroller 103 may access codec registers as needed. After microcontroller 103 has finished its codec accesses, the REQUEST bit should be set to zero to re-enable ISA access to the codec registers.

P3.4 - GRANT - This bit is polled by microcontroller 103 after setting the REQUEST bit =1. When GRANT is equal to one, microcontroller 103 may access codec registers without contention with the ISA bus. When GRANT =1 and subsequent ISA codec accesses are held off via IOCHRDY (discussed below in conjunction with FIGURE 19) until the REQUEST bit is set to zero by microcontroller 103.

P3.5 - Codec INT - Read Only. This bit follow the state of the internal codec interrupt signal. External EEPROM

As mentioned above, an external EEPROM is typically for all Codec 100 environments. The EEPROM is coupled to Codec 100 through the EEPROM interface circuitry of block 109.

The EEPROM is used for specifying configuration data that is used in setting up Codec 100 operation, Plug-n-Play resource data, and RAM patch data. The EEPROM supports two modes of operation which will be discussed in detail below. The mode identifiers are shown in TABLE 33. FIGURE 19 emphasizes the circuitry of the EEPROM interface. Refer to FIGURE 20 for a flow chart of a detect/load EEPROM sequence.

The existence and type of EEPROM is determined by two bytes that are located in the first two locations of the EEPROM memory. On power-up, Codec 100 looks for the existence of these two bytes via the EEPROM interface. If the first two EEPROM locations are found to contain these matching bytes then Codec 100 will load the EEPROM data into Codec 100 internal memory. How the EEPROM data are interpreted and acted upon is determined by the defined EEPROM mode.

48

SUBSTTTUTE SHEET (RULE 26) The first mode of operation assumes that a compatible EEPROM exists. The EEPROM data format for this mode is defined in TABLE 34. The data supports specification of Peripheral Port address length, mapping of interrupt and DMA pins to specific ISA bus lines, and definition of Plug-n-Play resource data. Upon a power-up reset the EEPROM data will be copied into Codec 100 RAM starting at address 0x400C. The additional configuration data needed (0x4000 to 0x400B) will have been copied from ROM defaults to RAM (as the result of a power-on reset) before the EEPROM is detected. The contents of the RAM will then be used to update the hardware (TABLE 34).

The Data Length Bytes (2,3) specify the total length of data contained in the EEPROM not including the two validation bytes or the two data length bytes themselves.

The External Peripheral Port I/O Decode Address Length Byte (4) determines which devices connected to the External Peripheral 109 Port may require an I/O decode address length of four or eight:

0x00 = I/O Length Four Bytes; and 0x08 = I/O Length Eight Bytes

The Mixer Input Mapping Byte (5)(default 0x40) determines what physical devices are connected to the various mixer inputs. TABLE 35 described the available selections.

The Interrupt Selection A,B Bytes (6)determine what physical ISA Bus interrupt pin is connected to the IRQA and IRQB pins of Codec 100. The available connections are shown in TABLE 36.

C,D, Byte (7) determines what physical ISA Bus interrupt pin is connected to the IRQC and IRQD pins of Codec 100. TABLE 37 shows the possible connections.

The Interrupt Selection E,F, Byte (8) determines what physical ISA Bus interrupt pin is connected to the IRQD and IRQE pins of Codec 100. The possible connections are described in TABLE 38.

The DMA Selection A,B Byte (9) determines what physical pair of ISA Bus DMA pins are connected to the DRQA, DRQB and DACKA, DACKB pins of Codec 100. TABLE 39 describes the available connections.

The DMA Selection C Byte (A) determines what physical pair of ISA Bus DMA pins are connected to the DRQA, DRQB and DACKA, DACKB pins of Codec 100. TABLE 40 describes the available connections.

49

SUBSTTTUTE SHEET (RULE 26) Bytes 1 1 through L are reserved for Plug-n-Play resource data. The^' format of the Plug-n-Play data are described above.

Codec 100 EEPROM resource data format for the second mode in TABLE 33 is shown in TABLE 41. The data is copied into Codec 100 RAM memory and the hardware will be updated based on the stored RAM values. The identification word for this format is 0xBB55.

The fields of address mask register/alternate CDROM base address register (Byte 4) is depicted in FIGURE 21 A. The CDROM Address Mask Register provides a means to vary the number of consecutive byte locations that the secondary CDROM I O decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the secondary CDROM I/O decode. The valid bit combinations are as shown in TABLE 42. All other combinations are invalid and may cause erroneous operation.

The bitfields of Address Mask Register Modem (Byte 5) are shown in FIGURE 21 B. The Modem Address Mask Register provides a means to vary the number of consecutive byte locations that the modem decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the modem I/O decode. The valid bit combinations are as shown in TABLE 43. All other combinations are invalid and may cause erroneous operation. The Miscellaneous Configuration Bits, Byte 6. are shown in FIGURE 21C. Where: PCDINT - Polarity CDROM Interrupt bit specifies polarity of CDROM interrupt input: 0 = CDROM interrupt is active low; and 1 = CDROM interrupt is active high.

PSINT - Polarity Synthesizer Interrupt bit specifies poiarity of synthesizer interrupt input:

0 = synthesizer interrupt is active low; and

1 - synthesizer interrupt is active high.

CKD - Crystal Key Disable bit controls response of Codec 100 to the Crystal Key Sequence:

CKD 0 = Enable - Codec 100 will Respond to Crystal Key; and PKD 1 = Disable - Codec 100 will NOT Respond to Crystal Key. PKD - Plug-n-Play Key Disable bit controls response of Codec 100 to the PnP Key Sequence: PKDO = Enable - Codec 100 will Respond to Pnp Key; and

PKD1 = Disable - Codec 100 will NOT Respond to PnP Key. RES - Reserved, always defined as zero (0);

50

SUBSTTTUTE SHEET (RULE 26) PMINT - Polarity Modem Interrupt bit specifies polarity of modem interrupt input:

0 = modem interrupt is active low; and

1 = modem interrupt is active high. XBUF - Transceiver buffer control: XBUF = 0 drives data bus on reads of CDROM addresses; and

XBUF = I tri-states data bus on reads of CDROM addresses. SD7DE - SD7 Disable:

SD7DE 0 - SD7-SDO driven during reads of CDROM Alternate Base + 1 ; and SD7DE 1 = SD7 tri-stated, SD6-SDO driven during reads of CDROM Alternate Base +1.

FIGURE 21D defines the bitfields of the Misc. Configuration Bits, Byte 7. This byte is copied to microcontroller 103 addresses 0x4002 on powerup and 0x34 on powerup or PNP JPDATE command.

VCEN - Volume Control Enable - This bit is copied to the corresponding VCEN bit in microcontroller 103 register 0x34. The Firmware also uses this bit to enable up/down/mute external pushbutton volume control.

The Global Configuration Byte,Byte 8 is depicted in FIGURE 21E and is copied to

0x4003 on powerup. The actions taken based on the data in this byte occur at powerup in the

EEPROM case and during a PNP_UPDATE command in the case of a host resource data shoot. NOTE: All defined bits other than D3 and D2 in register 0x40 are preserved. The bit decoding is as follows:

Reserved - These bits are reserved for future use and should be set to zero; SPS - Serial Port Switch - This bit is copied to the corresponding SPS bit in microcontroller 103 register 0x40; WTEN - Wave Table Enable - This bit is copied to the corresponding WTEN bit in microcontroller 103 register 0x40;

AIDIS - Alternate Input Disable - This bit, when set, will cause SB initiated writes to registers 118. 119 to NOT be mapped to X0, XI if IFM or WTEN are set; VCF0 - This bit. along with the VCF1 bit, is used to specify which volume control button scheme is used;

VCF1 - This bit, along with the VCF0 bit, is used to specify which volume control button scheme is used; and

51

SUBSTTTUTE SHEET (RULE 26) IFM - When this bit is set to a one the internal FM synthesizer is enabled.

Firmware Revision information bytes are used by the host to identify which patch is present in the part and what patch options are set.

Features Byte indicates major feature sets of the embedded microcode. Each bit in this byte represents a feature or feature set.

Firmware REVISION at 0x41BE byte indicates the current revision of the embedded microcode patch and is written 0x22 on powerup.

The Logical -to-Physical Device Mapping, Bytes 8-15, are used to map Logical Devices to Physical Devices. Each Logical Device has a byte associated with it. To map physical devices into a particular logical device a one is programmed into the corresponding bit location. TABLE

44 defines the mapping. The physical device bits are mapped the same as the Physical Device Activation register. As an example, to define Logical Device 0 as Sound System/Sound Blaster/Synth, Byte 0 should be written as a 0x43 to mapped the three physical devices to Logical Device 0. Codec 100 EEPROM may also optionally include RAM patch data starting at offset L+l and continuing to N (max = 0x43FD).

Because all implementations of Codec 100 will require either a host resource load or EEPROM, the default (ROM) resource data and configuration has been minimized to save code space and therefore does not contain a full set of Plug-n-Play resource data. However, without an EEPROM. using the default ROM data, Codec 100 will still be able to participate in a PnP or Crystal Key sequence but will have no resource data to report. An example of this feature follows:

Codec 100 ROM RESOURCE DATA

;** BEGIN Codec 100 RESOURCE DATA NEW_KEY:

; EEPROM Validation Bytes

DB 055H, 0BBH ; EEPROM Validation Bytes

DB 000H ; EEPROM data length upper byte

DB 02CH ; lower byte, Listed Size of Resource = 44

52

SUBSTTTUTE SHEET (RULE 26) USER_DATA:

; Hardware Configuration Data (Resource Header)

DB 000H Address Mask - CDROM

DB 003H Address Mask - Modem

DB 080H Misc Config bits

DB 000H Reserved

DB 043H Reserved

DB 020H Reserved

DB 004H Reserved

DB 008H Reserved

DB 010H Reserved

DB 080H Reserved

DB 000H Reserved

DB 000H Reserved D DBB 0 00000HH ; 00 = 4/08 = 8 peripheral port size, XCTL0 XA2

DB 048H LINE, AUX1, AUX2 mapping - RESERVED

DB 075H IRQ selection A & B - B = 7, A = 5

DB 0B9H IRQ selection C & D - D = 1 1, C = 9

DB 0FCH IRQ selection E & F - F = 15, E = 12 D DBB 0 01100HH ; DMA selection A & B - B = 1, A = 0

DB 003 H DMA selection C - C = 3 ; PnP Resource Header - Starts with Crystal PnP ID for Codec 100 IC

DB 00EH, 063 H, 0A2H, 032H, 0FFH, OFFH, 0FFH, OD4H ; CSCS 232 FFFFFFFF DB 00AH, 01 OH, 002H ; PnP version 1.0, Vender version 0.2

DB 082H, 008H, 000H. 'Codec 100', 000H ; ANSI ID DB 079H, 03 fH ; End of Resource Data, Checksum

;** END Codec 100 RESOURCE DATA

As shown in FIGURE 19, Codec 100 interfaces to an external EEPROM device via Peripheral Port Interface 109. The actual pins used are as follows. The XDO pin connects to the EEPROM data pin and the XA0 pin connects to the EEPROM address pin. To XDO pin is open-collector and therefore requires a 5K pull-up resistor. The interface is designed to be compatible with a variety of EEPROM devices that are I²C compatible.

The EEPROM is accessible via microcontroller 103 microcontroller and directly via the ISA bus via multiplexer 1901 and read drivers 1902.

Microcontroller 103 access to the EEPROM is enabled via the EPP bit in the Plug-n-Play Control/Status Register (microcontroller 103 address = 0x14). When the EPP bit is equal to one

53

SUBSTTTUTE SHEET (RULE 26) microcontroller 103 Port 1 pins 6 and 7 are enabled onto the XDO and XAO pins respectively. The only time in which microcontroller 103 enables access to the EEPROM is after a Codec 100 reset (RESDRV = 1 or PD1,PD0 = 10). In this instance, as part of a initialization sequence, microcontroller 103 checks for the existence of an EEPROM device. If a compatible EEPROM is found then its contents are loaded into Codec 100. Microcontroller 103 only reads EEPROM devices it does not have the ability to write EEPROM devices. Writing of the EEPROM is accomplished by using the ISA Bus EEPROM access port via Codec 100 Control Base + 1 register. The timing of the data and clock signals are determined by microcontroller 103 ROM code. The timing relationship between the clock and data are shown in FIGURE 22A. The state of the data line can change only when the clock line is low. A state change of the data line during the time that the clock line is high is used to indicate start and stop conditions.

Codec 100 supports a single EEPROM up to 2K bytes. EEPROM device read access is shown in FIGURE 22B. The timing follows that of a random read sequence. Prior to issuing the slave address with the R/W bit set to a one, Codec 100 first performs a "dummy" write operation. Codec 100 first generates a start condition followed by the slave device address and the byte address of zero. The slave address is made up of a device identifier (OxA) and a bank select (bits A2..A0) which are always zero. Codec 100 always begins access at byte address zero and continues access a byte at a time. The byte address automatically increments by one until a stop condition is detected. ISA Bus access to the EEPROM is enabled via the DATALN bit in Codec 100 Control

Base+1 register. When the DATALN bit is set to a one then the CLOCK and DATAOUT bits are enabled on to the XAO and XDO pins respectively. The timing of the clock and data signals is completely determined by the host based software program and should be the timing requirements shown in FIGURE 28. It should be noted that in order to read back data from the EEPROM device, the DATAOUT bit must be set to a one.

SOUND BLASTER

The Sound Blaster/MPU-401 to microcontroller 103 interface 2300 is shown in FIGURE 23A and consists of a number of data latches 2301 and transceivers 2302 that are used to send and receive data between ISA bus 130 and microcontroller 103. The particular ISA Bus base I O addresses, as defined by the Plug & Play configuration data, are decoded by ISA address decoder

2303. When a ISA Bus generated read/write occurs to a Sound Blaster or MPU-401 device then an interrupt (active low) is generated on the LNT1 TRO input of microcontroller 103

54

SUBSTTTUTE SHEET (RULE 26) (FIGURE 3). At the same time the ISA Bus IOCHRDY line is driven low to force the current ISA BUS cycle to wait. Data are put on PORT1 to indicate to microcontroller 103 what ISA Bus access has generated the interrupt microcontroller 103 then performs a read or write of the ISA Data Port depending on the current cycle type (read/write). The trailing edge of microcontroller 103 read/write strobe tri-states (releases) the IOCHRDY line and the current ISA cycle is allowed to complete.

It is not required in all cases for microcontroller 103 to access the ISA Data Port immediately after receiving an interrupt. Microcontroller 103 may perform a number of processing tasks, while IOCHRDY holds off the ISA Bus, before the access to the ISA Data Port occurs which releases IOCHRDY. However the amount of time in which IOCHRDY is asserted should be keep to a minimum to minimize the impact on system performance.

The Plug & Play block 106 maps the Sound Blaster functions into the ISA environment. The Sound Blaster I/O map is shown in TABLE 45. The FM registers addresses 0-3 and 8-9 are maps to a synthesizer connected externally to Codec 100 via the External Peripheral Port 109. The Mixer Address and Data registers are mapped into the codec mixer by microcontroller 103.

The DSP registers are used to send receive Sound Blaster commands and data from microcontroller 103. Addresses OxB, OxD, and OxF are aliases from addresses OxA, OxC, and OxE respectively. Unused bits (6..0) at addresses OxC, OxD, OxE, and OxF are mapped to bits 6..0 in latch at address OxA, B. The Sound Blaster digital audio DMA functions are supported by the Windows Sound

System codec (external to Codec 100). It should be noted that in the Sound Blaster mode (via a context switch) Codec 100 swaps the left right samples in the codec (capture and playback) so that they match the Sound Blaster standard.

The Sound Blaster mixer functions are mapped into codec mixer 204. This mapping is illustrated in FIGURE 31 and TABLE 46.

The mixer data are buffered by microcontroller 103 into internal memory. Then, during a time in which Codec 100 is holding the ISA bus via IOCHRDY, the appropriate codec mixer writes are done to affect the mixer change. This is done because microcontroller 103 cannot access the codec registers while DMA audio is being transferred to the codec 100. While IOCHRDY is asserted DMA activity to codec 100 is suspended and the Sound Blaster mixer registers are shadowed by microcontroller 103. The Input Filter, DNF1, and VSTC (mono/stereo) bits do not have a codec equivalent function and therefore are don't cares.

55

SUBSTTTUTE SHEET (RULE 26) Sound Blaster Mixer accesses operate as follows: Mixer Write

1. An ISA Bus write occurs to Sound Blaster Mixer Address Register (Base +5);

Codec 100 drives IOCHRDY low to hold bus. Data are put on PORT1 and a microcontroller 103 interrupt is generated; microcontroller 103 reads the ISA Data Port (External RAM address = 0) and stores address value in local memory; and

IOCHRDY is released and the ISA Bus cycle completes.

2. An ISA Bus write occurs to Sound Blaster Mixer Data Register (Base +6); Codec 100 drives IOCHRDY low to hold bus, data are put on PORT1 and a microcontroller 103 interrupt is generated; microcontroller 103 reads ISA Data Port (External RAM address-0) and stores data value in local memory; and

IOCHRDY is released and the ISA Bus cycle completes. 3. Microcontroller 103 then writes codec 100 registers to perform mixer function that was specified.

Mixer Read

1. An ISA Bus write occurs to Sound Blaster Mixer Address Register (Base +5);

Codec 100 drives IOCHRDY low to hold bus, data are put on PORT1, and a microcontroller 103 interrupt is generated: microcontroller 103 reads ISA Data Port (External RAM address = 0) and stores addressed value in local memory; and

IOCHRDY is released and the ISA Bus cycle completes.

2. An ISA Bus read occurs to Sound Blaster Mixer Data Register (Base +6); Codec 100 drives IOCHRDY low to hold bus, data are put on PORT1, and microcontroller 103 interrupt is generated; microcontroller 103 writes Mixer Data Latch (External RAM address = 0) with shadow Sound Blaster mixer register contents; and

IOCHRDY is released and the ISA Bus cycle completes. Sound Blaster interface 2300 further includes uses a hardware handshake mechanism

2304 for processing commands. The mixer does not use a handshake mechanism and is always

56

SUBSTTTUTE SHEET (RULE 26) assumed to be available for ISA bus accesses. Two handshake bits are used: Command Busy, and Data Available. The Command Busy is located in the Write Buffer Status Register (bit 7). The Data Available bit is located in the Data Available Status Register (bit 7). The Command Busy bit indicates when microcontroller 103 is busy processing a command. The Data Available bit is used to indicate when microcontroller 103 has responded to a command with some data.

The handshake works as follows:

1. The Command Busy bit is generated by the logical OR of two independently controlled microcontroller 103 accessible bits; SB_BUSY1 and SB_BUSY 2;

Writes to the Sound Blaster Command Register (SB_Base + C) immediately set the Command Busy bit (via SB_BUS Y 1 );

Microcontroller 103 reads and processes the command. Once the command is processed, a read of the Sound Blaster Data Register (External RAM address 0x01), by microcontroller 103, will clear this bit. This bit is set to a 1 on a reset (RESDRV); and Writes to the Sound Blaster Reset Register (SB_Base t- 6) with a DO value of one immediately sets the Command Busy bit (via SB_BUSY 2). Microcontroller 103 processes the reset command and clears the Command Busy bit by executing a write of microcontroller 103 address 0x8.

2. When microcontroller 103 writes data to the SB Data Register (microcontroller 103 External RAM address 0x02) the Data Available bit is set to a one. This bit is cleared once the Read Data Port (Sound Blaster base address + A) is read via the ISA bus. This bit defaults to 0 on reset.

Codec 100 supports Sound Blaster ADPCM 2:1, 3: 1, and 4:1 decompression. When a ADPCM byte is transferred to Codec 100 via DMA, an interrupt is generated to microcontroller 103 via input TRO, and the data are latched. Microcontroller 103 is then able to read the data from the latch by reading from memory location OxC.

The Sound Blaster RESET command is generated by writing a one to register index 6 and then writing index register 6 to a zero. In Codec 100 hardware detects the zero-one-zero transition and interrupts microcontroller 103 on the one-to-zero transition. The interrupt is acknowledged by microcontroller 103 reading the ISA Data Latch. In addition to the standard codec DMA request generation the Sound Blaster hardware has the capability of generating a DMA request via a number of commands. In Codec 100

57

SUBSTTTUTE SHEET (RULE 26) microcontroller 103 detects these commands and writes microcontroller 103 External RAM address OxE. The Sound Blaster hardware senses this write and generates a DMA Request on the ISA Bus. In addition microcontroller 103 may write a byte to the Sound Blaster Data Latch depending on which command is being responded to. The ISA Bus will in turn generate a DMA Acknowledge. If the DMA acknowledge is a read then the DMA request is cleared and the data that was written to the Sound Blaster Data Latch is put onto the ISA data bus. If the DMA acknowledge is a write then an interrupt is generated to microcontroller 103 microcontroller via INT1 and the data present on the ISA Data Bus is written into the Sound Blaster ADPCM Data Latch with the trailing edge of the IOW strobe. The leading edge of the IOW strobe clears the DMA Request. Microcontroller 103 responds to the interrupt by reading the Sound Blaster

ADPCM Data Latch (microcontroller 103 address OxOC).

In addition the Sound Blaster hardware may generate its own interrupt. This is accomplished by microcontroller 103 writing to External RAM address OxFH which will generate an interrupt on the ISA bus. The Sound Blaster interrupt is cleared when a read from Sound Blaster Data Available Register (index OxE). The MPU-401 has become the defacto standard for controlling MIDI devices via IBM-PC compatible personal computers.

A MPU401 logical device interface 104 occupies 2 I/O locations and utilizes 10-bit address decoding. The standard base address is 330h. This device also requires an interrupt, typically 9. Codec 100 implements the UART mode of the MPU-401 functionality. This mode is used to send and receive MIDI data to and from the host computer and a external MIDI device through interface 104. MPU-401 Interface 104 consists of two registers (Command/Status Register, Transmit/Receive Register) that are mapped into the host I/O space. MPU-401 interface 104 is idle until a Enter UART Mode command is written to the Command register. Once UART mode is entered, MIDI data are written to or read from the Transmit/Receive register a byte at a time. Microcontroller 103 stores the data in separate receive and transmit FIFO's. Each transfer of a byte into the receive FIFO should generate an interrupt to the host computer.

The Transmit (TXD) and Receive (RXD) pins of microcontroller 103 MPU401/UART port 104 connect to the MIDI OUT and MIDI IN pins respectively. After power-up reset, the interface is in "non-UART" mode. Non-UART mode operation is defined as follows: 1. All writes to the Transmit Port, MPUbase+0, are ignored;

58

SUBSTTTUTE SHEET (RULE 26) 2. All reads of the Receive Port, MPUbase+0. return the last received buffer data; and

3. All writes to the Command Port, MPUbase+1 , are monitored and acknowledged as follows: a. A write of 3 Fh sets the interface into UART operating mode. An acknowledge is generated by putting an FEh into the receive buffer FIFO which generates an interrupt; b. A write of A0-A7, ABh, ACh, ADh, AFh places an FEh into the receive buffer FIFO (which generates an interrupt) followed by a one byte write to the receive buffer FIFO of OOh for A0-A7, and ABh commands, 15h for ACh, Olh for ADh, and 64h for AFh commands; and c. All other writes to the Command Port are ignored and an acknowledge is generated by putting an FEh into the receive buffer FIFO which generates an interrupt.

UART mode operation is defined as follows: 1. All writes to the Transmit Port, MPUbase+0, are placed in the transmit buffer FIFO.

Whenever the transmit buffer FIFO is not empty, the next byte is read from the buffer and sent out the MIDOUT pin. The Status Register, MPUbase+1 , bit 6, TXS is updated to reflect the transmit buffer FIFO status;

2. All reads of the Receive Port, MPUbase+0, return the next byte in the receive buffer FIFO. When serial data are received from the MDIN pin. it is placed in the next receive buffer FIFO location. If the buffer is full, the last location is overwritten with the new data. The Status Register, MPUbase+1, bit7, RXS is updated to reflect the new receive buffer FIFO state;

3. A write to the Command Register, MPUbase+ 1, of FFh will return the interface to non-UART mode; and

4. All other writes to the Command Register. MPUbase+1, are ignored. MPU-401 interface 104 also uses a hardware handshake mechanism. The MPU-401 interface incorporates receive and transmit FIFO's implemented by microcontroller 103. External handshake bits indicate to the host the current FIFO status. The two handshake bits are as follows: Transmit FIFO Full Flag, and Receive Buffer Empty Flag. The status of both flags is output onto the ISA bus in response to a read of the MPU Commands/Status Register (MPU-401 base address + 1 ). The flags function as follows: 1. Transmit FIFO Full Flag is set when a ISA write cycle occurs to the MPU-401 Transmit/Receive Data Port or the Command/Status Register. This flag is reset when a microcontroller 103 read of the MPU Data Register (External RAM address = 0x02) occurs: and 2. Receive Buffer Empty Flag is set to one when an ISA read cycle occurs to the

Transmit Receive Data Port. This flag is reset to zero when microcontroller 103 performs a write to the MPU Data Register (External RAM address = 0x02). This write also generates an interrupt on ISA bus. When an ISA Bus read of the Transmit/Receive Register occurs the interrupt will be cleared. TABLES 47A-47E summarize the Sound Blaster/MPU 401 Hardware Interface

Definition and Protocol.

FIGURES 24A-24L are diagrams of the bitfields of the Sound Blaster/MPU-401 registers.

FIGURE 24A is a diagram of the ISA DATA READ/ MIXER LATCH register at microcontroller address 0x00. This microcontroller 103 address location is read by microcontroller 103 in response to a ISA bus write cycle to the Sound Blaster DSP Command

Register, Mixer Address Register, Mixer Data Register, or the MPU-401 Command Register.

When microcontroller 103 read strobe is low, ISA bus data is enabled onto microcontroller 103

XDB[7:0] bus (FIGURE 3). A write to this location occurs in response to read from the Mixer

Data Port. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch. The output from the latch is then enabled onto the ISA data bus where it is read.

FIGURE 24B is a diagram of the bitfields of the Sound Blaster Data Latch register at microcontroller address 0x01. This microcontroller 103 address location is written by microcontroller 103 in response to a ISA bus write to the Sound Blaster Command Register. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch. The output from the latch is then enabled onto the ISA data bus where it is read.

FIGURE 24C is a diagram of the bitfields of the MPU-401 Receive Data Latch at microcontroller address 0x02. This microcontroller 103 address location is written by microcontroller 103 in response to a ISA bus write to the MPU-401 Command Register or read by the ISA bus of the MPU-401 Transmit/Receive Register. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch. The output from the latch is then enabled onto the ISA data bus where it is read.

60

SUBSTTTUTE SHEET (RULE 26) FIGURE 24D is a diagram of the bitfields of the STATUS REGISTER at Address 0x03. This microcontroller address location when read by microcontroller 103 returns the current status of the Sound Blaster, MPU-401 ISA bus handshake bits, codec interrupt, and Sound Blaster ADPCM data ready: RXS-MPU-401 Receive Buffer Status 0=not empt, l=empty;

TXS-MPU-401 Transmit Buffer Status 0=not full, l=full;

SCB-Sound Blaster Command Busy 0=not busy, l=busy;

SDA-Sound Blaster Data Available 0=no data available, l=data available;

CINT-Codec Interrupt Status 0=no interrupt pending, 1 interrupt pending; and SBAD Sound Blaster ADPCM Status 0=old ADPCM data, l=new ADPCM data.

FIGURE 24E is a diagram of the Reserved Registers at microcontroller Addresses 0x04 through 0x07.

FIGURE 24F is a diagram of the bitfields of Reset Sound Blaster Busy 2 at microcontroller 103 Address 0x08. FIGURE 24G is a diagram of the bitfields of the Reset Sound Blaster Busy 2 register at microcontroller address 0x08. When this microcontroller 103 address is written, the Sound Blaster Command Busy 2 flag is forced to a zero.

FIGURE 241 is a diagram of the bitfields of the Sound Blaster ADPCM Data Latch at microcontroller 103 Address OxC. This address is read in response to a Sound Blaster ADPCM DMA write (ADPCM Status bit=l and TRO interrupt active). A microcontroller 103 read of this address resets the ADPCM Status bit to a zero.

FIGURE 24J is a diagram of the bitfields of Set Sound Blaster Busy 1 at microcontroller 103 Address MD. When this microcontroller 103 address is written the Sound Blaster Command Busy 1 flag is forced to a one. FIGURE 24K is a diagram of the bitfields of the

Sound Blaster DMA Request Register at microcontroller 103 Address ME which is in response to a write of a DMA command to the Sound Blaster Command Register. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch which also results in a DMA Request being generated on the ISA bus. When the ISA bus responds via a DMA acknowledge, the data that was written to this register is enabled onto the ISA bus where it is read. The DMA request may also be cleared by microcontroller 103 performing a read of this register.

61

SUBSTTTUTE SHEET (RULE 26) FIGURE 24L is a diagram of the bitfields of the Sound Blaster interrupt Request Register at microcontroller 103 Address OxOF. When this microcontroller 103 register is written an interrupt is generated on the ISA bus. The interrupt is cleared when the Sound Blaster DSP Data Port is read. Control Register Interface

In the Control. Logical Device space exits a set of registers for Codec 100 specific functions. These functions include EEPROM programming, power management modes, host interrupt generation. Sound Enhancement control, SP DIF control, and various other miscellaneous control bits. The control registers are summarized in TABLES 48 A and 48B. FIGURES 25A-25S and the accompanying text describe each of the Control Registers in detail.

FIGURE 25 A is a diagram of the Miscellaneous Control Register (at base +0, default = 0x00000000). Microcontroller 103 reads this register and controls the various functions accordingly. An ISA bus write of this register will also generate an interrupt to microcontroller 103 microcontroller via LNT1. The bitfields can be described as follows.

JS1, JS0 These bits select among four joystick operating speeds:

0 0 = slowest speed;

0 1 - medium slow speed;

1 0 - medium fast speed; 1 1 = fastest speed

The CONSW bit controls host interrupt generation when a context switch occurs. The interrupt will only be passed through to the ISA bus if an interrupt resource was specified for

Codec 100 logical device and the PnP configuration manager mapped the interrupt. Thus setting

CONSW to a one does not necessarily guarantee that an ISA bus interrupt will get generated on a context switch. The decoding is:

0 - no interrupt generated on context switch

1 - interrupt generated on context switch

The PM1, PM0 bits control the various power down modes of Codec 100: 0 0 = normal operation with bits PDC, PDP, PDM enabled; 0 1 = A/D and D/A of codec are powered down. Analog mixer is still active in this mode, but gain attenuation values are frozen. Bits PDC and PDM disabled; 1 0 = full Codec 100 power down. All Codec 100 functions are disabled except reads and writes to this register. This is a software version of the RESDRV pin. A reset will be generated (all clocks disabled), and held, to all Codec 100 internal logic including microcontroller 103 and all internal registers. The reset is released once these bits are written to 00 and the clocks are re-enabled; and

1 1 = In this mode the A/D and D/A of the Codec, microcontroller 103, and the codec mixer including VREF are all powered down. Microcontroller 103 is forced into idle mode. An interrupt to microcontroller 103 will cause microcontroller 103 to exit idle mode and resume normal operation, but the codec A/D, D/A, and mixer will remained powered down. The mixer register settings are reset to default settings in this mode.

When these bits are set to one all accesses to codec registers are disabled. When these bits are toggled from a 1 1 to a zero there will be a delay, caused by VREF capacitor charging, until the codec registers may be accessed reliably. The delay is determined by the capacitor value on the VREF pin and typically is on the order of 200ms.

The PDC bit (Power Down Codec) controls codec power down:

0 = Normal operation

1 = A/D and D/A functions of codec are powered down.; the codec interface remains active and registers, including mixer registers, may be read or written.

The PDP Power Down Processor bit: 0 = Normal operation

1 = microcontroller 103 is forced into idle mode. Any interrupts generated to microcontroller 103 (PnP, Sound Blaster, MPU-401, Context Switch) will cause microcontroller 103 to exit IDLE mode and resume normal operation. Microcontroller

103 will clear this bit when idle mode operation is exited. The PDM Power Down Mixer:

0 = Normal operation

1 = Mixer is powered down. While in this mode the codec interface is enabled and the codec registers are accessible.

RES - The RES bits are reserved bits that may be required for future changes or additions. These bits should have physical storage elements associated with them.

63 SUBSTTTUTE SHEET (RULE 26) FIGURE 25B is a diagram of the Hardware Control Register (at address base +1, default 0x10000000). This bitfield of this register can be described as follows:

The PCDLNT (Polarity CDROM Interrupt) bit specifies polarity of CDROM interrupt input:

0 = CDROM interrupt is active low; and

1 = CDROM interrupt is active high.

The PSINT (Polarity Synthesizer Interrupt) bit specifies polarity of synthesizer interrupt input:

0 = synthesizer interrupt is active low; and 1 = synthesizer interrupt is active high.

The PMINT (Polarity Modem Interrupt) bit specifies polarity of modem interrupt input:

0 - modem interrupt is active low; and

1 = modem interrupt is active high.

The ADC1, ADCO (A/D Control 1 ,0) bits are used to control an additional analog mix feedback path into the A/D converters:

00 = normal operation. A/D input from input mux/gain, stage. No mix of Input MLJX to output;

01 = output from Input Mux is mixed into line outputs. A/Dinput is from Input Mux;

10 = output from Input Mux is mixed into line outputs. A/D input is from line outputs; and

1 1 - reserved.

FIGURE 25C is a diagram of the Power Down Control Register (at address control base +2, default = 00000000). Microcontroller 103 reads this register and controls the various functions accordingly. An ISA bus write of this register will also generate an interrupt to microcontroller 103 via INT1. This register is decoded:

Full Power Down

Power down. When this bit is set to 1 Codec 100 is put into a full power down mode. All functions are disabled except reads and writes to this register. Microcontroller 103 is held reset and all clocks are disabled. When this bit is set to zero Codec 100 will resume normal operation after valid clocks are detected, VREF has reached the operating level, and a calibration cycle has been completed. Only the codec analog mixer

64

SUBSTTTUTE SHEET (RULE 26) registers are reset when this bit is set to a one. Due to the fact that microcontroller 103 is reset by this bit. internal registers may be changed as defined by microcontroller 103 start-up initialization sequence.

SRC Power down of the Sample Rate Converter when set = 1. If the input sampling rate is at 44100Hz. the data will feed through unaffected.

REF Power down of the reference voltage source when set = 1. The complete analog section of the device powers down. When VREF is powered up and the Mixer is powered down, Mono Bypass Mode is functional. A pop on the line outputs will always occur if this bit is set even if the master volume is muted. When this bit is set to one all accesses to codec registers are disabled and when toggled from a one to a zero there will be a delay, caused by VREF capacitor charging, until the codec registers may be accessed reliably. This delay is determined by the capacitor value on the VREF pin and typically is on the order of 200ms. MIXER Power down of the mixer analog section when set = 1. All op amps except for the MONO in and MONO out op amps are powered down, all analog inputs and outputs are centered around VREF, if VREF is enabled and not powered down. A reset is not required to maintain the calibrated state if the mixer is powered down and VREF is powered up. ADC Power down of the A/D converter, decimator, A/D SRC, and A/D compression circuitry. Capture timing is disabled.

DAC Power down of the DAC, switch cap filter, interpolator, SRC, decompressor circuitry, FM engine, serial port circuitry. Playback timing is disabled.

MC Microcontroller 103 is put into IDLE mode Any interrupts generated to microcontroller 103 (PnP, Sound Blaster, MPU-401, Context Switch) will cause microcontroller 103 to exit IDLE mode and resume normal operation.

FM Power down of the FM synthesis engine. NOTE: Software should mute the ADC, DAC, FM and Mixer outputs when asserting erting any power down modes to prevent clicks and pops.

65

SUBSTTTUTE SHEET (RULE 26) FIGURE 25D is a diagram of the bitfields of the Control Address/Index Register (at address, base +3, default = 00000000). The Control Address/Index Register is used to specify an index into a set of extended control registers, discussed further below. Once a particular register index has been specified the register may be accessed by reading or writing the Control Data Register. Bits D7..D4 are decoded and must be zero's to access the extended control registers.

FIGURE 25E is a diagram of the bitfields of Control Data Register (at address base +4, default = 00000000). The Control Data Register is used to access data from an extended control register that is specified in the Control Address/Data Register. FIGURE 25F is a diagram of the bitfields of the Command Register (at address base +5, default = 00000000). This register is used to control various functions of Codec 100. A Command is executed after the appropriate Command identifier is written to this register. When this register is either read or written via the ISA bus an interrupt will occur to microcontroller 103 via LNT1. The support commands are listed below: DISABLE_PNP (0x55) This command is used to disable Codec 100 Plug & Play function so that Codec 100 may operate in non-PnP environments. DISABLE_CSC (0x56) This command is used to disable Codec 100 "Crystal Key" back door mechanism so that Codec 100 may operate in multiple Codec 100 environments in which the "Crystal

Key" is used to configure a Codec 100. UPDATE PNP (0x5 A) This command is used to force an update of the current values that specify the settings for mapping inputs to

Codec 100 mixer as well as the settings for ISA Bus interrupt and DMA mapping and configuration data for all

Codec 100 logical devices. If the current settings were changed due to a Program RAM load then this command will force the new settings to be transferred to the hardware. This command will also disable any logical devices, including the Control Port, that are active at the time this command is sent.

66

SUBSTTTUTE SHEET (RULE 26) RAM_LOAD (OxAA) This command is used to read/write the Program Ram. Once the OxAA command is received Codec 100 expects the following two bytes to specify a starting address location. This starting address location specifies where data are to be written into or read from the Program RAM. The first byte following the command byte specifies the low byte of a 16-bit RAM load start address and the second byte specifies the high byte. Subsequent bytes are then written to RAM ( Write Cycle to the Program RAM Access Register) or read from the RAM (Read Cycle to the Program RAM Access Register). After each byte is transferred, the RAM address pointer is automatically incremented to point to the next location. Data will continue to be written to or read from the RAM until the Program RAM Access End Register is written. The data written to the Program RAM Access End Register is a don't care.

SOFTWARE RESET (0x59) When this value is written to Codec 100 Control Port microcontroller 103 will be forced to jump to ROM location 0x0000. This will cause all the hardware configuration registers to be reset back to an off state. The function of any multi-function pins will be unchanged by this command. If a Legacy Mode EEPROM is present, then the hardware configuration registers are re-programmed according to the data contained in the EEPROM. If a Legacy Mode EEPROM is not present then the configuration registers must be setup by a host load or PnP configuration sequence.

SUSPEND REQUEST (0x33) When this value is written to Codec 100 Control Port microcontroller 103 will copy the current microcontroller 103 state into the area of RAM that is used to store the Plug-n-Play

67

SUBSTTTUTE SHEET (RULE 26) resource data. This command will cause Codec 100 to hold IOCHRDY low until microcontroller 103 has been copied to RAM. SUSPEND (0x3 C) When this value is written to Codec 100 Control Port microcontroller 103 will enter IDLE mode.

RESUME (OxCC) When this value is written to Codec 100 Control Port microcontroller 103 will exit from IDLE mode and restore the state of microcontroller 103 from RAM.

FIGURE 25G is a diagram of the bitfields of the Program RAM Access End Register (at address base +6, default = 00000000). This register is used to end access to the Program RAM memory of Codec 100. When this register is written via the ISA bus, an interrupt will occur to microcontroller 103 via INT1.

FIGURE 25H is a diagram of the bitfields of the Status Register (at address base +7, default = 00000000). The bitfields decoding is as follows: CSS ( Context Switch Status) bit indicates current operating mode of Codec 100:

0 = Sound Blaster; and

1 = Sound System.

The CSI (Context Switch Interrupt Status) bit indicates current status of Context Switch Interrupt: 0 = no interrupt pending; and

1 = interrupt pending. The SBI (Sound Blaster Interrupt Status) bit indicates current status of Sound Blaster Interrupt:

0 = no interrupt pending; and 1 = interrupt pending.

The CDECI (Codec Interrupt Status) bit indicates current status of Codec Interrupt:

0 = no interrupt pending; and

1 = interrupt pending.

The MPUI (MPU401 Interrupt Status) bit indicates current status of MPU-401 Interrupt: 0 = no interrupt pending; and

1 = interrupt pending.

68

SUBSTTTUTE SHEET (RULE 25) The Control Indirect Registers (C10-C131) are summarized in TABLE 48B above. The individual registers can now be described in further detail

FIGURE 251 is a diagram of the bitfields of the Miscellaneous Control at Control Index register (CO, default = 00000000). The bitfields decoding is as follows: RWSS Reset code registers. Resets all codec registers to zero while this bit is set to a one. When this bit is set back to zero then all codec registers are reset to default values, res Reserved.

FIGURE 25 J is a diagram of the bitfields of the Version ID at Control Index register (Cl, default = 10000100). This read only register shadows the current contents of codec indirect register 125. This register holds the current chip identifier and version number where: V2-V0 Version number. See above for a description of these bits, res Reserved

CID2-CID0 Chip Identification. FIGURE 25K is a diagram of the bitfields of SRS Control Register at Control Index (C2, default = 00000010). The bitfield decodings are:

SPC (Space) 3-0, SRS processed signal gain termed "SPACE". The least significant bit represents -1.5dB, the attenuation range is from 0 dB to - 22.5 dB, with 0000 = (0 dB or min attenuation). TABLE 49 A associates the SPC register values with the resulting attenuation. CNT (Center) 3-0, SRS processed signal gain termed "CENTER". The least significant bit represents -1.5 dB, the attenuation range is from 0 dB to - 22.5 dB, with 0000 = (0 dB or min attenuation). TABLE 49B associates the CNT register values with the resulting attenuation.

FIGURE 25L is a diagram of the bitfields of 3D Sound Control Register at Control Index (C3, default = 00000000). The field decodings are as follows: 3DEN When this bit is set to 1 , the 3D Audio DSP is enabled and will process any stereo signal from the Digital Mixer. The processed signal is converted by the DAC to "3D" stereo analog 2 channel audio data. The 3D Audio DSP will process either SRS or QSound based on which ROM code is selected. 3DMON When this bit is set to 1 , the SRS Mono to Stereo DSP is enabled instead of the SRS Stereo DSP, and will process any mono or stereo signal from the Digital Mixer. The processed signal is converted by the DAC to

69 SUBSTTTUTE SHEET (RULE 26) "pseudo" stereo analog 2 channel audio data. The 3DEN bit must be set to 1, on Codec 100. 3 DSP When this bit is set to 1 , the digital data to the Serial Port is from the 3D

Audio DSP. When this bit is set to 0, the digital data to the Serial Port is from the A/D converter.

QSEN This bit when set to a one will enable the QSound circuitry.

Res Reserved for future use.

Note: SRS MONO - When the Mono to Stereo function is selected, the "Space" and "Center" bits in register C2 are blocked from writing to, and the registers are set to the default values - "Space" -3 dB or 0010 and "Center" 0 dB or 0000.

FIGURE 25M is a diagram of the bitfields of the S PDIF Control Register at Control Index (C4, default = 00000000). The decodings are as follows:

SPDIF When this bit is set to 1 and the indirect register 16 is set to 1 (Serial Port enable), the digital data to the Serial Port is formatted to the S/PDIF protocol. When this bit is set to 0 and the indirect register 116 SPEN bit is set to a 1 (Serial Port enable), the Serial Port transmits the standard format digital data from the A D or 3D data as selected by the 3DSP bit in register C3. BLKST A low to high transition specifies a new channel status block boundary.

(Block Start) U U Bit is a user defined bit.

V Validity Bit. Indicates whether the audio sample is suitable for conversion to an analog signal, res Reserved for future use

FIGURE 25N is a diagram of the bitfields of S/PDIF Channel Status Data - 0 at Control Index (C5, Default = 00000000). The bitfields are decoded as follows:

CS0 0 = Consumer;

CSI Audio:

0 = Digital Audio; and

1 = Non - Audio Data; CS2 Copy/Copyright:

0 = copy inhibited/copyright asserted; and

1 = copy permitted/copyright not asserted; CS3-CS4 Pre-emphasis:

00 - defines no pre-emphasis - if CSO = 0 (digital audio); and

1 = 50/15us pre-emphasis;

CS5 Lock: Source Sample frequency: 0 = locked; and

I = unlocked; CS24 Fs: Sample frequency 0 = 44.1 kHz; and

CS25 Fs: Sample frequency 0 - 44.1 kHz.

FIGURE 250 is a diagram of the bitfields of S/PDIF Channel Status Data - 1 at Control Index (C6) (Default = 00000000). The bitfields are decoded as follows:

CS 15 L Bit Generation Status:

0 = Original; and

1 = 1st Generation or higher; and CS8-CS 14 Category Code: 0000000 General;

0000001 Experimental; 0001 xxx Solid State Memory; OOlxxxx Broadcast Reception; OlOxxxx Digital/Digital converters; 01 lOOxx A D converters w/o copy info:

01 lOlxx A/D converters w/ copy info -(using Copy and L bits); 01 1 lxxx Broadcast reception; lOOxxx Laser-Optical; lOl xxx Musical Instruments; 1 1 Oxxxx Magnetic tape or disk; and

1 1 lxxxx Reserved. FIGURE 25P is a diagram of the bitfields of FAB Port ID at Control Index (C7, Default = 00000000). In order to track the various FAB ports of Codec 100 this register is updated each time any changes are done to the current revision in order to accommodate FAB specific requirements.

FB7-FBO = 0x00 FAB 1; 0x01 FAB 2;

71

SUBSTTTUTE SHEET (RULE 26) 0x02 FAB 3; and 0x03 FAB 4. FIGURE 25Q is a diagram of the bitfields of Wavetable and Serial Port at Control Index (C8, Default = 00000000). The bitfield encodings are as follows: SBSP Sound Blaster Swap Playback - when this bit is set to a zero the current ordering of samples for DMA playback are swapped relative to the current defined format; SBSC Sound Blaster Swap Capture - when this bit is set to a one the current ordering of samples for DMA capture are swapped relative to the current defined format; res Reserved;

WTEN Wavetable Enable - When this bit is set to a one the XD7:XD5 pins are switched to support a wavetable interface as shown in TABLE 50. SPS Serial Port Switch - When this bit is set to a one and the SPE bit in register 116 is set to a one the DSP serial port pins are switched from the second joystick pins to the XD pins as shown in TABLE 51. If SPS is a zero and the SPE bit in register 116 is set to a one the DSP serial port pins are routed to the second joystick pins. If the SPE bit in register 116 is a zero then the serial port pins do not appear anywhere. If either WTEN or SPS are set to a one then the XBUF bit in CDROM Interface Control

Register at microcontroller 103 address 0x34 is forced to a one.

MCLKDIS When this bit is set to a one, and the wavetable serial interface is enabled by WTEN = 1 , the MCLK pin to the wavetable device is synchronously forced to zero. MCLK will remain a zero until MCLKDIS is set to zero. At this time MCLK will synchronously be enabled: and

BRESET When this bit is set to a one the BRESET pin is forced to zero. This is to allow microcontroller 103 and host control of external devices connected to the BRESET pin; FIGURE 25R is a diagram of the bitfields of Left Output Master Volume at Control Index (C27, default = 001x0000) where:

LOA3-LOA0 are the Left Output Master Volume bit LOAO is the least significant bit and represents 2dB steps. The range is +12db to -18db; and

72

SUBSTTTUTE SHEET (RULE 26) LMSLLMSO are the Left Output Mixer Summer Attenuation bits and: 0 0 -12dB;

0 1 OdB;

1 0 -6dB; and 1 1 -18dB.

FIGURE 25 S is a diagram of the bitfields of Right Output Master Volume at Control Index (c29, default = 001x000) where:

ROA3-ROA0 are the Right Output Master Volume bits. ROA0 is the least significant bit and represents 2dB steps. The range is +12dB to -18dB; and RMSLRMSO Right Output Mixer Summer Attenuation where:

0 0 -12dB 0 1 OdB 1 0 -6dB 1 1 -18dB Codec Interface

Codec Interface 107 includes logic that enables access to the registers located in the core from either the ISA bus (through Plug-n-Play configuration registers) or microcontroller 103. FIGURE 26 is a diagram emphasizing Codec Interface 100.

The Sound System Codec software interface consists of 4 I/O locations starting at the Plug and Play address values 'WSSbase' shown in TABLE 52A, and supports 12-bit address decoding. If the upper address bits, SA12-SA15 are used, they must be a 0 to decode a valid address. The SS Codec also requires one interrupt and one or preferably two DMA channels, one for playback and one for capture. Since the SS Codec and Sound Blaster device are mutually exclusive, the two devices share the same interrupt and DMA playback channel. The WSS Codec functions 204 include FIFOs 121 and 122 (FIGURE 1) 16-sample FIFOs in both the playback and capture digital audio data paths. The FIFOs are transparent and have no programming associated with them. When playback is enabled, playback FIFO 121 continually requests data until the FIFO is full, and then makes requests as positions inside the

FIFO are emptied, thereby keeping as full as possible. Thus, when Codec 100 cannot respond within a sample period, the FIFO starts to empty, avoiding a momentary loss of audio data output to the ISA bus. If the FIFO runs out of data, the last valid sample can be continuously output to the DACs (if DACZ in register 116 is set) which will eliminate pops from occurring. When capture is enabled, capture FIFO 121 continually makes requests to the ISA bus every sample period thereby attempting to remain empty. Thus, when codec 100 cannot respond within a sample period, capture FIFO 121 starts filling, thereby avoiding a loss of data in the audio data stream. Four I/O mapped locations (block 107, FIGURE 1) are available for accessing the Codec functions and mixer. The control registers allow access to status, audio data, and all indirect registers via the index registers. The IOR and IOW signals are used to define the read and write cycles respectively. A PIO access to the Codec begins when the host puts an address on the ISA bus which matches WSSbase and drives AEN low. The WSSbase register is programmed during a Plug and Play configuration sequence. Once a valid base address has been decoded then the assertion of IOR will cause the WSS Codec to drive data on the ISA data bus lines. Write cycles require the host to assert data on the ISA data bus lines and strobe the IOW signal. The WSS Codec will latch data into the PIO register on the rising edge of the IOW strobe.

The audio data interface typically uses DMA request/grant pins to transfer the digital audio data between WSS Codec 204 functions and the bus. WSS Codec 204 is responsible for asserting a request signal whenever the Codec's internal buffers need updating. The bus responds with an acknowledge signal and strobes data to and from the Codec, 8 bits at a time. The WSS Codec functions keep the request pin active until the appropriate number of 8-bit cycles have occurred to transfer one audio sample. Note that different audio data types require a different number of 8-bit transfers.

The second type of parallel bus cycle from WSS Codec 204 is a DMA transfer. DMA cycles are distinguished from PIO register cycles by the assertion of a DRQ, while AEN is inactive, followed by an acknowledgment by the host by the assertion of DACK. While the acknowledgment is received from the host, WSS Codec 204 assumes that any cycles occurring are DMA cycles and ignores the addresses on the address lines.

WSS Codec 204 may assert the DMA request signal at any time. Once asserted, the DMA request will remain asserted until a complete DMA cycle occurs. DMA transfers may be terminated by resetting the PEN and/or CEN bits in the Interface Configuration register (19), depending on the DMA that is in progress (playback, capture, or both). Termination of DMA transfers may only happen between sample transfers on the bus. If DRQ goes active while resetting PEN and or CEN, the request must be acknowledged with DACK and a final sample transfer completed.

74

SUBSTTTUTE SHEET (RULE 26) Mapping of the WSS Codec DRQ and DACK onto the ISA bus is accomplished by the Plug and Play configuration registers. If the Plug and Play resource data specifies only one DMA channel for the Codec (or the codec is placed in SDC mode discussed below) then both the playback and capture DMA requests should be routed to the same DRQ/DACK pair (DMA Channel Select 0). If the Plug and Play resource data specifies two DMA channels for the Codec, then the playback DMA request will be routed to the DMA pair specified by the DMA Channel Select 0 resource data, and the capture DMA requests will be routed to the DMA pair specified by the DMA Channel Select 1 resource data.

WSS Codec 204 supports a single and a dual DMA channel mode. In dual DMA channel mode, playback and capture DMA requests and acknowledges occur on independent DMA channels. In dual DMA mode, SDC should be set to 0. The Playback- and Capture-Enables

(PEN, CEN, 19) can be changed without a Mode Change Enable (MCE, R0). This allows for proper full duplex control where applications are independently using playback and capture.

When two DMA channels are not available, the SDC mode forces all DMA transfers (capture or playback) to occur on a single DMA channel (playback channel). The trade-off is that the WSS Codec will no longer be able to perform simultaneous DMA capture and playback.

To enable the SDC mode, set the SDC bit in the Interface Configuration register (19). With the SDC bit asserted, the internal workings of the WSS Codec remain exactly the same as dual mode, except for the manner in which DMA request and acknowledges are handled. The playback of audio data will occur on the playback channel exactly as dual channel operation; however, the capture audio channel is now diverted to the playback channel. Alternatively stated, the capture DMA request occurs on DMA channel select 0 for WSS Codec 204. (In MODE 2, the capture data format is always set in register 128.) If both the both playback and capture are enabled, the default will be playback. SDC does not have any affect when using PIO accesses.

As discussed briefly above, Windows Sound System codec 204 is mapped via four locations. The I/O base address, WSSbase, is determined by the Plug and Play configuration. The WSSbase supports four direct registers, shown in TABLE 52A. The first two direct registers are used to access 32 indirect registers shown in TABLE 52B. The Index Address register (WSSbase+0) points to the indirect register that is accessed through the Indexed Data register

(WSSbase+1). The Master Volume Control uses a 26-step linear mapping of 2dB per step. The Sound Blaster Mixer Master Fader Control uses the non-linear Sound Blaster mapping with a range of OdB to -28dB in eight steps.

The ISA bus writes to the Sound Blaster Mixer Master address and Volume change button pushes are mapped to the CODEC_MASTER_OUT registers, I27A and I29A. The Sound

Blaster mixer range is implemented as a gain reduction to the current CODEC Master Volume setting. Thus, the Master Volume setting of +2dB will allow a 2dB to -26dB Sound Blaster Master Out control gain range. A Master Volume setting of -30dB will allow a -30db to -36dB range for the Sound Blaster Master Out control. In all cases, moving the Sound Blaster Master Out Control to the bottom of its range (zero or one) will cause a CODEC mute. Also the lowest

CODEC Master Volume step (twenty six) will cause a CODEC mute.

The default for the Master Volume control is OdB. The default for the Sound Blaster Master Out Control is -1 ldB.

The UP/DOWN/MUTE pins are accessible by microcontroller 103 at Port 3 when the VCEN bit has been set to a one at microcontroller 103 address 0x34. FIGURE 8, discussed briefly above, generally describes the bit fields of Port 3. Once VCEN =1, microcontroller 103 access to Port 3 will return the current data present on the UP/DOWN/MUTE pins (TTL levels).

The 26-step volume control is implemented using a 26 byte table which maps the numbers 0-25 with the Summer and Gain settings. The user changes the Sound Blaster Master Volume by using ISA bus writes to the Sound

Blaster mixer (external) mapped at I/O addresses 0x224 and 0x225.

The embedded code uses a combination of 2 groups of internal RAM variables and the I27A/I29A codec registers to accomplish Master volume control. The user hits buttons and the embedded code increments or decrements a count to keep track of the Master volume. This value is then combined with the appropriate mode fader (SB Master volume for Sound Blaster mode or WSS Master volume for Windows Sound System mode) to arrive at the final register value which will be written to the Codec registers I27A and I29A 205. TABLE 53 defines the Codec Master Map which correlates index values, register values and dB settings. Master Volume Algorithm: dCodecMasterVoiL/R + dWSSMasterVoil/*R = "index into

CODEC_MASTER_MAP_TABLE"

"CODEC_MASTER_MAP_TABLE Register Value" = I27A/I29A value.

*It is assumed that because the driver will vary the Codec Master Volume that the

WSS Master Volume will not be used and therefore will always remain at its default value of 0 (db). Because of this the dWSSMasterVoiL and dWSSMasterVolR values can be ignored when handling the Master Volume Control. o read the Codec Master volume:

1. Read dCodecMasterVolL/dCodecMasterVolR (using a RAM Internal Access command)to obtain Index Value.

2. Convert Index Value to dB setting using the CODEC_MASTER_MAP_TABLE. o write the Codec Master volume: 1. Receive user dB setting;

2. Convert dB setting to Index Value based on CODEC_MASTER_MAP_TABLE;

3. Convert dB setting to Register Value based on CODEC_MASTER_MAP_TABLE;

4. Write dCodecMasterVolL/dCodecMasterVolR registers with Index Value (using new RAM Internal Access command);

5. Write dLMasterHold/dRMasterHold registers with the Register Value (using new RAM Internal Access command); and

6. Perform Hold/Go OR Write 127 129 via the Hold/Go mechanism using the Register Value. (Any Hold/Go sequence will cause 127/129 registers to be updated with the register values in dLMasterHold/dRMasterHold).

Example: The Codec Master Volume Buttons are set at Max (+ 12 dB) volume. If a 0x16 is written to dWSSMasterVoiL and dWSSMasterVolR via the control port commands, then the Master output level will be -32 dB. In both Sound Blaster mode and WSS mode, the user may change the CODEC Master Volume via pins connected to physical switches or buttons. There are four different "button schemes" supported by the Codec 100.

The user selects one of these four schemes by setting the VCFl and VCFO bits in the Hardware Configuration Data, Global Configuration Byte, contained in external EEPROM.

In the first scheme, the Up and Down pins are connected to momentary SPST switches and the Mute pin connected to a Push on/push off SPST switch. This scheme is selected by setting VCFl and VCFO to 00. The first scheme provides the functionality described in TABLE 54. In the second scheme, the Up, Down and Mute pins are connected to momentary SPST switches and is selected by setting VCFl and VCFO to 01. TABLE 55 describes button operations in this scheme.

In the third scheme, the Up and Down pins are connected to momentary SPST switches and the Mute pin is NOT connected. This scheme is selected by setting VCFl and VCFO to 10. TABLE 56 describes the button operations in this scheme.

In the fourth scheme, the Mute and Down pins are connected to momentary SPST switches. The Mute pin is connect to the Up button momentary SPST switch. The Up pin is NOT connected. This scheme is selected by setting VCFl and VCFO to 1 1. Button functionality for the fourth scheme is described in TABLE 57. FIGURE 27A-27BB and the accompanying text describe Codec Register 107 in further detail.

FIGURE 27A is a diagram of the bitfield Index Address Register at address (WSSbase + 0, R0). The bitfields are described below:

IA4-IA0 Index Address: These bits define the address of the indirect register accessed by the Indexed Data register (RI). These bits are read/write;

IA4 Allows access to indirect registers 16-31. Only available MODE 2. In MODE 1 , this bit is reserved; TRD Transfer Request Disable: This bit, when set, causes DMA transfers to cease when the INT bit of the Status Register (R2) is set. Independent for playback and capture interrupts:

0 - Transfers Enabled (playback and capture DRQs occur uninhibited); and

1 - Transfers Disabled (playback and capture DRQ only occur if INT bit is 0);

78 SUBSTTTUTE SHEET (RULE 26) MCE Mode Change Enable: This bit must be set whenever the current mode of WSS

Codec 204 is changed. The Data Format (18, 128) and Interface Configuration (19) registers cannot be changed unless this bit is set. The exceptions are CEN and

PEN which can be changed "on-the-fly". The DAC output is muted when MCE is set; and

INIT WSS Codec Initialization: This bit is read as 1 when Codec 204 is in a state in which it cannot respond to parallel interface cycles. This bit is read-only. Immediately after RESET (and once WSS Codec 204 has left the INIT state), the state of this register is: 010x0000 (binary - where 'x' indicates unknown). During initialization and software power down (PM1,0 = 01), this register cannot be written and always reads 10000000

(80h).

FIGURE 27B is a diagram of the bitfield of Indexed Data Register (at address WSSbase+1, RI). The bitfield decoding is as follows:

ID7-ID0 Indexed Data register: These bits are the indirect register referenced by the Indexed Address register (R0).

During initialization and software power down of WSS Codec 204 . this register cannot be written and is always read 10000000 (80h).

FIGURE 27C is a diagram of the bitfield Status Register (at address WSSbase+2, R2, Read Only). The bitfield decodings are: INT Interrupt Status: This indicates the status of the internal interrupt logic of WSS

Codec 204. This bit is cleared by any write of any value to this register. The IEN bit of the Pin Control register (110) determines whether the state of this bit is reflected on the IRQ pin assigned to the WSS Codec: Read States: 0 - Interrupt inactive; and

1 - Interrupt active; PRDY Playback Data Ready. The Playback Data register (R3) is ready for more data. This bit would be used when direct programmed I/O data transfers are desired: 0 - Data still valid. Do not overwrite; and 1 - Data stale. Ready for next host data write value;

PL/R Playback Left/Right Sample: This bit indicates whether data needed is for the Left channel or Right channel in all data formats except ADPCM. In ADPCM it

79

SUBSTTTUTE SHEET (RULE 26) indicates whether the first two or last two bytes of a 4-byte set (8 ADPCM samples) are needed: I

0 - Right or 3/4 ADPCM byte needed; and

1 - Left, Mono, or 1/2 ADPCM byte needed; PU/L Playback Upper/Lower Byte: This bit indicates whether the playback data needed is for the upper or lower byte of the channel. In ADPCM it indicates, along with PL R, which one of the four ADPCM bytes is needed:

0 - Lower or 1/3 ADPCM byte needed; and

1 - Upper, any 8-bit format, or 2/4 ADPCM byte needed; SER Sample Error: This bit indicates that a sample was not serviced in time and an error has occurred. The bit indicates an overrun for capture and underrun for playback. If both the capture and playback are enabled, the source which set this bit cannot be determined. However, the Alternate Feature Status register (124) can indicate the exact source of the error; CRDY Capture Data Ready. The Capture Data register (R3) contains data ready for reading by the host. This bit would be used for direct programmed I/O data transfers:

0 - Data are stale. Do not reread the information; and

1 - Data are fresh. Ready for next host data read;

CL/R Capture Left/Right Sample: This bit indicates whether the capture data waiting is for the Left channel or Right channel in all audio data formats except ADPCM.

In ADPCM it indicates whether the first two or last two bytes of a 4-byte set (8 ADPCM samples) are waiting:

0 - Right or 3/4 ADPCM byte available; and

1 - Left, Mono, or 1/2 ADPCM byte available CU/L; and CU/L Capture Upper/Lower Byte: This bit indicates whether the capture data ready is for the upper or lower byte of the channel. In ADPCM it indicates, along with CL/R, which one of four ADPCM bytes is available:

0 - Lower or 1/3 ADPCM byte available; and

1 - Upper, any 8-bit format, or 2/4 ADPCM byte available. Note on PRDY/CRDY: These two bits are designed to be read as one when action is required by the host. For example, when PRDY is set to one, the device is ready for more data;

80 SUBSTTTUTE SHEET (RULE 26) or when the CRDY is set to one. data are available to the host. The definition of the CRDY and PRDY bits are therefore consistent in this regard.

The PIO Data register is two registers mapped to the same address. Writes to this register sends data to the Playback Data register. Reads from this register will receive data from the Capture Data register.

During initialization and software power down of WSS Codec 204, this register cannot be written and is always read 10000000 (80h).

FIGURE 27D is a diagram of the bitfield Capture I/O Data Register (at address WSSbase + 3, R3, Read Only). The bitfield encodings are as follows: CD7-CD0 Capture Data Port. This is the control register where capture data are read during programmed I/O data transfers. The reading of this register will increment a state machine so that the following read will be from the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the Status register (R2). Once all relevant bytes have been read, the state machine will point to the last byte of the sample until a new sample is received from ADCs 11 1.

Once the Status register (R2) is read and a new sample is received from the FIFO, the state machine and Status register (R2) will point to the first byte of the new sample.

During initialization and software power down of WSS Codec 204, this register cannot be written and is always read 10000000 (80h). FIGURE 27E is a diagram of the bitfield of Playback I/O Data Register (at address

WSSbase+3. R3, Write Only).

PD7-PD0 Playback Data Port. This is the control register where playback data are written during programmed IO data transfers.

Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset after the

Status register (R2) is read, and the current sample is sent to the DACs 1 10 via the FIFOs 122.

The indirect registers are accessed by placing the appropriate index in the Index Address register (R0) and then accessing the Indexed Data register (RI) discussed above. A detailed description of each indirect register is given below. All reserved bits should be written zero and may be 0 or 1 when read. Note that indirect registers 16-31 are only available when the MODE

2 bit in MODE and ID register (112) is set. FIGURE 27F is a diagram of the bitfield of Left ADC Input Control (10, default = 000x0000). The field decodings for this register are: LAG3-

LAG0 Left ADC Gain. The least significant bit represents +1.5dB, with 0000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ;

LMGE Left Mic Gain Enable: This bit enables the 20dB gain stage of the left mic input signal, LMIC.LWSSl-LWSSO; LWSS1-

LWSS0 Left ADC Input Source Select. These bits select the input source for the left ADC channel:

0 - Left Line: LLLNE;

1 - Left Auxiliary 1 : LAUX12;

2 - Left Microphone: LMIC3; and

3 - Left Line Output Loopback. FIGURE 27G is a diagram of the bitfield of Right ADC Input Control (II, default =

000x0000). The bitfield decodings are:

RAG3-RAG0 Right ADC Gain. The least significant bit represents +1.5dB, with 0000

= 0dB; res Reserved. Must write 0, could read as 0 or 1 ; RMGE Right Mic Gain Enable: This bit enables the 20dB gain stage of the right mic input signal. RMIC; and RWSS1-

RWSS0 Right ADC Input Select. These bits select the input source for the right

ADC channel: 0 - Right Line: RLINE;

1 - Right Auxiliary 1 : RAUX1 ;

2 - Right Microphone: RMIC; and

3 - Right Line Out Loopback.

FIGURE 27H is a diagram of the bitfield of Left Auxiliary #1 Input Control (12, default = lxxOlOOO). The bitfield decoding for this register is:

82

SUBSTTTUTE SHEET (RULE 26) LX1G4-

LX1G0 Left Auxiliary # 1 , L AUX 1 , Mix Gain. The least significant bit represents

1.5dB, with 01000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and LX1M Left Auxiliary #1 Mute. When set to 1, the left Auxiliary #1 input,

LAUX1, to the mixer, is muted. FIGURE 271 is a diagram of the bitfield of Right Auxiliary #1 Input Control (13, default = lxxO 1000). The bitfields are: RX1G4- RX1G0 Right Auxiliary #1, RAUX1, Mix Gain. The least significant bit represents 1.5dB, with 01000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and

RXIM Right Auxiliary #1 Mute. When set to 1, the right Auxiliary #1 input, RAUX1, to the mixer, is muted. FIGURE 27J is a diagram of the bitfield of Left Auxiliary #2 Input Control (14, default

= lxxOlOOO). The bitfield decodings are:

Left Auxiliary #2, LAUX2, Mix Gain. The least significant bit represents 1.5dB, with

01000= OdB; res Reserved. Must write 0; and LX2M Left Auxiliary #2 Mute. When set to 1. the left Auxiliary #2 input. LAUX2. to the mixer, is muted. FIGURE 27K is a diagram of the bitfields of Right Auxiliary #2 Input Control (15, default = lxxOlOOO). The bitfields decodings are: RX2G4- RX2G0 Right Auxiliary #2, RAUX2, Mix Gain. The least significant bit represents 1.5dB, with 01000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and

RX2M Right Auxiliary #2 Mute. When set to 1. the right Auxiliary #2 input, RAUX2, to the mixer, is muted. FIGURE 27L is a diagram of the bitfield of Left DAC Output Control (16, default =

1x000000).

83 SUBSTTTUTE SHEET (RULE 25) LDA5-

LDAO Left DAC Attenuator. The least significant bit represents -1.5dB, with

000000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and LDM Left DAC Mute. When set to 1 , the left DAC output to the mixer will be muted. FIGURE 27M is a diagram of the bitfield of Right DAC Output Control (17, default = 1x000000). The bitfields are decoded as:

RDA5-RDA0 Right DAC Attenuator. The least significant bit represents -1.5 dB, with 000000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and

RDM Right DAC Mute. When set to 1 , the right DAC output to the mixer will be muted. FIGURE 27N is a diagram of the bitfield of Fs and Playback Data Format (18, default = 00000000). The bitfield decoding is as follows:

C2SL Clock 2 Source Select: This bit selects the clock source used for the audio sample rates for both capture and playback. Note that this bit can be disabled by setting SRE in 122. C2SL can only be changed while MCE (R0) is set: 0 - XTAL 1 Typically 24.576MHz; and 1 - XTAL2 Typically 16.9344MHz;

CFS2-

CFS0 Clock Frequency Divide Select: These bits select the audio sample frequency for both capture and playback. The actual audio sample frequency depends on which clock source (C2SL) is selected and its frequency. Frequencies listed as N/A are not available because their sample frequency violates the maximum specifications; however, the decodes are available and may be used with crystals that do not violate the sample frequency specifications. Note that these bits can be disabled and controlled by 122. CFS2-CFS0 can only be changed while MCE (R0) is set: XTAL1 XTAL2

Divide 24.576MHz 16.9344MHz

0 - 3072 8.0 kHz 5.51 kHz

. ⁸⁴ SUBSTTTUTE SHEET (RULE 26) 1 - 1536 16.0 kHz 1 1.025 kH2

2 - 896 27.42 kHz 18.9 kHz

3 - 768 32.0 kHz 22.05 kHz

4 - 448 N/A 37.8 kHz

5 - 384 N/A 44.1 kHz

6 - 512 48.0 kHz 33.075 kHz

7 - 2560 9.6 kHz 6.62 kHz; and

S/M Stereo/Mono Select: This bit determines how the audio data streams are formatted. Selecting stereo will result in alternating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels. Mono capture only captures data from the left channel. In MODE 1 , this bit is used for both playback and capture. In MODE 2, this bit is only used for playback, and the capture format is independently selected via 128. MCE (R0) or PMCE (116) must be set to modify S/M: 0 - Mono; and

1 - Stereo

C/L, FMTl , and FMTO bits set the audio data format as shown in TABLE 58. In MODE

1, FMTl, which is forced low, FMTO, and C/L are used for both playback and capture. In

MODE 2, these bits are only used for playback, and the capture format is independently selected via register 128. MCE (R0) or PMCE (116) must be set to modify the lower four bits of this register. See Changing Audio Data Formats section for more details.

FIGURE 270 is a diagram of the bitfield of Interface Configuration (19, default = 00x01000). The bitfields are decoded as follows:

PEN Playback Enable. This bit enables playback. The WSS Codec will generate a DRQ and respond t DACK signal when this bit is enabled and PPIO = 0. If

PPIO = 1 , PEN enables PIO playback mode. PEN may be set and reset without setting the MCE bit:

0 - Playback Disabled (playback DRQ and PIO inactive); and

1 - Playback Enabled; CEN Capture Enabled. This bit enables the capture of data. WSS Codec 204 will generate a DRQ and respond to DACK signal when CEN is enabled and CPIO

85

SUBSTTTUTE SHEET (RULE 26) = 0. If CPIO = 1 , CEN enables PIO capture mode. CEN may be set and reset without setting the MCE bit:

0 - Capture Disabled (capture DRQ and PIO inactive); and

1 - Capture Enabled; SDC Single DMA Channel: This bit will force BOTH capture and playback DMA requests to occur on the Playback DMA channel. This bit forces WSS Codec 204 to use one DMA channel. Should both capture and playback be enabled in this mode, only the playback will occur: 0 - Dual DMA channel mode; and 1 - Single DMA channel mode;

CAL1,0 Calibration: These bits determine which type of calibration WSS Codec 204 performs whenever the Mode Change Enable (MCE) bit, R0, changes from 1 to 0. The number of sample periods required for calibration is listed in parenthesis:

0 - No calibration (0, 40 the first time); 1 - Converter calibration (136);

2 - DAC calibration (40); and

3 - Full calibration (168);

PPIO Playback PIO Enable: This bit determines whether the playback data are transferred via DMA or PIO: 0 - DMA transfers; and

1 - PIO transfers;

CPIO Capture PIO Enable: This bit determines whether the capture data are transferred via DMA or PIO: 0 - DMA transfers; and I - PIO transfers.

This register, except bits CEN and PEN, can only be written while in Mode Change Enable (either MCE or PMCE).

FIGURE 27P is a diagram of the bitfields of Pin Control (110, default = OOOOOOOx). The bitfields are: res Reserved. Must write 0, could read as 0 or 1;

86

SUBSTTTUTE SHEET (RULE 26) IEN Interrupt Enable: This bit enables the interrupt pin. The Interrupt pin will reflect the value of the INT bit of the Status register (R2). The interrupt pin is active high:

0 - Interrupt disabled; and 1 - Interrupt enabled;

DTM DMA Timing Mode. Mode 2 only. When set, causes the current DMA request signal to be deasserted on the rising edge of the IOW or IOR strobe during the next to last byte of a DMA transfer. When DTM = 0 the DMA request is released on the falling edge of the IOW or IOR during the last byte of a DMA transfer; DEN Dither Enable : When set, triangular pdf dither is added before truncating the ADC

16-bit value to 8-bit, unsigned data. Dither is only active in the 8-bit unsigned data mode:

0 - Dither enabled; and

1 - Dither disabled; OSM1-

OSM0 These bits are enabled by Setting SRE = 1 in register 122. These bits in combination with DIV5-DIV0 and CS2 (122) determine the current sample rate of WSS Codec 204 when SRE = 1 :

00 - 12kHz < Fs a 24 kHz; 01 - Fs > 24 kHz;

10 - Fs a 12 kHz; and

1 1 - reserved; and. XCTL 1 -XCTL0 XCTL Control:

0 - TTL logic low on XCTL 1,0 pins; and 1 - TTL logic high on XCTL 1 ,0 pins.

FIGURE 27Q is a diagram of the bitfields of Error Status and Initialization (11 1. Read Only, default = 00000000). The bitfields are decoded as: ORL1-

ORLO Overrange Left Detect: These bits determine the overrange on the left ADC channel. These bits are updated on a sample by sample basis:

0 - Less than -1.5dB;

1 - Between -1.5dB and OdB;

87

SUBSTTTUTE SHEET (RULE 26) 2 - Between OdB and 1.5dB overrange; and

3 - Greater than 1.5dB overrange; ORR1-

ORR0 Overrange Right Detect: These bits determine the overrange on the Right ADC channel:

0 - Less than -1.5dB;

1 - Between -1.5dB and OdB;

2 - Between OdB and 1.5dB overrange; and

3 - Greater than 1.5dB overrange; DRS DRQ Status: This bit indicates the current status of the DRQs assigned to the

WSS Codec:

0 - Capture AND Playback DRQs are presently inactive; and

1 - Capture OR Playback DRQs are presently active;

ACI Auto-calibrate In-Progress: This bit indicates the state of calibration: 0 - Calibration not in progress; and

1 - Calibration is in progress; PUR Playback underrun: This bit is set when playback data has not arrived from the host in time to be played. As a result, if DACZ = 0, the last valid sample will be sent to DACs 110. This bit is set when an error occurs and will not clear until the Status register (R2) is read; and

COR Capture overrun: This bit is set when the capture data has not been read by the host before the next sample arrives. The old sample will not be overwritten and the new sample will be ignored. This bit is set when an error condition occurs and will not clear until the Status register (R2) is read. The SER bit in the Status register (R2) is simply a logical OR of the COR and PUR bits.

This enables a polling host CPU to detect an error condition while checking other status bits.

FIGURE 27R is a diagram of the bitfield of ODE and ID (112, default = lOxxlOlO). The bitfields are decoded as follows:

ID3-ID0 Codec ID: These four bits indicate the ID and initial revisions of the codec. Further revisions are expanded in indirect register 25. These bits are read only: 0001 - Rev A;and 1010 - Rev B; res Reserved. Must write 0, could read as 0 or 1 ;

MODE 2 MODE 2: Enables the expanded mode of the CS4232. Must be set to enable access to indirect registers 16-31 and their associated features: 0 - MODE 1 : CS4248 "look-alike"; and

1 - MODE 2: Expanded features. FIGURE 27S is a diagram of the bitfield of Loopback Control (113. default = 000000x0). The bitfields of this register are decoded as follows:

LBE Loopback Enable: When set to 1 , the ADC data are digitally mixed with data sent to the DACs:

0 - Loopback disabled; and

1 - Loopback enabled; res Reserved. Must write 0, could read as 0 or 1 ; and LBA5- LBAO Loopback Attenuation: These bits determine the attenuation of the loopback from

ADC to DAC. The least significant bit represents -1.5dB. with 000000 = OdB.

FIGURE 27T is a diagram of the bitfield of Playback Upper Base (114, default = 00000000) The bitfields of this register are decoded as follows:

PUB7-PUB0 Playback Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. The Current Count registers cannot be read. When set for MODE 1 or SDC, this register is used for both the Playback and Capture Base registers. FIGURE 27U isa a diagram of the bitfield of Playback Lower Base (115, default = 00000000). The bitfields of this register are decoded as Follows:

PLB7-PLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. When set for MODE

1 or SDC, this register is used for both the Playback and Capture Base registers. FIGURE 27V is a diagram of the bitfield of Alternate Feature Enable I (116, default = 00000000). The bitfields of this register are decoded as follows:

DACZ DAC Zero: This bit will force the output of the playback channel to AC zero when an underrun error occurs: 1 - Go to center scale; and

0 - Hold previous valid sample;

SPE Serial Port Enable. When enabled, audio data from the ADCs is sent out

SDOUT and audio data from SDLN is sent to the DACs:

1 - Enable serial port; and

0 - Disable serial port. ISA Bus used for audio data; SF1, SF0 Serial Format. Selects the format of the serial port when enabled by SPE:

0 - 64-bit enhanced;

1 - 64-bit;

2 - 32-bit; and

3 - Reserved;

PMCE Playback Mode Change Enable. When set, it allows modification of the stereo/mono and audio data format bits (D7-D4) for the playback channel, 18. MCE in R0 must be used to change the sample frequency;

CMCE Capture Mode Change Enable. When set, it allows modification of the stereo/mono and audio data format bits (D7-D4) for the capture channel, 128. MCE in R0 must be used to change the sample frequency in 18;

TE Timer Enable: This bit. when set, will enable the timer to run and interrupt the host at the specified frequency in the timer registers; and

OLB Output Level Bit: Provided for backwards compatibility, internally providing a typical output full-scale voltage of 2.8Vpp.

FIGURE 27W is a diagram of the bitfield of Alternate Feature Enable II (I17,default = 0000x000). The bitfields of this register are decoded as follows:

HPF High Pass Filter: This bit enables a DC-blocking high-pass filter in the digital filter of the ADC. This filter forces the ADC offset to 0:

0 - disabled; and

1 - enabled;

XTALE Crystal Enable;

90

SUBSTTTUTE SHEET (RULE 26) res Reserved. Must write 0, could read as 0 or

APAR ADPCM Playback Accumulator Reset. While set, the Playback ADPCM accumulator is held at zero. Used when pausing a playback stream; and TEST Factory Test. These bits are used for factory testing and must remain at 0 for normal operation.

FIGURE 27X is a diagram of the bitfield of Left Line Input Control (118, default = lxxOlOOO). The bitfields of this register are described as follows:

LLG4-LLG0 Left line, LLINE, Mix Grain. The least significant bit represents 1.5dB, with 01000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and

LLM Left Line Mute. When set to 1, the left Line input, LLINE, to the mixer, is muted. FIGURE 27Y is a diagram of the bitfield of Right Line Input Control (119, default = lxxOlOOO). The bitfields of this register are decoded as follows: RLG4-

RLG0 Right Line, RLINE, Mix Gain. The least significant bit represents 1.5dB, with

01000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and

RLM Right Line Mute. When set to 1 , the Right Line input. RLINE, to the mixer, is muted.

FIGURE 27Z is a diagram of the bitfield of Timer Lower Base (120, default = 00000000). The bitfields of this register are decoded as follows:

TL7-TL0 Lower Timer Bits: This is the low order byte of the 16-bit timer base register. Writes to this register cause both timer base registers to be loaded into tne internal timer, therefore, the upper timer register should be loaded before the lower. Once the count reaches zero, an interrupt is generated, if enabled, and the timer is automatically reloaded with these base registers. FIGURE 27AA is a diagram of the bitfield of Timer Upper Base (121, default = 00000000). The bitfields of this register are decoded as follows:

91

SUBSTTTUTE SHEET (RULE 26) TU7-TU0 Upper Timer Bits: This is the high order byte of the 16-bit timer. The time base is determined by the clock source selected from either C2SL in 18 or CS2 in 122; C2SL = 0 - divide XTALI by 245 (24.576 MHz - 9.969 ms); and C2SL = 1 - divide XTAL2 by 168 ( 16.9344 MHz - 9.92 ms).

FIGURE 27AB is a diagram of the bitfield of Alternate Sample Frequency Select (122, default = 00000000). The bitfields of this register are decoded as follows:

CS2 Crystal 2 Select. This bit selects the clock source used for generating the audio sample rate: 0 - XTAL 1 = 24.576 MHz; and

1 - XTAL2 = 16.9344 MHz; DIV5 - DIVO Clock Divider. These bits select the audio sample frequency for both capture and playback: Fs = (2*XTAL)/(M*N); XTAL = 24.576 MHz CS2 = 0;

XTAL = 16.9344 MHz CS2 = 1; N = DIV5-DIV0;

16 < N < 49 for XTAL = 24.576 MHz; 12 <_N < 33 for XTAL = 16.9344 MHz; (M set by OSMl,0 in I10);

M = 64 for Fs > 24 kHz; M = 128 for 12 kHz < Fs a 24 kHz ; and M = 256 for Fs a 12 kHz; SRE Alternate Sample Rate Enable. When this bit is set to a one, bits 0-3 of 18 will be ignored, and the sample frequency is then determined by CS2, DIV5-DIV0, and the oversampling mode bits OSM1, OSM0 in 110. FIGURE 27AC is a diagram of the bitfield of Alternate Feature Enable III (123, default = xxxxxxxO). The bitfields of this register are decoded as follows:

ACF ADPCM Capture Freeze. When set, the capture ADPCM accumulator and step size are frozen. This bit must be set to zero for adaptation to continue. This bit is used when pausing a ADPCM capture stream; res Reserved. Must write 0, could read as 0 or 1 ;

92

SUBSTTTUTE SHEET (RULE 26) FIGURE 27AD is a diagram of the bitfield of Alternate Feature Status (124, default = xOOOOOOO). The bitfields of this register are decoded as follows:

PU Playback Underrun: This bit, when set, indicates that the DAC has run out of data and a sample has been missed; PO Playback Overrun: This bit, when set, indicates that the host attempted to write data into a full FIFO and the data was discarded; CO Capture Overrun: This bit, when set, indicates that the ADC had a sample to load into the FIFO but the FIFO was full. In this case, this bit is set and the new sample is discarded; CU Capture Underrun: This bit indicates that the host has read more data out of the

FIFO than it contained. In this condition, the bit is set and the last valid byte is re-read by the host; PI Playback Interrupt: This bit indicates that an interrupt is pending from the playback DMA count registers; Cl Capture Interrupt: This bit indicates that an interrupt is pending from the capture

DMA count registers; TI Timer Interrupt: This bit indicates that an interrupt is pending from the timer count registers; and res Reserved. Must write 0, could read as 0 or 1. The PI, Cl, and TI bits are reset by writing a "0" to the particular interrupt bit or by writing any value to the Status register (R2). FIGURE 27AE is a diagram of the bitfield of Mono Input and Output Control (126, default = 101x0000). The bitfields of this register are decoded as follows: MIA3- MIA0 Mono Input Attenuation. When MIM is 0, these bits set the level of MIN summed into the mixer. MIA0 is the least significant bit and represents 3dB attenuation, with 0000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ;

MBY Mono Bypass. MBY connects MTN directly to MOUT (FIGURE 1) attenuation of 9dB. When MBY = 1, MIM should be 1.0 - MIN not connected directly to

MOUT.l - MIN connected directly to MOUT; MOM Mono Output Mute. The MOM bit will mute the mono mix output, MOUT. This mute is independent of the line output mute:

0 - no mute; and

1 - mute; MIM Mono Input Mute. Controls the mute function on the mono input, MIN (FIGURE

1). The mono input provides mix for the "beeper" function in most personal computers. When MIM = 0, MBY should by 0:

0 - no mute; and

1 - muted. FIGURE 27AF is a diagram of the bitfield of Left Output Attenuation (127, default =

OxxxOOOO). The bitfields of this register are decoded as follows: LOA3-

LOA0 Left Output Attenuation. LOAO is the least significant bit and represents -2dB attenuation, with 0000 = OdB; res Reserved. Must write 0, could read as 0 or 1; and

LOM Left Output Mute. The LOM bit will mute the left output:

0 - no mute; and

1 - mute.

FIGURE 27AG is a diagram of the bitfield of Capture Data Format (128, default = OOOOxxxx). The bitfields of this register are decoded as follows: res Reserved. Must write 0. could read as 0 or 1 ; and

S/M Stereo/Mono Select: This bit determines how the capture audio data stream is formatted. Selecting stereo will result with alternating samples representing left and right audio channels. Selecting mono only captures data from the left audio channel. MCE (R0) or CMCE (116) must be set to modify S/M:

0 - Mono; and

1 - Stereo;

C/L, FMTl, FMTO set the capture data format in MODE 2. The capture data format can be different from the playback data format; however, the sample frequency must be the same and is set in 18. MCE (R0) or CMCE (116) must be set to modify this register.

FIGURE 27AH is a diagram of the bitfields of Right Output Attenuation (129, default - OxxxOOOO). The bitfields of this register are decoded as follows:

94

SUBSTTTUTE SHEET (RULE 26) ROA3-

ROA0 Right Output Attenuation. ROA0 is the least significant bit and represents -2dB attenuation, with 0000 = OdB; res Reserved. Must write 0, could read as 0 or 1 ; and ROM Right Output Mute. The ROM bit will mute the right output:

0 - no mute; and

1 - mute.

FIGURE 27AI is a diagram of the bitfield of Capture Upper Base (130, default = 00000000). The bitfields of this register are decoded as follows: CUB7-

CUB0 Capture Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Capture Base register. Reads from this register returns the same value that was written. FIGURE 27AJ is a diagram of the bitfields of Capture Lower Base (131, default = 00000000). The bitfields of this register are decoded as follows:

CLB7-

CLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Capture Base register. Reads from this register returns the same value which was written. The extended registers TABLE 52C are accessed by placing the appropriate index in the

Index Address register (R0) and then accessing the Indexed Data register (RI). A detailed description of each indirect register is given below. All reserved bits should be written zero and may be 0 or 1 when read. Indirect registers 16-31 are only available when the MODE 2 bit in MODE and ID register (112) is set. FIGURE 27AK is a diagram of the bitfields of Left Alternate FM Input Control (X0, default = 00000000). The bitfields of this register are decoded as follows: LL2G3-

LL2G0 Left Alternate Input Gain. The least significant bit represents +1.5dB, with 01000 = OdB; LL20M Left Alternate Mute to output mixer;

LL21M Left Alternate gain block mute to input mixer; and

LL2M Left Alternate mute to input mixer.

95

SUBSTTTUTE SHEET (RULE 26) FIGURE 27AL is a diagram of the bitfields of Right Alternate FM Input Control (XI, default = 00000000). The bitfields of this register are decoded as follows: RL2G3-

RL2G0 Right Alternate Input Gain. The least significant bit represents +1.5dB, with 01000 = OdB;

RL2OM Right Alternate Mute to output mixer;

RL2IM Right Alternate gain block mute to input mixer; and

RL2M Right Alternate mute to input mixer.

FIGURE 27 AM is a diagram of the bitfields of Left Mic Input Control (X2, default = 00000000). The bitfields of this register are decoded as follows:

LMCG4- LMCG0 Left Mic Input Gain. The least significant bit represents +1.5dB, with

00111 = 0dB; LMBST Left Mic 19.5dB boost enable to output mixer; LLM Left Mic mute to output mixer; and

LMIM Left Mic mute to input mixer.

FIGURE 27 AN is a diagram of the bitfields of Right Mic Input Control (X3, default = 00000000). The bitfields of this register are decoded as follows: RMCG4- RMCGO Left Mic Input Gain. The least significant bit represents +1.5dB, with

00111 = 0dB; RMBST Left Mic 19.5dB boost enable to output mixer;

RLM Left Mic mute to output mixer; and

RMIM Left Mic mute to input mixer. FIGURE 27AO is a diagram of the bitfield of Control (X4, default = 00000100). The bitfields of this register are decoded as follows: MTE Mixer Test Mode Enable;

IS 1 Redirects accesses to 118, 119 to X6, X7 when IFM = 1 : 0 = no redirection; and 1 = redirection enabled;

ISO Redirects accesses to 118 and 119 to X 16 and X 17 when WTEN = 1 : 0 = redirection enabled; and

96

SUBSTTTUTE SHEET (RULE 26) 1 = no redirection; IFM Internal FM - when this bit is a one the Internal FM block is enabled; LIS1-

LISO Left Mixer Summer Attenuator 00 = OdB;

01 = -6dB; 10 = -12dB; and l l = -18dB; and MIMR Right channel mono mute to output mixer: 0 - unmute; and

1 - muted. FIGURE 27AP is a diagram of the bitfield of Control (X5, default = 00000000). The bitfields of this register are decoded as follows:

DIFMIC Differential Mic Input Enable. When this bit is set to a one the right channel Mic input is inverted and combined with the non-inverted left channel input. The presummer gain block to the output mixer is also set to 13.5db; RIS 1 -RIS0 Right Mixer Summer Attenuator: 00 = OdB; 01 = -6dB;

10 = -12dB; and l l = -18dB; and MOMR Right channel mono mute to output mixer:

0 - unmute; and 1- muted.

FIGURE 27AQ is a diagram of the bitfields of Left FM Volume Control (X6, default = 10111111). The bitfields of this register are decoded as follows: LFMA5-

LFMA0 Left FM volume control. Least significant bit represents 1.5dB, with 000000 = OdB; and

LFMM Left FM volume mute:

0 - ummute; and

97

SUBSTTTUTE SHEET (RULE 26) 1 - muted. FIGURE 27AR is a diagram of the bitfield of Right FM Volume Control (X7, default = 10111111). The bitfields of this register are decoded as follows: RFMA5- RFMAO Right FM volume control. Least significant bit represents 1.5dB, with

000000 = OdB; RFMM Right FM volume mute:

0 - unmute; and

1 - muted. FIGURE 27 AS is a diagram of the bitfield of Left DSP Serial Port Volume Control (X8, default = 00000000). The bitfields of this register are decoded as follows: LSPA5-

LSPA0 Left DSP Serial Port volume control. Least significant bit represents

1.5dB, with 000000 = OdB; and LSPOM Left DSP Serial Port volume mute:

0 - unmute; and

1 - muted.

FIGURE 27AT is a diagram of the bitfield of Right DSP Serial Port Volume Control (X9, default = 00000000). The bitfields of this register are decoded as follows: RSPA5-

RSPA0 Right DSP Serial Port volume control. Least significant bit represents

1.5dB, with 000000 = OdB; RSPOM Right DSP Serial Port volume mute:

0 - unmute; and 1 - muted.

FIGURE 27AU is a diagram of the bitfield of Right Digital Loopback Volume Control (X10, default = 00111111). The bitfields of this register are decoded as follows: RLBA5-

RLBA0 Right Digital Loopback volume control. Least significant bit represents 1.5dB, with 000000 = OdB; and

SLBE Stereo Loopback Volume Control Enable. When this bit is set to a one the Digital Loopback Volume control becomes stereo with 113 controlling

98

SUBSTTTUTE SHEET (RULE 26) the left channel volume and bits D5-D0 of this register controlling the right volume:

0 - Mono; and

1 - Stereo. FIGURE 27AV is a diagram of the bitfield of DAC, SRC Confrol (XI 1, default =

11000000). The bitfields of this register are decoded as follows:

SRCE Sample Rate Converter Enable. When this bit is set to a one the Capture and

Playback sample rates are set by registers XI 2 and XI 3; RDIM Right DAC mute into the input mixer. This bit is not affected by a change to Mode 1 or Mode 2; and

LDIM Left DAC mute into the input mixer. This bit is not affected by a change to Mode

1 or Mode 2. FIGURE 27AW is a diagram of the bitfield of Capture Sample Rate Control (X12,default = 001 10000). The bitfields of this register are decoded as follows: CSR7-CSR0 Sets the sample rate for the A/D.

FIGURE 27AX is a diagram of the bitfield of Playback Sample Rate Control (X13, default = 00110000). The bitfields of this register are decoded as follows: PSR7-PSR0 Sets the sample rate for the A/D.

FIGURE 27AY is a diagram of the bitfield of Left PCM Audio Volume Control (XI 4, default = 00000000). The bitfields of this register are decoded as follows:

LPA7- LPA0 Left PCM Audio Volume Control. Least significant bit represents 1.5dB, with

000000 = OdB. FIGURE 27AZ is a diagram of the bitfields of Right PCM Audio Volume Control (X15, default = 00000000). The bitfields of this register are decoded as follows:

RPA7- RPAO Right PCM Audio Volume Control. Least significant bit represents 1.5dB, with

000000 = OdB. FIGURE 27BA is a diagram of the bitfields of Left Wavetable Volume Control (XI 6, default = 10000000).The bitfields of this register are decoded as follows:

LPA7-LPA0 Left wavetable Audio Volume Control. Least significant bit represents 1.5dB, with 000000 = +12dB. FIGURE 27BB is a diagram of the bitfield of Right Volume Control (XI 7. default = - 10000000). The bitfields of this register are decoded as follows:

RB7-RB0 Right Wavetable Audio Volume Control. Least significant bit represents

1.5dB, with 000000 = +12dB. Some operating modes of Codec/mixer 204 will require that microcontroller 103 and ISA

Bus both have access to the Codec data bus. An example of this is when microcontroller 103 is updating the Codec/mixer 204 mixer registers for Sound Blaster Pro functions while DMA audio is being transferred over the data bus. To arbitrate between the two devices a software arbitration scheme is used. Each Sound Blaster command (ISA write to Sound Blaster base + C) causes the ISA Bus signal IOCHRDY to be forced low thereby holding the current bus cycle (DMA cycles held off). Codec 100 makes use of this time and microcontroller 103 is guaranteed access to the codec for mixer updates. Once IOCHRDY is released, after microcontroller 103 has finished accessing the codec, the current bus cycle is allowed to complete.

A context switch mechanism is provided to enable switching between Sound Blaster mode and Windows Sound System mode transparently to the user. Logic detects when a mode change from Sound Blaster to Sound System occurs and an interrupt is generated to microcontroller 103. The switch from Sound System to Sound Blaster is done by microcontroller 103 without any additional external logic support. Optionally a ISA Bus interrupt may be generated upon detection of a Context Switch provided the interrupt is enabled via Codec 100 Miscellaneous Control Reg. (base +0). FIGURE 28 is a timing diagram of a typical context switching operation.

When a context switch from Sound Blaster to WSS mode occurs IOCHRDY is forced low. The current ISA bus access to codec/mixer 204 is thereby held off until the interrupt has been acknowledged by microcontroller 103. The "Context Switch" is only recognized (enabled) when the WSS and Sound Blaster physical devices are enabled. Accordingly IOCHRDY is not driven low during a Context Switch unless both the WSS and Sound Blaster devices are enabled.

A context switch from Sound Blaster to WSS mode results in codec/ mixer 204 being set to mode 1 operation and the SRE and CMCE bits will be set to zero. No other register bits are affected. A context switch from WSS to Sound Blaster mode results in the mixer registers being restored to values that existed the last time Codec 100 was in Sound Blaster mode. In other words during context switches Sound Blaster mixer settings ace retained while WSS mixer settings are not.

In Codec 100 the context switch from WSS to Sound Blaster mode occurs during the first access to the Sound Blaster Command register or a "Sound Blaster Reset Command". FIGURE 29 is a diagram of the External Peripheral Port 109. External Peripheral Port is a general purpose programmable port that is used to connect external devices to the ISA bus with a minimum of glue logic. The External Peripheral interface includes buffers 2901 and decode-strobe generation logic 2902 to provide an independent data path to the external synthesizer chip and CDROM IDE interface. The External Peripheral Port buffers the ISA data bus and SA2:SA0 address lines, generates Read and Write strobes, and provides programmable

I/O base address decoding, and DMA/Interrupt mapping. The XIOR/ and XIOW/ strobes are generated by gating the IOR/ and IOW/ signals with the CDCS0/, CDCS1/, SCS/, and MODEMCS/ chip selects. The timing of External Peripheral port reads and writes is shown in FIGURES 30A and 30B. Synthesizer Interface 123 may be used to provide a direct connection to an OPL3/4 synthesizer chip. The interface consists of an address decoder 3101 (see FIGURE 31 which emphasizes the synthesizer and CDROM interfaces) and an input for an interrupt The other signals such as address bits and read/write strobes are provided by the External Peripheral Port. Address decoder generates a chip select. The address that is decoded is determined by data that is written during a Plug & Play configuration sequence. The chip select is a logical OR of the synthesizer (Adlib) decode and Sound Blaster synthesizer decode. The interrupt is mapped onto the ISA bus depending on the configuration defined during the Plug & Play sequence. synth chip select = decode of synthesizer ISA address (338:33B) OR decode of Sound Blaster base address (0:3 and 8:9) The CDROM interface (see also FIGURE 31) provides a connection to CDROM drives

3103. The interface consists of programmable address decoders 3101 and 3102 to act as a device selects, DMA request and acknowledge mapping, and interrupt mapping. A Plug & Play sequence will determine the base address and specific DMA and interrupt mapping. Various CDROM interfaces such as Mitsumi, Sony, Panasonic, and Enhanced IDE are supported. The other signals required for the CDROM interface are provided by the External Peripheral Port.

FIGURE 32 emphasizes the clocking scheme for codec 100. Microcontroller 103 clock requirement is a non-overlay 2-phase clock that is under 17.5MHz in frequency. The 16.9344MHz clock fits this criteria. Microcontroller 103 Timer 2, which is used as the MIDI baud rate generator, is always clocked via an externally generated clock that is derived from the 16.9344MHz crystal /17 or 996.141 kHz. The other requirement is a 2-phase non-overlap clock. The non-overlap must > =5ns. The microcontroller clock is generated by 2-phase non-overlap clock generator 3201.

In Codec 100 the ADC and DAC operate at a fixed sample frequency of 44.1 kHz. Sample rate converters are used to convert between variable system sample rates and the 44.1 kHz required by converters 114/115. The analog clock for the converter switched capacitor filters operates at a fixed 128fs frequency. The delta-sigma modulators operate at a fixed 256fs clock rate.

The internal FM clock uses the 16.9344MHz 384fs clock.

A large number of available sample rates are provided by two independent sample rate converters 112; one for capture and one for playback. Sample rate converters 112 convert from a variable rate to a fixed 44.1 kHz rate. The sample frequency is determined by a register value that is used to index a ROM 3202. ROM 3202 stores the coefficients used by the sample rate converter to perform the rate conversion.

FIGURE 33 is a diagram of the Game Port which provides an interface to a standard personal computer type joystick. The joystick (JOYSTICK, FIGURE 1) interface supports two joysticks and four push buttons. The ISA interface to the Game Port includes an address decoder and read/write strobe generator.

The Game Port hardware interface consists of four 555 like timers 3301 (two of which are shown for reference), read/write strobe generator 3305, address decode 3303 and data buffer 3304. A selected joystick itself consists of two 100K potentiometers 3302; one (3302a) for the x-axis and one (3302b) for the y-axis. As the joystick position is varied the resistance of the x and y axis potentiometers will also vary in direct proportion to the joystick movement. In addition one-to-four push buttons 3306 may be included, two of which (3303 a and 3303 b) are shown in FIGURE 33. One timer 3301 is connected to each potentiometer. Two joysticks therefore require four timers. Once triggered the timer output pulse width is determined by the output current supplied by the timer, the joystick potentiometer resistance, and an external capacitor. Host software on the personal computer continually reads the timer pulse outputs and determines joystick position depending on the width of the pulses. The state of the push buttons are also monitored by the host software.

102

SUBSTTTUTE SHEET (RULE 26) Digital Pulse Width = 24.2usec + 0.011 (r)usec r = resistive load Codec 100 provides for four selectable time constants. The default should match the one above and the others should offer shorter time constants.

Programmable speed control is implemented by selecting one of four reference voltages that is fed to the input of a comparator. The other input to the comparator is connected to the external joystick RC circuit. The four selectable reference voltages allow the trip-point of the comparator to be varied over a range of voltages associated with a typical RC generated curve.

The speed confrol variation is illustrated in FIGURE 34.

To minimize the noise effects of large di dt currents generated by the discharge of the external .0056uF capacitor the following techniques are used:

1 ) Separate analog ground for capacitor discharge devices;

2) Discharge control will be synchronized to the internal noise-managed digital clock; and

3) Sequential, two-step discharge, (small device first, large device later). FIGURE 35 is a timing diagram illustrating the joystick port timing. This timing generally follows the following routine:

1) DIS1 & DIS2 must be driven low on the first noise-managed clock after a valid joystick 10W;

2) COMPJ output will go low T=RC later; 3) DIS1 must be raised on the first noise-managed clock edge after COMPJ output goes low;

4) DIS2 should go high - lused: after DIS1 (DIS2 high will cause COMPJ output to go high); and

5) In powerdown (PDN active), DIS 1 & DOS2 must be low. In order to support Microsoft's Directlnput™ specification for digitally assisted joysticks the Codec 100 includes the features described below.

FIGURE 36A generally describes joystick interface 105. A more detailed illustration of circuitry 3601 of FIGURE 36A is provided as 36B.

Joystick coordinate block 3601 includes a 16-bit up-counter 3603 and latch 3604 for each joystick input for each joystick (i.e., a total of four). The counters all operate in parallel via the same clock (XTAL/2) with each counter gated by its corresponding joystick coordinate enable.

Each individual enable signal is generated by the joystick COMPJ blocks 3602. COMPJ blocks

103

SUBSTTTUTE SHEET (RULE 26) 3602 produce a pulse in whose length is defined by the current joystick position. The trigger for COMPJ block 3602 is initiated by an ISA bus write to the Game Port address base + [0..5] or by a microcontroller 103 write to memory address 0x38. In the normal operating mode one trigger is produced per ISA bus write, but when the Auto Re-trigger Enable bit is set, the circuit becomes self-triggering and further ISA bus or microcontroller 103 writes are not required. However the host is still able to generate a trigger by performing a write to the Game Port base [0..5].

Each counter increments for a period of time defined by the enable. At the end of the current pulse (trigger) period, as defined by the longest COMPJ pulse, the current counter values are clocked into the holding registers and the counters are reset. The holding registers may then be read by microcontroller 103 in response to an ISA bus read of Game Port address base +7.

Each holding register requires that two addresses (16-bits) be mapped into microcontroller 103 address space. This results in eight addresses being required in total (addresses 0x38 through 0x3F). In order for microcontroller 103 to accurately read the holding registers (there is a possibility that microcontroller 103 read could occur at the same time as the holding register is clocked), a hardware locking mechanism prevents clocking of the holding registers while microcontroller 103 is in processes of accessing the registers.

Each joystick, joystick A and joystick B, independently controls the clocking of each X, Y counter pair. In other words the XI and Yl counters follow the joystick A movement only, and the X2 and Y2 counters follow the joystick B movement only. The XI, Yl and X2, Y2 counters do not wrap around. When a maximum count value of

OxFFFF is reached, the counter is prevented from incrementing further and the OxFFFF count is held until the next one-shot trigger pulse occurs (which resets the counters to zero). This prevents unconnected joysticks from generating false count values. In normal operation the X,Y position counters should never reach a count value of OxFFFF. In order to provide support for joystick digital assist the PO address decoding for the standard joystick is changed as follows:

1) Game Port address range remains at eight bytes;

2) Standard joystick access occurs at addresses Game Port Base Address + 0 through 5. A write to any of these addresses causes a trigger of the one-shots. A read from any of these addresses puts the current one-shot and button data onto the

ISA bus;

104 SUBSTTTUTE SHEET (RULE 26) 3) The Joystick Digital Assist register is located at Game Port Base + 7. A read or write of Game Port Base + 7 interrupts microcontroller 103 with a PORTI. value of 0x5C (write) and 0x5E(read); and

4) Access to Game Port Base + 6 is reserved for future use. A read or write access to Game Port Base + 6 will interrupt microconfroller 103 and generate a PORTI value of 0x58(write) and 0x5A(read). Host control and data access of the Joystick Digital Assist function occurs via a read/write port at the GamePort (base+7) address. An ISA bus read or write cycle to this address interrupts microcontroller 103 via INTI and IOCHDRY is forced low. Also a interrupt identifier of 0x5C(write) or 0x5E(read) is placed on PORTI. Microcontroller 103 responds by either a read of microcontroller 103 address 0 (ISA write) or writing to microcontroller 103 address 0x00 (ISA read). All Joystick Digital Assist commands to read joystick positional data or control its operation are sent through this port.

Microcontroller 103 may access the Digital Assist Registers at any time, but data integrity is only guaranteed with the following sequence. Microcontroller 103 read from address 0x38 (XI

Position Low Byte) will cause the hardware to prevent any further updates of the Digital Assist Position Registers. Microcontroller 103 may then continue reading the other Digital Assist Position registers. As the Digital Assist Position Registers are being accessed by microcontroller 103, the one-shot counters will continue to be updated by auto-retrigger pulses in the background. Upon the final read of address 0x3F (Y2 position high byte) the clocking of the Digital Assist

Position Registers will be enabled. Digital Assist Position Registers will then be clocked at the end of the next one-shot pulse period.

FIGURE 37A is a diagram of the bitfields of Digital Assist Control/Status at microconfroller 103 address=0x37. The bitfields of this register are decoded as follows:

ARE When this bit is set to a one, each X,Y one-shot will be

(Auto automatically retriggered at the end of the current one-shot time

R e t r i g g e r out period. The transition of ARE from a one to a zero should not

Enable) initiate a trigger. Once ARE has been set to a one, a trigger must be either initiated by either a host write to Gameport Base + 0-5 or via a microcontroller 103 write to address 0x38. Once the initial trigger occurs no further triggers are required by the host or microcontroller 103. The end of m"e ohe^shot time out period rs defined as the trailing edge of the longest one-shot pulse (X or Y). Each X,Y coordinate pair is treated as an independent block. In other words the absolute retrigger pulse timing is unique for each connected joystick: joystick #1, joystick #2. This bit must be read/ write. When ARE transitions from a 1 to a 0 the trigger sequence in progress will complete and the last count value is transferred to the holding latches before further triggers are disabled;

Y2 This bit represents the current state of the #2 joystick Y coordinate one-shot. A one indicates that the one-shot has been triggered. A zero means the current trigger pulse cycle has ended. Read Only;

X2 This bit represents the current state of the #2 joystick X coordinate one-shot. A one indicates that the one-shot has been triggered. A zero means the current trigger pulse cycle has ended Read Only;

Yl This bit represents the current state of the #1 joystick Y coordinate one-shot. A one indicates that the one-shot has been triggered. A zero means the current trigger pulse cycle has ended Read Only;

XI This bit represents the current state of the #1 joystick X coordinate one-shot. A one indicates that the one-shot has been triggered. A zero means the current trigger pulse cycle has ended Read Only.

FIGURE 37B is a diagram of the bitfields of Joystick Trigger/Xl Position Data Low Byte controller 103 address=0X38. The bitfields of this register are decoded as follows:

Write This register when written by microcontroller 103 will initiate a trigger of the joystick one-shots on the trailing edge of the write pulse. Read This register when read will return the low byte of the last known

16-bit position of the j oystick #1 X coordinate. Also any further updates of all X, Y Position Data registers are suspended until a read from microcontroller 103 address 0x3F occurs. FIGURE 37C is a diagram of the bitfields of XI Position Data High Byte at microcontroller 103 address=0x39. The bitfields of this register are decoded as follows. This register when read will return the high byte of the last known 16-bit position of the joystick #1 X coordinate.

FIGURE 37D is a diagram of the bitfields of Yl Position Data Low Byte at microcontroller 103 address=0x3A. The bitfields of this register are decoded as follows. This register when read will return the low byte of the last known 16-bit position of the joystick #1

Y coordinate. FIGURE 37E is a diagram of the bitfields of Yl Position Data High Byte at microcontroller 103 address=0x3B. The bitfields of this register are decoded as follows. This register when read will return the high byte of the last known 16-bit position of the joystick #1

Y coordinate.

FIGURE 37F is a diagram of the bitfields of X2 Position Data Low Byte at microcontroller 103 address=0x3C. The bitfields of this register are decoded as follows. This register when read will return the low byte of the last known 16-bit position of the joystick #2 X coordinate.

FIGURE 37G is a diagram of the bitfields of X2 Position Data High Byte at microcontroller 103 address=0x3D. The bitfields of this register are decoded as follows. This register when read will return the high byte of the last known 16-bit position of the joystick #2

X coordinate.

FIGURE 37H is a diagram of the bitfields of Y2 Position Data Low Byte at microcontroller 103 address=0x3E. The bitfields of this register are decoded as follows. This register when read will return the low byte of the last known 16-bit position of the joystick #2 Y coordinate.

FIGURE 371 is a diagram of the bitfields of Y2 Position Data High Byte at microcontroller 103 address=0x3F. The bitfields of this register are decoded as follows. This register when read will return the high byte of the last known 16-bit position of the joystick #2

107 SUBSTTTUTE SHEET (RULE 25) Y coordinate. Also this register when read will re-enable updates to all X,Y Position Data registers.

FIGURE 38 is an additional timing diagram illustrating the operation of joystick interface 105. A write of signal IOW to Game Port port address 200-205 initiates trigger of signal COMPJ. From that time on, the circuit may be self (auto) triggering in that logical AND of each

X,Y DIS2 signal will continuously trigger the COMPJ blocks 3602 of each joystick when the Auto Retrigger Enable bit is set. In this way the two COMPJ blocks are retriggered simultaneously by the last DIS2 rising edge. This insures that the two counters associated with each joystick always contain valid data that is the result of the previous trigger event. The Auto Retrigger Enable bit is controlled by microcontroller 103. Alternately, microcontroller 103 may initiate a trigger by performing a write to memory address 0x38. The counter is incremented by each XTAL2 rising edge when DIS 1 is high. DIS2 also locks the counter value into latch which may be read by microcontroller 103 8-bits at a time. After the data has been clocked into the latch the counter must be reset. At any point in time microcontroller 103 is able to read the last value of each joystick coordinate. The joystick position data is then transferred to the host via an ISA bus read of Game Port address base +7 after the appropriate command has been written to Game Port address base +7.

The Codec 100 includes a 6-channel Input Mixer and 6-channel Output Mixer. Both the Input and the Output Mixers are fully independent. The Input Mixer provides volume control and mixing capability for combining up to six analog audio sources into the A/D 11 1 converter for sampling. The Output mixer provides volume control and mixing capability for combining up to six analog audio sources into the line outputs. FIGURE 39 is a diagram of one channel of the input mixer (the second channel is identical). FIGURE 40 is a diagram of one channel of the output mixer (the second channel is also identical). The available analog audio sources into the Input and Output Mixer are Line In, Auxl,

Aux2, Digital (DAC) Audio, Microphone, and Line Out.

The Line In, Auxl, Aux2 inputs each have an adjustable input gain stage 3901/4001 that has a gain range of +12dB to -34.5dB. The outputs of these adjustable gain stages feed into the Input and Output Mixer Summers 114 and 115 respectively. The Input and Output Mixer Summers have four different gain settings to allow the user to adjust for optimum signal/noise and overload. The Aux2 inputs have the ability to accept a differential input via a "Ground Differential" reference Pin (VCM- Pin 96) that can be used to eliminate ground loop noise from a CD-ROM input source.

The stereo Microphone input has an adjustable input gain stage 3902/4002 having gain range of +22.5dB to -22.5dB. The Microphone path to the Output mixer has an additional +20dB gain block that may be enabled in Mode 3. The +20dB gain block is set by the LMBST-RMBST bits in Codec Extended registers X2 and X3. To emulate the 20db Microphone gain boost in Mode 2 (LMGE and RMGE bits set to 1), the Mode 3 microphone volume control gain stage is forced to a fixed +1 9.5dB (via LMCG4-LMCG0, RMCG4-RMCG0 =00010). The Microphone inputs can be set into a Differential Mode for enhanced noise rejection and ground loop immunity. This function is available in Mode 3 only. The differential mode is set by the DIFMIC bit in extended register X5. The left channel is connected to the inverting pin of an op-amp, and the right channel to the noninverting pin of the op-amp, with the output sent to the left and right channel inputs of the Input and Output Mixers. The Microphone volume is controlled by the left channel only when in Differential Mode.

When Differential M crophone Mode is selected, the microphone gain level is automatically reduced 6dB.

The analog input mixer functions can now be described in detail in conjunction with FIGURE 39. Mode 1, 2 does not support a true mixer, but requires a mux function that allows only one input at a time to drive the corresponding A/D converter 111. In this mode, the pre-summer gain blocks 3901 are all bypassed (OdB gain) except for the microphone input which may have its gain block set to either OdB (mic boost disabled) or +19.5dB (mic boost enabled). The Input Mixer Summer gain block 3903 is also set fixed to OdB. The post-summer gain block is used to adjust the gain of the currently selected input source over a range of 0 to +22.5dB. Switches 3904 are used to mute all unselected inputs. The DAC output path to the Input Mixer

Summer is also forced muted in this mode. These functions are consistent with Mode 1 , 2 operation.

The input source selection is via the LSSLLSSO and RSSLRSSO bits in registers 10 and II (codec registers, discussed above), respectively. The input source gain (post-summer gain block) is selected by the LAG3:LAG0 and

RAG3:RAG0 bits in registers 10 and II respectively.

109 SUBSTTTUTE SHEET (RULE 26) The +19.5 dB mic gain boost (pre-summer Mic gain block) is selected by the LMGE and RMCE bit in registers 10 and 11 respectively.

In MODE 1, 2 operation, only one input channel at a time is selected by the LSS1-0, RSSl-0 bits. In Mode 3, all of the channels may be selected as inputs simultaneously (see TABLE 59).

The Codec 100 Mixer prevents access (switches are forced open and cannot be closed) to the input mute switches shown in TABLE 59 to implement Mode 1 and Mode 2 mixer functionality.

Microphone The Microphone gain boost is set to 20db, the LMGE and RMGE bits are set to 1, the confrol register map LMCG4 - LMCG0, RMCG4 - RMCG0 are forced to 00010, (19.5dB). The default setting is 01111 (Odb). The mixer switches LMM, RMM are disabled, because MODE 2 operation does not support connecting the Microphone to the output mixer. Line In The mixer switches LLIM, RLIM are disabled. Switches LLM,

RLM and LLMM, RLMM are enabled. Input source gain is only provided to the output mixer and is bypassed to the input mixer. Aux 1 The mixer switches LX1 IM, RXl IM are disabled. Switches

LX1M, RX1M and LX1MM, RX1MM are enabled. Input source gain is only provided to the output mixer and is bypassed to the input mixer. Aux 2 The mixer switches LX2 IM, RX2 IM are disabled. Switches

LX2M, RX2M are enabled. The Aux 2 input is only provided to the output mixer and is disabled to the input mixer. DAC The mixer switches LDIM, RDIM are disabled. Switches LDM,

RDM are enabled. The DAC output is only provided to the output mixer, and is disabled to the input mixer. Mono In The mixer switches MIM and MIMR map to the MIM bit. The

MOM and MOMR both map to the MOM bit. Karoke The mixer switches are mapped to the ADC 1 and ADC0 bits in the Codec 100 Hardware Control Register (base +1) as shown in TABLE 60. Mode 3 operation supports an input mix function. As such individual gain/attenuation (+12dB to -34.6dB) blocks are provided for each analog input source into the mixer except for the LineOut and DAC inputs. The individual analog sources are then mixed in Input Summers 1 14. Input Summers blocks 114 four attenuation settings: OdB, -6dB, -12dB, and -18dB. Input

Summer attenuation is required when mixing multiple analog sources that have near full scale levels. To prevent clipping of the post-summer gain block the resultant analog source mixed signal must be attenuated.

Post-summer gain (OdB to +22.5dB) block 3903 is included to control the gain of the summed analog sources prior to being input to the A/D converter. The flexibility afforded by the various gain blocks results in an architecture that allows for maximum control of signal levels for obtaining the best S/N ratios.

All analog input sources are enabled into Input Summer 1 14. The pre-summer gain blocks 3901 of the input sources affect inputs to the Input Summer and Output Summer equally. In other words when a gain is changed for a particular input source, via the pre-summer gain blocks, the resultant output drives both the Input Summer and Output Summer. The mute function, however, for each analog audio source into the Input Summer and Output Summer is independent.

AUX2 pre-summer gain is set via the LX2G4:LX2G0 and RX2G4:RX2G0 bits in codec registers 14 and 15 respectively.

AUX1 pre-summer gain is set via the LX1G4:LXIG0 and RX1G4:RX1G0 bits in codec registers 12 and 13 respectively.

LINE-IN pre-summer gain is set via the LLG4:LLG0 and RRG4:RRG0 bits in codec registers 118 and 119 respectively. MIC pre-summer gain is set via the LMCG4:LMCG0 and RMCG4:RMCG0 bits in codec registers X2 and X-3 respectively.

Overall Mix Gain/ Attenuation is determined by the Input Summer Attenuation setting

(LIS 1 :LIS0 and RIS 1 :RIS0 bits in codec extended registers X4 and X5 respectively) added to the post-summer gain (LAG3:LAG0 and RAG3:RAG0 bits in codec registers 10 and II respectively). Thus, the gain/attenuation setting for each analog source into the A/D converter is determined by the following equation:

111 SUBSTTTUTE SHEET (RULE 26) Gain (into A/D) = (pre-summer gain) + (input summer attenuation) + (post-summer gain)

The analog output mixer can now be discussed in detail in conjunction with FIGURE 40.

The available analog audio sources into the Output Mixer are Line In, Auxl , Aux2, Digital Audio (DAC), Microphone, and Mono In. AR audio sources are stereo except for the Mono In. The organization of the Output Mixer is as follows: Each analog audio input source has associated with it a +12dB to -34.5dB pre-summer gain/attenuator stage 4001. All the pre-summer gain/attenuation blocks 4001 then feed into a mixer stage 115 (Output Mixer Summer) that includes four selectable attenuation settings of OdB, -6dB, -12dB, and -18dB. The Output Mixer Summer attenuation settings are controlled through Control Registers C27 and C29. These selectable attenuation settings are provided to allow for optimal adjustment for signal/noise and overload. The output of the Summer stage then feeds into a master volume control (C27, C29) with a gain/attenuation range of +12db to -18dB. The output from the master volume control then drives the line outputs. In Modes 1 and 2, the Output Mixer configuration consists of the Output Mixer Summer attenuation being fixed at -12dB. This results in an overall attenuation adjustment range of OdB to -34.5dB for the master volume confrol.

The Microphone input to the Output Mixer is also disabled via switches, LMM and RMM in Mode 1, 2. Mode 1, 2 operation does not support mixing the Microphone input into the output mixer. In addition in Mode 1 operation, the Line-In input is disconnected (muted) into the

Output Mixer Summer.

The Codec 100 further supports a mono input source and mono output, as illustrated in FIGURE 41. The Mono Input is sent to an attenuator block 4101 with a range of OdB to -45dB. The output from the attenuator is sent to the left and right Output Summer blocks 115a/ 115b of the Output Mixer. The Mono input also has a mixer bypass (attenuation 4103 of -9dB) path into the Mono Out when the MBY bit is set in register codec 126 bit D5. On power-on reset the MBY is forced to a 1 to enable the Mono Input to the Mono Output.

Mono Out is a summed output from the Left Line out and Right Line Out. The Left and Right Line Outputs are each attenuated at 4104 by -6dB prior to being summed at 4105 into the Mono Out:

112 SUBSTTTUTE SHEET (RULE 26) Mode 1 In Mode 1, the Mono Input Mute (MIM - 126 bit D7) is forced on to prevent the Mono Input from being fed into the Output Summer. In this mode only the mono bypass path is available; Mode 2 In Mode 2, the Mono Input Mute (MIM - 126 bit D7) and Mono Output Mute (MOM 126 bit D6) bits controls both channels; and

Mode 3 In Mode 3, the Mono Input Mute and Mono Output Mute have independent controls for the left and right channels. The left channel

Mono Input mute is controlled by MIM (126 bit D7) and the right channel

Mono Input mute is controlled by MIMR (X4 bit D7). The left channel Mono Output mute is controlled by MOM (126 bit D6) and the right channel Mono Input mute is controlled by MOMR (X5 bit D7). FIGURE 42 is a diagram of the digital audio processing subsystem of Codec 100. The digital audio functions will be discussed in the following portion. The Codec 100 features a 5 channel (stereo) Digital Mixer that feeds into the DAC. Like the Analog Mixer, the Digital Mixer has Mode 1, Mode 2, Mode 3, and Internal/External FM specific modes of operation.

FIGURE 43 is a diagram of the digital audio mixer. The inputs to the Digital Mixer are

PCM (wave) digital audio, Internal FM, Serial Port, Extemal Wavetable, and A/D Monitor

Loopback. Each input except for the Extemal Wavetable input has an adjustable attenuator 4301 with a range from OdB to -94.5dB. The extemal wavetable attenuator and FM synthesis path attenuators 4302 and 4304 have a range of +12db to 82.5dB.

To maximize signal-to-noise performance, a DAC attenuator is provided that is part digital and part analog. The total attenuation range (OdB to -94.5dB) is split into a digital controlled part 4304 and an analog controlled part 4305. Digital controlled part 4304 operates with an attenuation step size of -6dB over a range of from OdB to -60dB (10 steps). Analog controlled part 4305 operates with an attenuation step size of -1.5dB over a range of from +12dB to -34.5dB (23 steps). FIGURE 44 illustrates the present attenuation scheme and TABLE 61 describes the attenuation stepping/register settings.

In Mode 1 or 2, the Digital Output Mixer supports control of only the PCM (wave) audio codec registers 16, 17 and the A/D Monitor Loopback (codec registers 113). Control of Serial Port or wavetable volume is not available in this mode.

The PCM Audio (wave) volume is controlled by the LDA6-0, RDA6-0 bits in codec registers 16 and 17 respectively. Volume control range is +12dB to -94.5dB in 1.5dB steps.

113 SUBSTTTUTE SHEET (RULE 26) The A/D Monitor Loopback volume is controlled by

bits in codec register 113. Volume control range is OdB to -94.5dB in 1.5dB steps.

In Mode 3, additional codec registers are available for controlling the volume of Serial Port 117 (X8X9). extemal wavetable (XI6,XI7), and the right channel A/D Monitor Loopback (X1O).

The Serial Port 117 volume is controlled by the LSPA5-0, RSPA5-0 bits in codec extended registers X8 and X9 respectively. Volume control range is OdB - -94.5dB in 1.5dB steps.

The extemal wavetable volume is controlled by the LBA5-0, LBA5-0 bits in codec extended registers XI 6 and XI 7 respectively. Volume confrol range is +12dB to -82.5dB in

1.5dB steps.

The A/D Monitor Loopback Left Channel volume is controlled by the LBA5-0 bits in codec extended register 113. Volume control range is OdB to -94.5dB in 1.5dB steps.

The A/D Monitor Loopback Right Channel volume is controlled by the RBA.5-0 bits in codec extended register XI 0. Volume control range is OdB to -94.5dB in 1.5dB steps.

When Internal FM synthesizer 1 16 is enabled some functional changes occur in regard to mixer operation. Normally when using extemal FM, the FM audio is mixed into the Output Analog Mixer via the LLNE_LN input. When using internal FM the FM audio source is now digital which is mixed in via the Digital Mixer. Bits ISO and IS1 in codec extended register X4 are used to control the redirecting of certain host register accesses into specific volume control registers. IS1 controls the redirecting of host accesses for Internal FM and ISO controls the redirecting for the wavetable.

In the Codec 100, the extemal FM analog source is moved to an internal digital source, and the additional support for a digital extemal wavetable synthesizer. The Codec 100 transparently supports control of Internal FM and extemal wavetable volume via existing software and still maintain compatibility with traditional extemal analog sources being input via the LINE N input.

When Internal FM block 116 is disabled the Digital Mixer Operates in a standard Mode

2 configuration. In this mode the DAC attenuator (16, 17) affects all the digital audio sources; A/D Monitor Loopback, Serial Port, wavetable, and PCM(wave). The Extemal FM or MIDI volume is controlled through the LLNE_IN (118, 119) register pair. In this mode independent volume confrol of the Serial Port 117 and extemal wavetable is not possible.

114 SUBSTTTUTE SHEET (RULE 26) When the Internal FM block 116 is enabled, bits ISO and IS in register X4 determine the mapping of registers into specific volume controls. In the default operating mode of ISO, IS 1=01 host accesses to the LLNE_LN registers (118,119) are redirected to the FM volume control registers X6 and X7 in the Digital Mixer. In this mode the DAC attenuator (XI 4, XI 5) affects all the digital audio sources; A/D Monitor Loopback, Serial Port, extemal wavetable, and PCM(wave).

The Extemal FM or MIDI volume is controlled through the LINE_ N (118, 119) register pair. In this mode independent volume confrol of the Serial Port and extemal wavetable is possible.

There are cases when switching between Mode 2 and Mode 3 that wil 1 cause volume level changes or various audio input sources to be enabled that should not be. Examples are described below: a) When Internal FM is enabled the Digital Mixer is configured differently to allow individual control of the 4 digital input sources. In this instance the DAC volume control registers 16, 17 and the Digital Loopback Monitor volume registers XI 4, XI 5 swap. If the settings are different between the 16, 17 and XI 4, XI 5 registers when switching between Mode 2 and Mode 3 changes in volume level will occur; b) In Mode 3 operation the AUX 1 , AUX2, and L NE_IN inputs into the Input Mixer Summer have switches (LX1IM, LX1MM, RX1IM, RX1MM, LLIM, LLMM, RLIM, RLMM) that are independently controllable. These switches are all disabled in Mode 2 and will result in the Mode 3 configuration being lost until Mode 3 is again enabled. When the switch to Mode 2 occurs the input mixer reverts to a mux with the selected input source defined by the current value held in registers 10 and II;

Also Note: In Mode 3 the LX1IM - RX1IM and LX1MM - RX1MM bits (Auxl) or the

LLIM-RLIM and LLMM-RLMM bits (Line) must not be on simultaneously. Having both these switches on simultaneously connects the input and output of the pre-summer gain stage into the input mixer and will cause the signal to cancel itself out due to the fact that the pre-summer gain stage output is inverted relative to the input. c) The Input Mixer Summer attenuator is forced to OdB in Mode 1, 2. If the Input Mixer Summer attenuator is set to an attenuation setting other than OdB, via a Mode 3 change, then switching to Mode 1, 2 will cause the Input Mixer Summer attenuator to be forced back to OdB; d) In Mode 3 operation the Mono Input Mute and Mono Output Mute have independent left/right mute controls. The right channel mute controls are located in Mode 3 accessible registers only. If a Mode 3 application unmutes the right channel Mono Input or Mono Output then a switch to Mode 2 operation will leave the right channel Mono Input or Mono Output unmuted regardless of the state of the Mode 2 MIM or MOM bits; and e) In Mode 3 operation the Monitor Loopback path from A D to D/A has the ability to have independent left/right attenuation controls. The Monitor Loopback attenuation confrol becomes left/right independent when the SLBE bit in register XI 0 is set to 1. If the SLBE is left set to a one when switching to Mode 2 operation, the right channel Monitor Loopback attenuation control will not be affected by the Mode 2 Monitor Loopback attenuation register 113. In Mode 3. the LIS1-LIS0 (codec register X4), and RISl-RISO (codec register X5) bits and the LMS1-LMS0 (codec register C27), and RMSl-RMSO (codec register C29) bits set the amount of attenuation for the Left and Right Input Mixer Summer and Output Mixer Summer.

When more than one analog input source has a large voltage swing, overload may occur at the Mixer Summers. To optimize signal-to-noise performance and prevent overload, the amount of attenuation set in the Mixer Summers should be increased. By controlling the various combinations of Summer and Gain settings, signal overload can be avoided while maximizing the signal-to-noise. The host controlling software can keep track of how many input sources are used, based on which inputs are unmuted, and automatically adjust the Input and Output Mixer Summers accordingly. The concept is that, for every input level control that is unmuted (set above "0") the summer should be adjusted to increase attenuation by -6dB and adjust the post summer Gain block to add +6dB of gain. In this way the overall volume level stays the same, but the ability to prevent overload is increased. It should be noted that increasing mixer headroom, by increasing the Mixer Summer attenuation and increasing the Post Summer gain, will result in poorer signal-to-noise performance. The highest signal-to noise-ratio for PCM capture (when one input is used), is when the Input Mixer Summer bits LIS1-LIS0, and RISl-RISO are set to 00, which is OdB attenuation, and the post-summer gain LAG4-0, RAG4-0 is set to 0000 (OdB) gain. If signal gain is required, the pre-summer input gain block should be used rather than the post-summer gain block. Increasing gain prior the summer, reduces the effect of noise generated by the Input Summer and keeps the signal to ratio the highest throughout the signal path. When more than one input channel is used the Input Mixer Summer should be set to attenuate -6dB for each additional input used. This will prevent clipping at Input Summer 114.

The highest signal-to-noise ratio through the Line Out is obtained when the Output Mixer Summer bits LMS1-LMS0 and RMSl-RMSO are set to 01 (OdB attenuation) and the Post

Summer gain is set to OdB. Note: Mode 2 is defaulted with the Output Mixer Summer set to 12dB attenuation and the Gain is set to +12dB. This was designed so that the Summer would not overload under typical usage. To obtain the best signal-to-noise ratio performance use Mode 3 and set the Output Mixer Summer to OdB attenuation and set the Post Summer Gain to OdB. When making signal-to-noise and distortion measurements the mixer should be set this way to obtain the best performance possible.

Codec 100 includes independent Sample Rate Converters (SRC) 1 12 and 113 on the capture (A/D) and playback (D/A) data paths. In Codec 100 both A/D converters and D/A converters operate at a fixed sample rate of 44.1 kHz. The SRCs 1 12 and 1 13 are then used to convert from 44.1 kHz to the desired sample rate as specified in codec registers 18 (Mode 1), 122

(Mode 2), or X12 and X13 (Mode 3). The SRCs 112 and 113 are digital filters that either decimate(capture) or interpolate(playback) the converter fixed rate data to a user specified alternate rate. This method whereby the converters operate at a fixed sample rate and digital filters are used to sample rate convert the data has distinct advantages in the area of noise management.

In the Codec 100 playback and capture sample rates may be specified by a variety of methods. The SRCs provide a wide range of available sample rates. See TABLE 62 for available sample rates.

In Mode 1 , Codec Register 18 bits CSF2 - CSF0 and C2SL are used to set the capture and playback sample rates. TABLES 63A and 63B show the mapping for the SRC Divider values.

In this mode the sample rate for both capture and playback are identical.

In Mode 2, Codec Register 122 - When the SRE bit is set to 1, bits D3 - DO of codec register 18 are ignored, and the sample rate frequency is determined by CS2, DIV5 - DIVO and

OSM1 - OSM0 in codec register 110. In this mode a much larger range of samples rate are available. In this mode as in Mode 1 the playback and capture rates are identical (TABLE 64).

In Mode 3, Codec Extended register XI 4 - When the SRCE bit is set to 1 the codec extended registers XI 2 and XI 3 are used to set the sample rate, and codec registers 18 or 122 are ignored. Register X12 (SRAD7-0) is used to specify the sample rate for capture (A/D SRC 113), and register XI 3 (SRDA7-0) is used to specify the sample rate for playback (D/A SRC-112). This Mode thus allows independent sample rates for capture and playback. TABLE 65 tabulates the available Mode 3 sample rates. FIGURE 45 is a more detailed diagram of FM synthesis block 1 16 and associated circuitry within codec 100. Internal FM block 1 16 provides full compatibility with market standard FM-based music synthesis as used in DOS games and educational software. The register interface emulates that of the Yamaha OPL2TM, and OPTUM devices, including the OPL3-L and OPL3-LS variations. Provision has been made in the Codec 100 internal FM block 116 to support both two operator and four operator FM compatibility modes. Two-operator mode is the most popular in DOS games. In 2-operator mode, either 18 voices are supported, or 15 voices plus five additional rhythm sounds. In 4-operator mode, either six 4-operator FM voices plus six 2-operator FM voices simultaneously, or six 4-operator FM voices, three 2-operator FM voices plus five rhythm sounds simultaneously.

FM synthesis engine 1 16 generally includes a multiplier 4501, shifter 4502, a pair of adders 4503a and 4503b, registers 4504a-4504b, multiplexers 4505a-4505b, parallel to serial converter 4506, and sample rate converter summer 4507. Also provided is an OPL3 RAM 4509 and associated state machine 4510. Included in an internal PCM waveform ROM table 4508 are 8 FM source waveforms: sine wave; half sine wave; rectified sine wave; rectified quarter sine wave x 2; half-period sine wave; rectified half-period sine wave; square wave; and a decaying square wave. The amplitude of each sine wave over time is controlled using an envelope generator which requires the following parameters to be specified: attack rate - the speed at which a sound rises to its initial volume; decay rate - the rate at which the amplitude drops off to a sustained level; sustain level

- the "normal" intensity of the tone (absolute 0 to 15 volume scale); and release rate - the speed at which the sound level drops from the sustain level to maximum attenuation. Other factors that need be specified include: pitch; volume; depth; feedback; vibrato and the particular synthesis algorithm. Internal FM block 124 has two 2-operator synthesis algorithms to choose from and four

4-operator algorithms. Each of the 4-operator algorithms provision for the output of one waveform generator to feedback into its input. The purpose of this feedback is to distort the base

118 SUBSTTTUTE SHEET (RULE 26) waveform oscillator output to produce a spectra rich in harmonics (used for FM based string sounds and for special effects in games).

The FM synthesis registers are discussed below in conjunction with TABLE 66 (direct registers) and TABLE 66 (indirect registers). FIGURE 46 A is a diagram of the bitfields of Status Register at address base +0, (default

= 0x00000000). The bitfields of this register are decoded as follows:

IRQ Interrupt Request Flag. IRQ is set to one when either FT1 or FT2 is set to one.

IRQ is reset to zero when the RST bit in array 0, address 0x4, is set to one; FTI Timer Flag 1. FTl is set to one when timer 1 has reached its terminal count. FT1 is reset to zero when the RST bit in anay 0, address 0x4, is set to one;

FT2 Timer Flag 2. FT2 is set to one when timer 2 has reached its terminal count. FTl is reset to zero when the RST bit in aπay 0, address 0x4, is set to one; res reserved; and

BUSY The FM Synthesis core requires a wait time between when an address is written to the address register and when data is written to the data register. The BUSY bit when = 1 indicates when the FM interface is "not ready" to receive data.

When the BUSY bit is a zero then the FM interface is ready to receive data.

The Index Registers are accessed by first writing the specific register index to either Base

+ 0 or Base + 1 depending on the register is located in Array 0 or Array 1. Data may then be read from the specified register by performing a read from base + 2 or written to the register by performing a write to either base + 2 or base +3. All registers are cleared when the RESDRV pin is high (TABLE 67).

FIGURE 46B is a diagram of the bitfields of Test at Index 0x0,0x1, (default = 0x00000000). The bitfields of this register are decoded as follows. All bits should be left at "0". FIGURE 46C is a diagram of the bitfields of Timer #1 at Index 0x2, (default =

0x00000000). The bitfields of this register are decoded as follows. Timer #1 has a resolution of 80.8usec. A count of 0-255 can be programmed. When STl is set to a one the contents of Timer #1 register is loaded into counter #1 and counter #1 begins to count down. When counter #1 underflows the IRQ bit is brought low and FTl is set to one. The counter is reloaded and continues to count down where: tl(ms) = Count value (0-255) * 80.8usec

119 SUBSTTTUTE SHEET (RULE 26) FIGURE 46D is a diagram of the bitfields of Timer #2 at Index 0x3, (default = 0x00000000). The bitfields of this register are decoded as follows. Timer #2 has a resolution of 323.1usec. A count of 0-255 can be programmed. When ST2 is set to a one the contents of Timer #1 register is loaded into counter #1 and counter #1 begins to count down. When counter #1 underflows the IRQ bit is brought low and FT2 is set to one. The counter is reloaded and continues to count down where: tl(ms) = Count value (0-255) * 323.1usec

FIGURE 46E is a diagram of the bitfields of Timer #1,#2 Control at Index 0x4, Register Array 0, (default = 0x00000000). The bitfields of this register are decoded as follows: RST When RST is set to a one, the FTl , FT2, and IRQ status bits are reset to zero's.

The IRQ pin is brought to a high level and the RST is reset to zero after FTl, FT2, and IRQ are reset; MT1 When MT1 is set to a one the STl bit and IRQ pin are forced to zero independent of Timer #1 operation; MT2 When MT2 is set to a one the ST2 bit and IRQ pin are forced to zero independent of Timer #1 operation; ST2 When ST2 is set to a one the Timer #2 register is loaded into the Timer #2 counter and starts to count down. When ST2 is a zero then the counter is stopped; and STl When STl is set to a one the Timer #1 register is loaded into the Timer #1 counter and starts to count down. When ST2 is a zero then the counter is stopped. FIGURE 46F is a diagram of the bitfields of 4-Operator Mode at Index 0x4, Register Array 1, (default = 0x00000000). The bitfields of this register are decoded as follows: CSEL5-

CSEL0 When a CSEL bit is set to a one the corresponding channel can be operated in 4-operator mode (TABLE 68). FIGURE 46G is a diagram of the bitfields of Expansion Register at Index W, Register Array 1, (default = 0x00000000). The bitfields of this register are decoded as follows: NEW When this bit is set to a one the expanded registers from OPL2 to OPL3 are enabled, i.e. register array 1 is enabled; and NEW3 When NEW and NEW3 are set to a one the extended OPL3 register bits

120 SUBSTTTUTE SHEET (RULE 26) PS(power save mode), PD(power-down mode), and the BUSY are enabled. FIGURE 46H is a diagram of the bitfields of Keyboard Split at Index 0x8, Register Array 0, (default = 0x00000000). The bitfields of this register are decoded as follows:

NTS Determines keyboard split separation points. When NTS is set to a zero, the separation point is determined by the second bit of the F-number. When NTS is set to a one, the separation point is determined by the MSB bit of the F-number. Rate scaling is performed by splitting 8 octaves into 16 parts. Octave splitting is called "keyboard split". FIGURE 461 is a diagram of the bitfields of Power Management at Index 0x8, Register Array 1, (default = 0x00000000). The bitfields of this register are decoded as follows:

PD Power Down. When the PD and PS bits are set to a one the internal FM block is powered down. All register contents are retained; and PS Power Save. The PS bit is ignored in the Codec 100. This bit is however read-write. FIGURES 46J is a diagram of the bitfields of Tremolo Effect at Index 0x20-35, OxBD,

(default = 0x00000000). The bitfields of this register are decoded as follows:

AM When AM is set to a one, a tremolo effect can be applied to the corresponding slot. The tremolo frequency is 3.7MHz; DM Sets depth where: DAM=1 4.8dB; and

DAM=0 ldB. FIGURES 46K is a diagram of the bitfields of Vibrato Effect at Index 0x20-35, OxBD, (default = 0x00000000). The bitfields of this register are decoded as follows:

VIB When VIB is set to a one, a vibrato effect can be applied to the corresponding slot. The vibrato modulation frequency is 6.0Hz;

DVB Sets depth where:

DVB=1 14%; and DAM=0 7%.

(One percent is a semi-tone divided by 100.) FIGURE 46L is a diagram of the bitfields of Non-percussive Percussive Sound at Index

0x20-35, (default = 0x00000000). The bitfields of this register are decoded as follows: EGT = 0 Percussive Sound; and

121

SUBSTTTUTE SHEET (RULE 26) = 1 Non-percussive Sound. FIGURE 46M is a diagram of the bitfields of Rate Key Scale at Index 0x20-35, (default = 0x00000000). The bitfields of this register are decoded as follows:

KSR Rate key scaling is performed when KSR=1. "Rate Key Scaling" simulates the phenomena that rise time of a sound increases as the frequency of the note increases. FIGURE 46N is a diagram of the bitfields of Frequency Multiplier at Index 0x20-35, (default = 0x00000000). The bitfields of this register are decoded as follows: MULT3- MULT0 MULT specifies the multiplier for the frequency determined by the

BLOCK and F-NUMBER. The actual frequency of each operator is the product of the specified frequency multiplied by the multiplier shown in TABLE 69. FIGURE 460 is a diagram of the bitfields of Total Level at Index 0x40-55, (default = 0x00000000). The bitfields of this register are decoded as follows:

L5-L0 Total Level sets the envelope damping. This can be used to control the modulation rate. The total level is given by the following equation: TL(dB) = (-24 x L5) + (-12 x L4) + (-6 x L3) + (-3xL2) + (-1.5 x Ll) + (-0.75 x L0). FIGURE 46P is a diagram of the bitfields of Level Key Scale at Index 0x:40-55, (default

= 0x00000000). The bitfields of this register are decoded as follows:

KSL1-KSL0 The volume of acoustic instruments normally decrease as the note frequency increases. The level Key Scale is used to simulate this. The KSL1:0 setting determines the attenuation on an octave basis; KSL1 :0 00 OdB^*

01 3dB/octave

10 1.5dB/octave

11 6dB/octave.

FIGURE 46Q is a diagram of the bitfields of Attack Rate at Index 0x60-75, (default = 0x00000000). The bitfields of this register are decoded as follows:

122 SUBSTTTUTE SHEET (RULE 26) AR3-ARO This register determines the attack rate. AR3:AR0 allow fifteen rates with 0 giving the largest rise time and a value of 15 giving the shortest rise time. FIGURE 46R is a diagram of the bitfields of Decay Rate at Index 0x60-75, (default = x00000000). The bitfields of this register are decoded as follows:

DR3 -DR0 This register determines the decay rate. DR3 :DR0 allow fifteen rates with 0 giving the longest decay time and a value of 15 giving the shortest decay time. FIGURE 46S is a diagram of the bitfields of Release Rate at Index 0x80-95, (default = 0x00000000). The bitfields of this register are decoded as follows:

RR3-RRO This register determines the release rate. RR3:RR0 allow fifteen rates with 0 giving the slowest release rate and a value of 15 giving the longest release rate. FIGURE 46T is a diagram of the bitfields of Sustain Level at Index 0x80-95, (default= 0x00000000). The bitfields of this register are decoded as follows:

SLY-SL0 This register determines the sustain rate. When EGT is set to a one, the output level from a slot is held after the attenuation reaches the level set in SL3:SL0. When EGT is set to zero (percussive), the falling rate is switched to the Release Rate from the Decay rate after the attenuation reaches the level specified in SL3:SL0. The sustain level is specified by the following equation:

SL(dB) = (-24 x SL3) + (-12 x SL2) + (-6 x SL1) + (-3 x SL0) (When SL3:SL0 - 15, the sustain level = -93dB). FIGURES 46U is a diagram of the bitfields of F-Number at Index 0xA0-A8, 0xB0-B8, (default = 0x00000000). The bitfields of this register are decoded as follows:

F9-F0 Determines the frequency for one octave. Values from 0 - 1023. FIGURE 46V is a diagram of the bitfields of Block at Index 0xB0-B8, (default = 0x00000000). The bitfields of this register are decoded as follows: B2-B0 Determines octaves. Values from 0 to 7 octaves: F Number is determined by pitch (frequency) and Block as follows:

F-Number = (tone pitch x2¹⁹ / 49.518 kHz

2BLOCK-1

123 SUBSTTTUTE SHEET (RULE 26) FIGURE 46W is a diagram of the bitfields of Key On at Index OxBO, (default = 0x00000000). The bitfields of this register are decoded as follows: KEYON where 0 = Key Off; and

1 = Key On. FIGURE 46X is a diagram of the bitfields of Rhythm at Index OxBD)

Default = 0x00000000). The bitfields of this register are decoded as follows:

RHY When this bit is set to a one, the corresponding slots 13 to 18 are set to rhythm mode. FIGURE 46Y is a diagram of the bitfields of Rhythm Instrument Selection at Index OxBD, (default = 0x00000000). The bitfields of this register are decoded as follows.

This register controls the synthesizing of each rhythm. In rhythm mode, the sound of a rhythm instrument is synthesized when the corresponding bit of the desired instrument is set to one.

The slot number used by each rhythm instrument is shown in TABLE 70. Set the rate, etc. to match the special features of each musical instrument. The available parameters are

F-NUMBER, BLOCK, EGT, MULT, TL, AR, DR, SL, PR, and WS. When a slot is set to the rhythm mode, set KEY ON of slots 13 to 18 to zero.

FIGURE 46Z is a diagram of the bitfields of Algorithm Selection at Index 0xC0-C8, (default = 0x00000000). This registers selects the algorithm. An "algorithm" is a connection scheme defining how a group of operators are combined. A different algorithm can be selected for each channel (register C0-C8H). The bitfields of this register are decoded as follows: 2- operator mode CNT where = 0 algorithm 1 ; and 1 algorithm 2 FIGURE 47 is a diagram representing these two algorithms.

In 4-operator mode, four algorithms type are selectable by setting two CNT bits. FIGURE 48 is a diagram illustrating the algorithms in the 4 operator mode (TABLE 71).

FIGURES 46 AA are diagrams of the bitfields of Feedback Modulation at Index 0xC0-C8, (default = 0x00000000). The bitfields of this register are decoded as follows. FIGURE 46AB is a diagram of the bitfields of Output Channel Selection at Index

0xC0-C8, (default = 0x00000000). The bitfields of this register are decoded as follows: CH0A, CH0B, where 1 = enabled; and 0 = disabled. FIGURE 46AC is a diagram of the bitfields of Register Settings at Index 0xE0-F5 (default 0x0000000). Codec 100 internal FM block 124 has 36 virtual waveform generators used for frequency modulation, created by time division multiplexing a single high-performance DSP core. Each waveform generator is called an "operator" or "slot". One sound generated by combining two or four operators is called a "channel". There are two kinds of registers: one is controlled by every slot unit, another is controlled by every channel unit.

The Register settings in slot units is generally as follows: Registers 20H-35H, 40H-55H, 60H-75H, 80H-95H, and E0H-F5H are controlled by every slot unit. Register addresses x6H, x7H, xEH, and xFH do not exist.

The 36 slots are numbered 1 to 36, which are called "Slot Number". The correspondence between Slot Number and register address is determined as shown in TABLE 72.

In the two-operator mode one FM sound (one channel) is generated using 2 slots. Therefore, 18 channels are generated in two-operator mode. Channels are numbered the same as Slot Number, and are called Channel Numbers.

In case of algorithm 2, any slot of 2 slots can correspond to operator- 1 (operator-2). However, in case of algorithm 1 the timbre depend on which slot is the modulator (which slot is carrier). Vigilance should be taken with regards to Slot Number.

Registers A0H-A8H, B0H-B8H, and C0H-C8H are controlled by every channel unit. The coπespondence between Channel Number and register address is determined as follows. Slot

Number and Channel in Four-operator Mode.

In four-operator mode one FM-type sound (one channel) is generated using 4 slots. 6 channels are generated using 24 slots in four-operator mode. In four operator mode, four algorithms are available as in four-operator mode, the correspondence between slot number and each operator (operator 1, 2,3, or 4^") is determined from TABLE 73.

The Register settings in channel units (Four-operator mode) are as shown in TABLE 74. Registers A0H-A2H, B0H-B2H, and C0H-C2H are controlled by every channel unit. However, the CNT bit of registers C3H-C5H is used as an algorithm parameter (refer to description of CNT bit). Codec 100 internal FM block can generate 5 rhythm instruments (bass drum, snare drum, tomtom, top cymbal, and hi-hat cymbal) using 6 slots. Rhythm slot number are determined to 13-18.

125

SUBSTTTUTE SHEET (RULE 26) 3D Spatial Enhancement is provided by a DSP block 1 18 that is located between the output of the Digital Mixer and the DAC 1 10 for each channel.

FIGURE 49 is a functional block diagram of stereo processor a selected DSP 118.

Because of the DSP block placement, providing 3D Spatial Enhancement to analog input sources requires that the A/D Monitor Loopback path be used. Analog audio sources mixed via the output mixer will not be spatial enhanced.

The SRS function creates a fully immersive three dimensional soundfield through the use of a standard two speaker stereo configuration. To enable the SRS stereo process, the SRS bit in control register C3 is set. Use the "SPACE" and "CENTER" features to adjust the level of SRS signal processing. The SPACE 3 - SPACE 0 bits control the amount of perceived width of the

SRS three dimensional soundfield. The CENTER 3 - CENTER 0 bits confrol the amount of mono sound (common to both left and right) such as a vocalist in music or mono game sound effects.

Sound sources that originate in digital format such as ISA Bus, internal FM Synthesis, and Serial Port data are adjusted and mixed through the Digital Mixer. Sound sources that are analog must be adjusted and mixed through the Analog Mixer and digitized by the A/D converter. This digitized data can then be sent to the Digital Mixer through the Monitor

FeedBack path for SRS processing.

SRS processed digital data can be simultaneously output to the DAC 1 10, and to the Serial Port 1 17 by selecting the SP3D bit in register C3.

The SRS 3D Mono to Stereo processing synthesizes a stereo signal from a mono input source. This processing creates a pleasing three dimensional sound field and eliminates many of the side effects of other stereo synthesis techniques.

Each DSP 118 further supports QSound processing. QSound creates a three dimensional soundfield through the use of a standard two speaker stereo configuration. To enable the QSound stereo process, the 3D Proc on bit in confrol register C3 is set. The "SPACE" and "CENTER" features discussed above to adjust the level of QSound signal processing. Using the SPACE 3 - SPACE 0 bits will control the amount of perceived width of the QSound three dimensional soundfield. Using the CENTER 3 - CENTER 0 bits will control the Digital Audio volume level. Sound sources that originate in digital format such as ISA Bus, internal FM Synthesis, and Serial Port data are adjusted and mixed through the Digital Mixer. Sound sources that are analog must be adjusted and mixed through the Analog Mixer and digitized by the A D

126 SUBSTTTUTE SHEET (RULE 26) converter. This digitized data can then be sent to the Digital Mixer through the Monitor FeedBack path for QSound processing.

QSound processed digital data can be simultaneously output to the DAC 110, and to the Serial Port by selecting the SP3D bit in register C3. 3D Spacial Enhancement registers are located in the Control logical device index space accessed by Confrolbase +3 and Confrolbase +4, discussed above with regards to the Control Registers. As indicated, each of the control registers indexes a set of extended control registers, two of which are as follows:

FIGURE 52A is a diagram of the bitfields of SRS Control Register at Control Index (C2, (default = 00000010). The bitfields of this register are decoded as follows:

SPC (Space) 3-0 SRS processed signal gain termed "SPACE". The least significant bit represents -1.5dB, the attenuation range is from 0 dB to - 22.5 dB, with 0000 = (0 dB or min attenuation). See TABLE 75 A; and

CNT (Center) 3-0 SRS processed signal gain termed "CENTER". The least significant bit represents -1.5 dB, the attenuation range is from 0 dB to - 22.5 dB, with 0000 = (0 dB or min attenuation). See TABLE 75B. When the SRS/MONO bit is set to a one this register is reset to 00100000.

FIGURE 52B is a diagram of the bitfields of 3D Sound Control at Control Index C3, (default = 00000000). The bitfields of this register are decoded as follows:

3DEN When this bit is set to 1, the 3D Audio DSP is enabled and will process any stereo signal from the Digital Mixer. The processed signal is converted by the DAC to "3D" stereo analog 2 channel audio data. The

3D Audio DSP will process either SRS or QSound based on which ROM code is selected,

3DMON When this bit is set to 1 , the SRS Mono to Stereo DSP is enabled instead of the SRS Stereo DSP, and will process any mono or stereo signal from the Digital Mixer. The processed signal is converted by the DAC to

"pseudo" stereo analog 2 channel audio data; 3DSP When this bit is set to 1, the digital data to the Serial Port is from the 3D

Audio DSP. When this bit is set to 0, the digital data to the Serial Port is from the A/D converter; and

127

SUBSTTTUTE SHEET (RULE 26) Res Reserved for future use.

Note: SRS MONO - When the Mono to Stereo function is selected, the "Space" and "Center" bits in register C2 are blocked from writing to, and the registers are set to the default values- "Space" -3 dB or 0010 and "Center" 0 dB or 0000. These principles can generally be described as follows, with a detailed discussion provided below. A master/slave volume control register pair are monitored to detect a volume control change. A change is detected when the contents of the master is different from the contents of the slave. The change detect activates an analog comparitor and a timeout counter. The analog comparitor senses the level of the volume controlled output relative to analog zero. When the analog output swings within the comparitor' s zero window, the comparitor outputs a digital signal that is used to update the slave register contents to match the master register. If there the analog signal does not activate the comparitor in a reasonable time, the timer will generate the update signal. Thus, a closed loop system is provided that continuously monitors it's input for a change, waits for an analog zero-cross (or near zero) or timeout, and then updates the volume control.

In the following discussion the volume control will be described as an attenuator. In practice these volume controls can have gain or attenuation, or both gain and attenuation in the same volume control.

The master and slave registers are elements 5001 and 5002. The change sensor is element 5003. The analog comparitor is element 5004. Elements 5005, 5006 and 5007 are the digitally controlled amplifier pieces. Element 5006 is a pulse stretcher. Element 5007 is the timeout counter. Element 5008 is a logical OR function. The control signal RESET initializes the volume control registers. The SLOW_CLK is a 10 ms clock used for the timeout timer. The DISABLE_ZC input forces the slave register 5002 to be transparent, so that volume control updates occur when the master register changes. The signal WR is the write enable for the master register 5001. DATA carries the digital word that will be stored in the master register.

VCOM is the analog ground reference. And ATN is the analog input, AOUT the analog output.

The functional analysis begins with the RESET signal. When RESET is asserted high, during chip initialization for example, the master and slave registers are forced to the default volume control setting. In the following description it will become evident that it is not necessary to initialize the slave. During RESET active and after RESET deassertion, the Master and SLAVE registers 5001 and 5002 will have identical contents, and the change sensor, 5003, will recognize that condition and output a low level on ZC_ON. The Slave register data will be decoded by 5005. which will activate one of its 32 output signals. The decoder output is used by Attenuator block, 5006, to select one resistor tap. All this results in Opamp, 5007 operating at the default attenuation setting. This is a stable configuration where the ZC_ON signal is inactive, the comparitor is powered off, the ZEROC signal is off, Timer 5010 is disabled, the

TIMEOUT signal is off, the DISABLE_ZC input is off, and the UPDATE signal is off. During normal operation the DISABLE_ZC signal will remain off, the WR signal will be used to load a digital volume confrol word from the DATA bus, and the SLOW_CLK signal will be running with a 10ms period. When a volume control change is desired, the new digital volume control value is placed on the DATA bus (not shown here) and Master latch 5001 is loaded by asserting the WR signal with a short pulse. The output of Master 5001 MASTER now holds the new volume control setting. The MASTER and SLAVE words are no longer identical, and change sensor 5003 recognizes this condition and asserts ZC_ON. Comparitor 5004, is powered up, Timer 5010, is activated. The comparitor senses the relative levels to AOUT and VCOM. If AOUT swings within the detection threshold of VCOM the ZEROC signal is asserted. ZEROC may be a very narrow pulse if AOUT is changing rapidly, and so Pulse Stretcher 5009 stretches ZEROC, and via OR gate 5008 asserts UPDATE. The UPDATE signal is the enable input of Slave Register 5002, which in this instance is implemented as a transparent latch. With the assertion of UPDATE, the SLAVE value will take the value of MASTER. The Change Sensor no longer sees a difference, and deasserts ZC_ON. Then everything returns to the stable state, the Comparitor powers off, ZEROC deasserts, the Pulse Stretcher deasserts UPDATE. If the AOUT signal did not activate Comparitor 5008, due to a DC offset or a very low frequency signal, Timer 5010 would count several ticks of the SLOW CLK, and then active TIMEOUT, which would force UPDATE asserted. When UPDATE asserts, the SLAVE value changes, and the system returns to its stable state. In the present implementation, Timer 5010 counts two SLOW_CLK pulses to assert TIMEOUT.

FIGURE 50B depicts an exemplary embodiment of a window comparator, such as comparator 5004 of the present circuitry. Different implementations will change many of the design features presented in this example. Some desirable tradeoffs are to use edge triggered flops for the Master and Slave registers, use longer timeout delay, use a timeout SLOW_CLK that was activated by the volume control change, or synchronize the UPDATE signal to a system clock or analog sampling clock. A classical problem with using crystal oscillator based clocking circuits is determining when the clock in stable in frequency and duty cycle. Many digital state machines and controller logic can produce undesirable behavior, if operated at the wrong frequency or duty cycle. The common problem is at startup. The oscillator circuit will be slow in starting after power is applied. The crystal will be slow in gaining amplitude. So for some time after power is applied, the oscillator output may be unstable in both frequency and amplitude.

The crystal oscillator clock generator 5100 (FIGURE 51 ) of the present invention has several parts. The oscillator block 5101 contains the crystal oscillator circuit. A super-hystersis buffer monitors the unbuffered oscillator output. A clock detector senses clock inactivity. And there are some other logic gates that synchronize the clock with reset and control the clock output.

The oscillator circuit, 5101, has an enable input and a buffered and non-buffered outputs. The enable input is the on-off confrol, with enable active, the oscillator circuit is powered up and the circuit will try to oscillate. The unbuffered oscillator output drives the super-hystersis buffer input. The super-hystersis buffer is a carefully designed buffer with about two volts of hysteris. This means that the buffer will not detect a low level until the input in one volt below the center level, and will not detect a high level until the input is one volt above the center level. The center level is designed to match the DC bias point of the crystal oscillator circuit, which is roughly one half the supply voltage. Thus, when enable is activated, the super-hysteria buffer output will be steady state until the magnitude of the crystal oscillator exceeds one volt above and below the bias level, then the super-hystersis output will be a square wave version of the unbuffered oscillator signal. The second part is to sense the super-hystersis output for inactivity and synchronously control the buffered oscillator output so that signal presented at the clock generator output is only active when the oscillator is running with a large magnitude.

The clock-off-detect sense inactivity on its input, which is the output of the super- hystersis buffer. If the super-hystersis buffer output does not change logical states within the timeout period of the clock-off-detect block, the olk_is_on signal will go low indicating a dead oscillator. In a powerup sequence the clock-off-detect will initially detect that the oscillator is dead, the flip-flop is initialized by a power-on reset function. The initial condition disables the

130

SUBSTTTUTE SHEET (RULE 26) buffered oscillator signal from reaching the xtal_l 6 output pin. Once the oscillator wakes up and the clock_off_detect asserts Clk_-is_on, the next clock rising edge from the buffered oscillator output will set the Iclkon signal, which enable the xtal_16 output, and the rest of the system now has a good clock. There is other logic outside the clock generator that deals with the situation when the oscillator dies. In general if the oscillator dies, the clk_is_on signal is used to shut down normal operation, and return the system to a state where it is awaiting the clock startup.

The DISABLE-ZC input is usefully for testability, and for turning off the zero cross volume control for applications where instantaneous volume control updates are desired. Father testability improvement can be made by making the Master and Slave independently readable.

DSP serial port interface 117 is enabled by setting the SPE bit in codec register 116.

Once this bit is set the DSP Serial Port pins function as specified by the SFLSFO bits in codec register 1 16 as long as the S/PDIF bit (discussed below) is set to zero. If the S/PDEF bit is set to a one then the DSP serial interface is disabled and S/PDIF data is sent out the SDOUT pin instead.

DSP Serial Interface 117 on codec 100 is available on two different sets of pins. By default codec 100 locates the DSP Serial Interface on the second joystick pins. The switching of the second joystick pins to the DSP Serial Interface is defined by the Serial Port Enable (SPE) bit in register 116 bit D 1. The mapping is: JBBI - FSYNC;

JBCX ~ SDOUT;

JBCY - SDIN; and

JBB2 - SCLK.

The DSP Serial Interface may also be located on the XDBUS. The XD4:XD1 pins (see below) are switched to this function by the SPS bit in control register C8. The mapping is:

XD4 - FSYNC (LRCLK);

XD3 ~ SDOUT;

XD2 ~ SDIN; and

XD1 ~ SCLK. The DSP Serial Interface on codec 100 supports four modes of operation. Serial Port 1 is illustrated in FIGURE 53, Serial Port Mode 2 is illustrated in FIGURE 54, Serial Port Mode 3 is shown in FIGURE 55, and Serial Port Mode 4 is illustrated in FIGURE 56.

131

SUBSTTTUTE SHEET (RULE 26) Serial Port Mode 3 is selected by setting the SF1,0 bits in register codec registers 116 to

11. This format is a 64 bit per frame format that includes ADC as well as DAC 16-bit data. This mode is intended for use by an extemal modem DSP so that the local audio sourced to the DAC may be cancelled from the local microphone signal (ADC). This feature is to allow only non-DAC source audio (voice) to be sent down the phone line.

S PDIF interface 119 is a means for serially transmitting digital audio data through a single connection. It provides two channels for audio data, a confrol channel, and error detection capabilities. The control information is transmitted one bit per sample and is accumulated into a block structure. The data is biphase encoded, which enables the receiver to extract the clock from the data. Coding violations, defined as preambles, are used to identify sample and clock boundaries. The frame/block is shown in FIGURE 57.

Digital data output from the Serial Port (sourced by the ADC or by the Playback Digital Mixer) can be formatted to the Sony Phillips Digital Interface Format (S/PDIF) by setting the S/PDIF bit in register control C4. In addition the SPE bit in codec register 116 must also be set to a one to enable the serial port interface. When the S PDIF format is enabled, the S/PDIF formatting is for only digital output data from the Serial Data Out (SDOUT pin) only and does not support digital S/PDIF format data input (SDIN) into the Serial Port. The encoded data is output on the SDOUT pin. Extemal circuitry is used to interface to either an optical output or to a 75 ohm coax cable interface. The S PDIF output conforms to the SCMS Serial Copy Management System for Digital

Audio Transmission for providing protection of unauthorized digital duplication of copyrighted material.

An S/PDIF block is 192 frames long. Each frame consists of a channel A and channel B sub-frame. FIGURE 58 is a diagram of the typical subframe. Each sub-frame consists of a Preamble (4-bits), auxiliary data (4^*-bits), audio data (20 bits), validity flag (1-bit), user data (1

-bit), channel status data (1-bit), and Parity (1-bit). Codec 100 supports 16-bits of audio data. Codec 100 generates zero's for the auxiliary data and for audio data bits 17 through 20.

The Channel Status Data is 192 bits in length and is transmitted one bit at a time per Frame. A number of user programmable bits are available in the Channel Status Data and are located in the registers described below. Consumer channel status data is summarized in TABLE

75C. The S/PDIF registers are located in the Confrol Logical Device Indexed Register space. Access to these registers is through the Control Registers C3 (Index) and C4 (Data), discussed above.

Codec 100 interfaces to a wavetable synthesizer, such as a Crystal Semiconductor CS4236, with zero glue logic through a block 123. FIGURE 59 is a diagram of the coupling between Codec 100 and a wavetable synthesizer 5901.

The combination operates from one 16.9344MHz crystal or clock source, Codec 100 being the master clock generator for synthesizer 5901.

The serial interface for the wavetable synthesizer requires three pins: MCLK, LRCLK, and DATA. Codec 100 generates the master clock via the MCLK pin for synthesizer 5901.

Codec 100 is able to accept 3v logic levels from extemal wavetable and extemal wavetable is able to accept 5v logic levels from Codec 100. This insures that both devices operate synchronously. Because of timing skews between Codec 100 and extemal wavetable, Codec 100 must synchronize the data sourced from extemal wavetable to its internal clock. Codec 100 detects the edge of LRCLK and performs synchronization so that the digital audio from extemal wavetable is mixed properly with Codec 100 internal audio data before being sent to the DAC. Four pins define pins define the Codec - wavetable synthesizer serial interface. These pins are muxed onto the XDBus by bit WTEN in Control Register C8: DATA as XD7 - input; LRCLK as XD6 - input;

MCLK as XD5 - output; and BRESET.

BRESET The BRESET pin is forced low when RESDRV high, when PM 1 , PM0 are set to 10 in CTRLbase + 0, or when the BRESET is set to \one in confrol register C8.

To minimize the number of serial port timing modes required for the wavetable synthesizer, the serial port timing is defined to match the default internal SCLK mode for a 384fs master clock. The SCLK frequency is 48 x 44.1 kHz. Thus, the least significant 16-bits should be accepted and the rest ignored. FIGURE 60 is a diagram illustrating this timing scheme, where:

Internal SCLK Mode; 16-Bit Data;

133 SUBSTTTUTE SHEET (RULE 26) Data Valid on Rising Edge of SCLK; and INT SCLK = 48Fs if MCLK/LRCK = 384.

Codec 100 supports a variety of test functions to aid in chip debug and production test.

The Primary Test Modes are numbered 0 through 10. Within a number of these Test Modes, namely Test Modes 0, 1, 3, 4 and 6, are a number of secondary test functions that may operate simultaneously with the Primary Test Mode. The available Primary Test Modes are summarized in TABLE 76 and the secondary test modes in TABLE 77.

Codec 100 Primary Test Modes are enabled by forcing the TEST pin high. The rising edge of TEST will strobe the data present on the [TD3.. TDO] pins. The data latched from these pins determines the Test Mode. If TEST is low then codec 100 operates normally. The

Secondary Test Modes available in Test Modes 0, 1, 3, 4 and 6, are selected by writing the secondary test function into register 117. The JAB2 pin is the enable pin for the Secondary Test Modes. It should be noted that even though the Secondary Test functions are available in Primary Test Modes other than 3, the fact that the JAB2 pin is remapped in these other modes means that indeterminate results could occur.

Primary Test Mode 3 has special pin mapping that is dependent on which secondary 117 mode is active. These pin mappings are:

Pin 117 mode Function

JAB2 All High activates the 117 mode C CDDCCSS((9944)) 2 2,, 33 1 bit input stream

CDLNT(92) 2, 3 1 bit input stream

CDRQ(91) 2, 4 1 bit output stream

CDACK(93) 2, 4 1 bit output stream

CDCS(94) All except 2,3 DBEN from RONFPGA - global chip decode CDINT(92) All except 2,3 DBDIR from RONFPGA - global chip direction

To facilitate testing Test Modes 3, 5, 6, 9, and IO all have the Plug-n-Play registers set to a default value. These default values define a set of I/O addresses, Interrupts, and DMA channel mapping per logic device, as shown in TABLE 78.

In this mode all RAM/ROM addresses, data lines, and confrol lines are brought out to Codec 100 pins. This enables access to Codec 100 internal ROM and read/write access to internal program RAM via an extemal device. This Test Mode allows testing of RAM via test

134 SUBSTTTUTE SHEET (RULE 26) pattern sequences as well as loading of the Program RAM with instructions that may be executed by microconfroller 103 during Test Mode 1. The pin remapping is shown in TABLE 79.

In Test Mode 1 , microcontroller 103 ROM addresses are swapped such that location 0000 (boot location) is moved from ROM to RAM. Microcontroller 103 is not held reset in this mode. A port 1 test register is also used. The register may be read or written by microcontroller 103.

The output of the register is also connected to the interrupt input lines of microcontroller 103. In this way microcontroller 103 functions may be tested via downloaded code. Extemal pins of codec 100 allow the address, data, and control signals of microconfroller 103 to be monitored externally. The pin remapping is summarized in TABLE 80. A typical Test Mode sequence is: 1) RESDRV=l or RESDRV=0;

2) TEST=1 , set XD3-XD0 to 0000 to select Test Mode 0. TEST=0;

3) Using Test Mode 0 load internal Program RAM with diagnostic code;

4) TEST=1, set XD3-XD0 to 0001 to select Test Mode 1. microcontroller 103 is reset; 5) TEST=0, microcontroller 103 now boots from RAM; and

6) Monitor extemal pins.

In Test Mode 2 all microcontroller 103 addresses, data, and confrol signals are monitored externally via codec 100 pins. The chip operation proceeds normally, with microcontroller 103 executing from its program ROM/RAM and the codec operating normally. The purpose of this Test Mode is to allow the operation of the internal microcontroller 103 to be monitored externally as it is operating in a system environment.

In order to monitor the codec registers, a means to identify SFR accesses to the codec registers is required. Thus the XD[7:0] bus definition is changed when codec 100 is operating in this Test Mode. The XDB[7:0] bus is defined to normally follow the state of Microcontroller 103 XDB[7:0] bus, but when a SFR access occurs, (indicated by SFRADL) the state of the

SFRDB[7:0] and SFRAB[7:0] buses are output onto the XD[7:0] pins in a multiplexed manner. To indicate when the XD[7:0] bus is outputting SFR address/data the XALXAO pins are both driven low simultaneously. The XALXAO pins should remain low during the SFR cycle. This Test Mode 3 pin remapping is summarized in TABLE 81. In the Codec (Sound System) codec register 117, Test Mode codec is isolated from the rest of codec 100 chip. This Test Mode will force the ISA interface logic to be enabled in a default Sound System mode. The base address, DMA and interrupt mapping is determined by

135

SUBSTTTUTE SHEET (RULE 26) power on default values. The Plug & Play interface logic is disabled in this mode. In this mode codec 100 operates as a WSS codec. All existing WSS based diagnostics and test vectors should operate normally. This mode is controlled by codec register 117, as summarized in TABLE 82. Each of Register 117 Secondary Test Modes can be described as follows: 117 Mode 0 Normal codec operation;

117 Mode 1 Disable Zero Cross (disable_zc). The volume control zero cross logic is bypassed. Volume control register writes update the slave register with the master register;

117 Mode 2 Codec digital 1 bit test (codig_test). The decimator inputs are re-synchronized to the XTAL clock. The DAC modulator still drives the

DAC analog. The following data paths are created:

DAC modulator left output --> CDRQ pin; DAC modulator right output~> CDACK pin; CDCS pin — > left ADC decimator input; and CDINT pin --> right ADC decimator input;

117 Mode 3 DAC analog test (dacana_test). The inputs are internally synchronized to the analog 128xFs clock. How you synchronize them externally is a neat trick. The following data paths are created:

CDCS pin --> left DAC S/C filter; and CDLNT pin --> right DAC S/C filter;

117 Mode 4 ADC analog test (adcana__test). The following data paths are created:

ADC modulator left output— >CDRQ pin; and ADC modulator right output~>CDACK pin; 117 Mode 5 Codec calibration test (test_cal). This mode suppresses the normal reset of the capture FIFO, allowing the capture path to function normally. The capture data represents the offset measured by the ADC as the codec is calibrating. The calibration measures the ADC's own offset first, then uses the ADC to measure the DAC offset. Thus the capture record will show the ADC settling to its own offset, then a transient, then the DAC offset;

117 Mode 6 Digital one bit loopback (test_dac2adc). The DAC 1 bit stream is looped back into the ADC decimator to form a digital loopback test;

136

SUBSTTTUTE SHEET (RULE 26) 117 Mode 7 Disable codec calibration (disable_cal). Do not calibrate the codec on chip reset or recovery from full powerdown; 117 Mode 8 Zero Cross Detector Test (zcd_test). Disable the volume control timeout timer so that volume control updates only occur on zero cross; 117 Mode 9 Digital loopback (testsrc). The playback data at the DAC interpolator input is routed to the ADC data formatter instead of the normal ADC data. This forms a digital loopback from playback to capture/serial ports;

117 Mode 10 Test FM ROM. The FM synthesizer's (ROM) is tested by adding all the bits in the ROM to create a check sum. This check sum is then sent to the digital mixer. In order to read the check sum directly the testsrc test is enabled; 117 Mode 1 1 Timer test (test_slw_cntr). The volume control time out counters will count 256fs clock periods instead of fs clock periods. 117 Mode 12, 13,14 Not used;

117 Test Mode 15

(test_opamp) The output of each op amp in the mixer is muxed to the MONO OUT pin.

An op amp's output becomes observable on the MONO OUT pin by writing to the least significant bit of its volume control register. FIGURE

61 is a test bit chart describing this mode.

In Test Mode 4 (replace internal microcontroller Test Mode) all signals from the "FPGA" logic and codec, which were connected to the internal microcontroller 103, are routed to codec

100 pins. FIGURE 62 describes the microcontroller memory map in Test Mode. Since SFR accesses are not visible outside of a standard microcontroller 103 microcontroller, some method of translating internal SFR accesses to accesses that are visible extemal to microcontroller 103 must be found. To accomplish this it is assumed that a special version of microconfroller 103 ROM code will be developed that will replace all codec internal

SFR accesses with externally visible MOVX instructions. Also there is a one-to-one conespondence between SFR addresses and the address that is generated during the corresponding MOVX cycle. The end result of this code change is that codec accesses into the

SFR address space are translated into accesses into the extemal RAM space. Once this has been accomplished the extemal microcontroller 103 read, write, address, and data signals are provided as inputs to codec 100 and are decoded to generate accesses to codec 100 codec registers.

In codec 100 the external microconfroller 103 multiplexed data/address bus XD[7:0] and a latched version of the address (XDBAL[5:0]) are input to codec 100 via extemal pins. Because the decoding of translated SFR addresses requires decoding 8-bits and the fact that not all address signals are input to codec 100, an internal 8-bit latch must be added to latch the address off of microcontroller 103 multiplexed address/data bus. This latch uses the ALE signal from the extemal microconfroller 103 to latch the data during the address phase of the multiplexed XD[7:0] bus. The XDBAL[5:0] pins are now free for other uses. The ALE signal is input via the JBB2 pin.

The Test Mode 4 Pin Remapping is summarized in TABLE 83.

Test Mode 5 allows test of the "FPGA" logic and interfaces. The ISA interface is forced to Sound System mode with the base address and DMA/Interrupt mappings at power on default settings. The codec operates in this mode, but microcontroller 103 is held reset. No remapping of pins is required in this mode.

Test Mode 6 (replace microconfroller Test Mode) tests the ISA Bus to microcontroller 103 interface logic. This mode is identical to Test Mode 4 except that the interface is forced to Sound System default settings. The codec operates normally in this mode and the internal microcontroller 103 is held reset. TABLE 84 summarized the pin remapping in this mode. Test Mode 7 is the Outputs High Test Mode. When this Test Mode is selected all digital outputs will be forced high.

Test Mode 8 is the Outputs Low Test Mode. When this Test Mode is selected all digital outputs will be forced low.

Test Mode 9 is the Digital Joystick Test Mode A. This is the same as Test Mode 5 except forces digital joystick 16-bit counters to operate as two 8-bit counters in parallel. In this way test time can be miriimized by having the upper and lower halves of the 16-bit counter increment at the same time. Thus testing the counter requires 255 clocks instead of 65536. Also joystick microcontroller 103 registers at addresses 0x38 to 0x3F are mapped into Control Register space at addresses C38 to C3F. Test Mode 10 is the Digital Joystick Test Mode B, which is the same as Test Mode 9 except digital joystick 16-bit counters operate as one 16-bit counter. FIGURE 63 is a diagram of the pinout of Codec 100.

138

SUBSTTTUTE SHEET (RULE 26) The pins can be described generally as follows. ISA Bus Interface Pins:

SA<11 :0> Address, Input

These signals are decoded during I/O cycles to determine access to the various functional blocks within codec 100 as defined by the configuration data written during a Plug And Play configuration sequence.

SA<15:12> - Address, Input

These additional address lines are decoded along with SA<11 :0> when the 16-bit decoding mode of codec 100 is selected.

SD<7:0> - Data Bus, Bi-directional, 24ma drive These signals are used to transfer data to and from codec 100 and associated peripheral devices.

AEN - Address Enable, Input

This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal is low during an I/O cycle and high during a DMA cycle .IOR/ - Read Command Strobe, Input

This signal defines a read cycle to codec 100. The cycle may be a register read or a read from codec 100 DMA registers. This signal is active low.

IOW/ - Write Command Strobe, Input

This signal indicates a write cycle to codec 100. The cycle may be a write to a control register or codec 100 DMA register. This signal is active low.

IOCHRDY - I/O Channel Ready, Open Collector Output, 8ma drive

This signal is driven low by codec 100 during ISA bus cycles in which codec 100 is not able to respond within a ininimum cycle time. IOCHRDY is forced low to extend the current bus cycle. The bus cycle is extended until IOCHRDY is brought high.

DRQ<A:C> - DMA Requests, Output, 24ma drive

These active high outputs are generated when codec 100 is requesting a DMA transfer. This signal remains high until all the bytes have been transferred as defined by the current transfer data type. The DRQ<A:C> outputs must be connected to 8-bit DMA channel request signals only. These are DRQ0, DRQ 1 , and DRQ3 on the ISA bus.

DACK/<A:C> - DMA Acknowledge, Input

139 SUBSTTTUTE SHEET (RULE 26) The assertion of these active low signals indicate that the current DMA request is being acknowledged and codec 100 will respond by either latching the data present on the data bus (write) or putting data on the bus(read). The DAK<2:0> inputs must be connected to 8-bit DMA channel acknowledge lines only. These are DACK0, DACK1, and DACK3 on the ISA bus.IRQ <A:F>- Host Interrupt

Pins, Output, 24ma drive

These signals are used to notify the host of events which need servicing. They are connected to specific interrupt lines on the ISA bus. The IRQ<A:F> are individually enabled as per configuration data that is generated during a Plug and Play configuration sequence.

Analog Inputs:

LLINE - Left Line Input

Nominally 1 VRMS max analog input for the Left LINE channel, centered around VREF. The LINE inputs may be selected for A/D conversion via the input multiplexer (10). A programmable gain block (118) also allows routing to the mixer. RLINE - Right Line Input

Nominally 1 VRMS max analog input for the Right LINE channel, centered around VREF. The LINE inputs may be selected for A/D conversion via the input multiplexer (II). A programmable gain block (119) also allows routing to the mixer. LMIC - Left Mic Input

Microphone input for the Left MIC channel, centered around VREF. This signal can be either 1 VRMS (LMGE = 0) or 0.1 VRMS (LMGE = l).The MIC inputs may be selected for A/D conversion via the input multiplexer (10)

.RMIC - Right Mic Input

Microphone input for the Right MIC channel, centered around VREF. This signal can be either 1 VRMS (RMGE = 0) or 0. 1 VRMS (RMGE = 1). The MIC inputs may be selected for A D conversion via the input multiplexer (II). LAUX1 - Left Auxiliary #1 Input

Nominally 1 VRMS max analog input for the Left AUXl channel, centered around VREF. The AUXl input may be selected for A/D conversion via the input multiplexer (10). A programmable gain block (12) also allows routing to the output mixer. RAUX1 - Right Auxiliary #1 Input

Nominally 1 VRMS max analog input for the Right AUXl channel, centered around VREF. The ALJX1 input may be selected for A/D conversion via the input multiplexer (II). A programmable gain block (13) also allows routing to the output mixer. LAUX2 - Left Auxiliary #2 Input

Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A programmable gain block (14) also allows routing of the AUX2 channels into the output mixer. RAUX1 - Right Auxiliary #1 Input

Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A programmable gain block (15) also allows routing of the AUX2 channels into the output mixer.

MIN - Mono Input

Nominally 1 VRMS max analog input, centered around VREF, that goes through a programmable gain stage (126) into both channels of the mixer. This is a general purpose mono analog input that is normally used to mix the typical "beeper" signal on most computers into the audio system.

Analog Outputs:

LOUT Left Line Level Output

Analog output from the mixer for the left channel. Nominally 1 VRMS max centered around VREF when OLB = 1 (116). When OLB = 0, the output is attenuated 3 dB and is a maximum of 0.707 VRMS.

ROUT - Right Line Level Output

Analog output from the mixer for the Right channel. Nominally 1 VRMS max centered around VREF when OLB = 1 (116). When OLB - 0, the output is attenuated 3 dB and is a maximum of 0.707 VRMS. MOUT - Mono Output When OL13=l (116),

MOUT is nominally 1 VRMS max analog output, centered around VREF. When OLB=0, the maximum output voltage is 3 dB lower, 0.707 VRMS. This output

141

SUBSTTTUTE SHEET (RULE 26) is a summed analog output from both the left and right output channels of the mixer. MOUT typically is connected to a speaker driver that drives the internal speaker in most computers. Independently mutable via MOM in 126. MIDI Interface: MIDOUT - Transmit Data, Output

This output is used to send MIDI data serially out to a extemal NMI device. MIDIN - Receive Data, Input

This input is used to receive serial MIDI data from an extemal MIDI device. Synthesizer Interface: SCS/UP - Synthesizer Chip Select, Output

This active low output is forced low when a valid address decode to the synthesizer, as defined in the Plug and Play configuration registers, has occurred. This pin also become the UP input for the extemal master volume control. XCTL1/SINT/DOWN/ACDCS Synthesizer Interrupt, Input /XCTLl, Output This active low input is driven by the synthesizer interrupt output pin or outputs

XCTLl depending on state of XIOW when RESDRV goes low. This pin also outputs the alternate CDROM chip select when the alternate CDROM base address register has been programmed to a non-zero value. When using this pin as ACDCS the XIOW pin should be tied through a 10k resistor to ground and this pin should be pulled up via a 10k resistor. This insures that ACDCS remains high until the alternate CDROM base address register has been programmed. This pin also become the DOWN input for the extemal master volume confrol. Extemal Peripheral Port:

XD<7:0> - Extemal Data, Bi-directional These pins are used to transfer data between the ISA bus and extemal devices such as the synthesizer and CDROM. XD[0] is also used in conjunction with SCL to access an extemal I C compatible serial E²PROM. The XD[0] is an open collector type output. A pull-up is required extemal to codec 100 on the XD[0] pin. The XD[0] pin should be also be connected to the data pin of the E²PROM device. The E²PROM is used to store the Plug and Play 72 bit serial identifier.

The XD pins also may be switched to support the extemal wavetable serial interface and DSP serial interface:

142 SUBSTTTUTE SHEET (RULE 26) XD7/DATA - Extemal Data Bit 7. or wavetable synthesizer serial interface Data pin; XD6/LRCLK - Extemal Data Bit 6, or wavetable synthesizer serial interface LRCLK pin; XD5/MCLK - Extemal Data Bit 5, or wavetable synthesizer serial interface MCLK pin; XD4/FSYNC - Extemal Data Bit 4, or DSP serial interface FSYNC pin; XD3/SDOUT - Extemal Data Bit 3, or wavetable synthesizer serial interface SDOUT pin;

XD2/SDIN - Extemal Data Bit 2, or DSP serial interface SDIN pin; XD1/SCLK - Extemal Data Bit 1, or DSP serial interface SCLK pin; XA2/XCTL0 - Extemal Address, Output XCTLO, Output: This pin either outputs ISA bus address A2 or XCTLO depending on the current

Plug & Play resource data; XA1 - Extemal Address, Output:

This pin outputs ISA bus address Al; XAO/SCL - Extemal Address, Output: This pin is used to output ISA bus address A0 or the clock for the extemal

EEPROM. BRESET/ - Extemal Reset, Output:

This active low signal is generated whenever the RESDRV pin goes high; XIOR - Extemal Read Strobe, Output - CDROM Enable, Input (Internal 100K pull-up): This active low signal is generated on a ISA bus read of an extemal peripheral device. This pin is sampled on the high to low transition of RESDRV. If this pin is sampled low then the CDROM interface operates normally. If this pin is sampled high then the CDROM interface pins operate as inputs for ISA bus address bits A12, A13, A14, and A15; and XIOW/ - Extemal Write Strobe, Output - SINT Enable, Input (Internal 100K pull-up):

This active low signal is generated on a ISA bus write of an extemal peripheral device. This pin is sampled on the high to low transition of RESDRV. If this pin is sampled low then the SINT pin functions as an input for the synthesizer interrupt. If this pin is sampled high then the SINT pin becomes an output for XCTLO.

Joystick/Serial Port Interface:

JACX, JACY, JAB1, JAB2, JBCX, JBCY, JBB1, JBB2 - Joystick Data, Input:

143 SUBSTTTUTE SHEET (RULE 26) These pins are used to connect directly to the game port connector. Optionally the #2 joystick pins may be programmed as a serial data interface. JACX, JACY - Joystick A coordinates, Input:

These pins should connect directly to the game port connector and are the X/Y coordinates for Joystick A;

JAB1, JAB2 - Joystick A Buttons, Input:

These pins should connect directly to the game port connector and are the switch inputs for Joystick A; JBCX/SDOUT - Joystick B Coordinate X, Input/Serial Data Output, Output: When this pin is used for a second joystick, it should connect directly to the X coordinate for Joystick B of the game port connector. When the serial port is enabled, via SPE=1 in 116, this pin is used to output the serial data. JBCY/SDIN - Joystick B Coordinate Y, Input/Serial Data Input, Input;

When this pin is used for a second joystick, it should connect directly to the Y coordinate for Joystick B of the game port connector. When the serial port is enabled, via SPE=1 in 116, this pin is used to input the serial data. JBB1/FSYNC - Joystick B Buttonl, Input/Frame Sync, Output:

When this pin is used for a second joystick, it should connect directly to the switch #1 input for Joystick B of the game port cormector. When the serial port is enabled, via SPE=1 in 116, this pin outputs the serial frame sync;

JBB2/SCLK - Joystick B Button2, Input/Serial Clock, Output:

When this pin is used for a second joystick, it should connect directly to the switch #2 input for Joystick B of the game port connector. When the serial port is enabled, via SPE=1 in 116, this pin outputs the serial clock; The dual functioning of the joystick interface pins is described in TABLE 85.

CDROM Interface:

CDCS/SA12 - CDROM Chip Select (Output)- SA12 Address (Input):

The function of this pin is determined by the state of the XIOR pin on the falling edge of RESDRV. If XIOR is sampled low then this pin functions as CDCS which is driven low whenever codec 100 decodes an address that matches the value programmed into the CDROM base address register. If XIOR is sampled high then this pin becomes an input for SA12; CDACK SA13/MCS - CDROM DMA Acknowledge (Output) - SA13 Address (Input)- Modem Chip Select (Input):

The function of this pin is determined by the state of the XIOR pin on the falling edge of RESDRV. If XIOR is sampled low then this pin functions as CDACK which is driven low whenever the ISA bus generates a low on the appropriate

DACK line. If XIOR is sampled high then this pin becomes an input for SA13. If the Modem base address register is programmed to a non-zero value then the CDACK, function is switched over to the MCS function. In this case whenever codec 100 decodes an address that matches the value programmed into the Modem base address register MCS is driven low. Once this pin has been switched over to function as MCS it locked into this function until a RESDRV occurs; CDLNT/SA14 - CDROM Interrupt (Input) - SAM Address (Input);

The function of this pin is determined by the state of the XIOR pin on the falling edge of RESDRV. If XIOR is sampled low then this pin functions as CDINT which is used as an input for the CDROM interface interrupt line. If XIOR is sampled high then this pin becomes an input for SAM; CDRQ/SA15 - CDROM DMA Request (Input) - SA15 Address (Input):

The function of this pin is determined by the state of the XIOR pin on the falling edge of RESDRV. If XIOR is sampled low then this pin functions as CDRQ which is used as an input for the CDROM interface DMA request line. If XIOR is sampled high then this pin becomes an input for SA15; Miscellaneous:

XTAL II - Crystal #1 Input: This pin will accept either a crystal with the other pin attached to XTAL 10 or an extemal CMOS clock. XTAL 1 must have a crystal or clock source attached for proper operation. The standard crystal frequency is 24.576 MHz although other frequencies can be used. The crystal should be designed for fundamental mode, parallel resonance operation; XTAL 10 - Crystal # 1 Output:

This pin is used for a crystal placed between this pin and XTAL II; XTAL2I - Crystal #2 Input:

145

SUBSTTTUTE SHEET (RULE 26) If a second crystal is used, is should be placed between this pin and XTAL2O.

The standard crystal frequency is 16.9344 MHz although other frequencies can be used. The crystal should be designed for fundamental mode, parallel resonance operation; XTAL2O - Crystal #2 Output:

This pin is used for a crystal placed between this pin and XTAL2I; RESDRV - Reset Drive, Input:

When this input is high codec 100 is held reset and placed in the lowest power consumption mode. All sections of codec 100, except the digital bus interface which reads 80h, are shut down and consume minimal power. This pin is typically connected to the RESDRV pin of the ISA Bus; VREF - Voltage Reference, Output:

All analog inputs and outputs are centered around VREF which is nominally 2.1

Volts. This pin may be used to level shift extemal circuitry, although any AC loads should be buffered. High internal-gain microphone inputs can be slightly improved by placing a lOuF capacitor on VREF; REFFILT - Voltage Reference Internal, Input:

Voltage reference used internal to codec 100 must have a 0.1 uF and a 10 uF capacitor with short fat traces to attach to this pin. No other connections should be made to this pin;

LFILT - Left Channel Antialias Filter Input:

This pin needs 1 OOOpF NPO capacitor attached and tied to analog ground; RFILT - Right Channel Antialias Filter Input:

This pin needs 1 OOOpF NPO capacitor attached and tied to analog ground; TEST - Test:

This pin must be tied to ground for proper operation; Power Supplies:

VA - Analog Supply Voltage; and

Supply to the analog section of the codec; AGND - Analog Ground:

Ground reference to the analog section of the codec. Internally, these pins are connected to the substrate as are DGND3/4/5; therefore, optimum layout is

146

SUBSTTTUTE SHEET (RULE 26) achieved with the AGND pins on the same ground plane as DGND3/4/5 (see Figure 17). However, other ground arrangements should yield adequate results. VD1, VD2 Digital Supply Voltage:

Digital supply for the parallel data bus section of the codec. These pins should be connected to the digital power plane section of the board;

VD3, VD4, VD5 -Digital Supply Voltage:

Digital supply for the internal digital section of the codec (except for the parallel data bus); DGND1, DGND2- Digital Ground: Digital ground reference for the parallel data bus section of the codec. These pins are isolated from the other digital grounds and should be connected to the digital ground section of the board: SGND1, SGND2, SGND3 - Substrate Ground:

Substrate ground reference for the internal digital section of the codec (except the parallel data bus). These pins are connected to the substrate of the die as is the

AGND pin. Optimum layout is achieved by placing SGND 3 on the analog ground plane with the AGND pin;

To support 3.3 Volt ISA Bus operation codec 100 connects all ISA Bus output pins (Data

Bus, DMA Requests, and Interrupts) to a isolated digital supply (VD1 and VD2). To support 3.3 Volt ISA Bus operation the VD1 and VD2 supplies are connected to the 3.3v power supply and the VDF1-VDF3 and VAA pins are connected to the 5Volt supply. This mode of operation assumes that the logic levels for the 3.3V ISA bus match that of standard TTL. Codec 100 ISA

Bus inputs are not 5v tolerant when operating with 3.3V supplies. Thus when operating in 3.3V mode the ISA bus signals must be at 3.3V logic levels. The Aux 2 inputs have a "Ground Differential" reference pin (VCM - Pin 96) that can be used to eliminate ground loop noise from the CD-ROM in a PC environment. Power supply noise is introduced onto the CD-ROM audio signal by the current that is drawn by from the CD-ROM.

The voltage on the ground pin of the CD-ROM audio cable is not at the same voltage potential as the other analog inputs to the Codec. This can result in CD-ROM disc drive "seeks" that can be easily heard in the background while playing music. Using a "Ground Differential" pin will reduce ground loop noise by up to 4φdB. Typical measured noise reduction is about -26dB and is completely effective in eliminating the noise. The only component and circuitry changes that

147 SUBSTTTUTE SHEET (RULE 26) are needed are the addition of a "ground" coupling cap. Instead of connecting the CD-ROM audio cable ground to analog ground, connect a luF ceramic cap from the CD-ROM audio cable ground to pin 96 (VCM) of Codec 100. The cable that connects from the CD-ROM can be shielded or unshielded. The microphone input, shown in FIGURE 64A, can be set into a Differential mode for enhanced noise rejection and ground loop immunity. The left channel is connected to the inverting pin of the input op-amp, and the right channel to the non-inverting pin of the input op-amp. The output of the op-amp is sent to the left and right channel inputs of the Input and Output Mixer. Gain is adjusted by the left channel in extended register X2 - LMCG4-0, the 20dB boost is applied on each channel separately.

The circuit, shown in FIGURE 64A, is a suggested implementation that may be used for both condenser and dynamic Microphones. The circuit supplies a switched DC bias that ramps slowly to help prevent pops when plugging in the Microphone.

FIGURE 65 is a circuits implementation that may be used to drive Line Out and Headphones. The circuit has a gain of 1, as the Codec has an output impedance of 600 - 900 ohms. The circuit is "Pop - Free" when a 2.2 uf cap is used for VREF (pin 78) and a 10 uf cap is used for REFFLT (pin 79). Using a 2.2uf cap for VREF instead of a lOuF cap allows the VREF voltage to charge up smoothly, when a lOuF cap is used the "quick charge" circuit is activated, causing a glitch in the voltage ramp-up. Note: also that the impedance seen by the Line out pins of the CS4236/7/8 must see a high DC impedance during reset or power up. The Line out pins are connected to VREF during reset by "weak" drivers and will not support low impedance loads. This will cause sagging of the signal during VREF ramp-up and glitch once VREF is complete. The circuit shown below prevents this by presenting a high DC impedance by buffering the input impedance of the op-amp by having the non-inverting input connected to VREF.

In an alternate embodiment of the present invention, codec 100 is provided in a streamlined version in which a number of features discussed above have been eliminated and new features have been added. This alternate embodiment has the substantial advantage of being less expensive while providing the essential functions in high-quality manner. Specifically, the following features that have been eliminated.

1. u-Law/A-Law;

2. ADPCM; 3. Digital Joystick Assist;

4. Extemal Peripheral Port;

5. Extemal Modem Interface Support;

6. Stereo Mic changed to Mono; 7. Stereo AUX - In;

8. SRS/QSound Stereo enhancement changed to Crystal method;

9. Mono Out; and

10. Digital Mixer. The added features are as follows: 1. Internal PnP ROM;

2. 90dB DAC;

3. Crystal Stereo enhancement;

4. Internal Pullup Resistors on Joystick buttons;

5. Seventh IRQ pin; 6. Backdoor Non-PnP Configuration;

7. Hardware configuration of PnP/Configuration port address;

8. ZVPORT; and

9. 250mw power.

In the alternate embodiment, several of the mixer functions have been modified or eliminated. The eliminated mixer functions include:

LLNE_IN (external FM/Wavetable) Stereo Analog Input;

ADC Digital Loopback - ability to monitor ADC is gone;

Independent Serial Port Volume Control - Volume confrol now shared between FM, extemal wavetable, and Clyde Serial Interface; One MIC input channel and associated gain blocks;

Gain Confrol Into ADC;

Mono Out;

Digital Mixer; and

Gain Removed from output Master Volume Control. In the alternate embodiments, a number of changes are made to the mixers. FIGURE 66 is a diagram of an alternate mixer section 6400. In general, any of the following changes may be made either alone or in combination.

149

SUBSTTTUTE SHEET (RULE 26) The mixer may operate as Mode 3 only. What this means is that switching to Mode 2 or Mode 1 operation will have no effect on mixer operation. The input sources into ADCs 111 are always controlled via a mix function and not a multiplexer function. Register accesses still have some Mode dependencies. These include Mode 2 and Mode 3 specific registers. Mode 2 registers may be accessed in Mode 2 or Mode 3 only and Mode 3 registers (i.e. Extended

Registers) are accessible in Mode 3 only.

The Digital Mixer may be eliminated such that no digital audio sources are mixed digitally. The possible digital audio sources are Intemal FM, extemal Wavetable, accelerator Digital, and ZV Port Digital Data. Instead, two DACs per channel are provided along with a number of multiplexers that control the flow of digital audio data into the DACs and then to the analog output mixer.

The two DACs are not identical. DAC1 110 is the standard, 16-bit high performance, 1-bit delta sigma converter. DAC1 is used for converting .WAV streams transferred via ISA Bus interface 101 or from digital serial interface 117. The other, DAC2 6401, is a 12-bit R-2R parallel converter. DAC2 is primarily provided for conversion of digital audio from devices where lower performance audio is acceptable, such as from FM and Wavetable/ZV Port devices. It should be noted that the audio performance of DAC2 is limited by bit accuracy (12 bits) and distortion not signal-to-noise. The signal-to-noise performance (data at zero) is on par with that of DAC1. Since the human hearing mechanism is much more sensitive to noise than to distortion this trade off acceptable for a low cost alternate. In addition all audio performance testing uses

DAC1 110.

A programmable volume confrol and mute function is provided for each DAC 110/6402. This results in the sharing of volume confrol between digital audio devices. Intemal FM and Wavetable (extemal wavetable)/ZV Port are summed together and thus share a common volume confrol. Alternate embodiments ^"of codec 100 include a sealer that can adjust the FM volume relative to Wavetable volume. The ISA Bus generated .WAV (wave) stream may only be controlled by the DAC1 volume control. Because a digital data stream may be directed to either DAC 110/6402, its volume may be controlled by either the DAC1 or DAC2 specific volume controls. In order to improve power consumption based on mixer configuration, controls have been added so that when certain controls within the mixer are muted, the operational amplifiers used in implementing their function are put into an Idle State to reduce power. Functions are put into

150

SUBSTTTUTE SHEET (RULE 26) an Idle State upon the following conditions. (Note: Numbers in parenthesis represent the number of op-amps in that block. Mic, Imbst, Outbufl, and Outbufr use 6pa4_big type op-amps which means its op-amp can source or sink twice as much current as the other block's op-amps (800 uA vs. 400 uA).)

Auxl 1 (1) - lxl im and lxlm are set (inputs to inmix and outmix are muted)

Auxlr (1) - rxlim and rxlm are set (inputs to inmix and outmix are muted) Aux21 (1) - lx2im and 1x2m are set (inputs to inmix and outmix are muted) Aux2r (1) - rx2im. and rx2m are set (inputs to inmix and outmix are muted) Dac21 (3) - 1 lim and 1 lorn are set (inputs to inmix and outmix are muted) Dac2r (3) - rlim and rlom are set (inputs to inmix and outmix are muted)

Mic (1) - lmim, 1mm, rmim, rmm are set (inputs to inmix and outmix are muted)

Imbst ( 1 ) - Mic is IDLED and boost is off

Mono in (1) - miml and mimr are set (inputs to outmix are set)

Inmixl (1) - Auxl 1, Aux21, Dac21, and Mic are IDLED when Dacl 1 is muted Inmixr (1) - Auxlr, Aux2r, Dac2r, and Mic are IDLED when Daclr is muted

Outmixl (1) - Auxll, Aux21, Dac21, Mic, and Mono In are IDLED when Dacll is muted

Outmixr (1) - Auxlr, Aux2r, Dac2r, Mic, and Mono In are IDLED when Daclr is muted

XP3D filt (3) - en3d is not set (both in C 13 and XI 8) XP3D outl ( 1 ) - Outmixl and XP3D filt is IDLED when loam is set XP3D outr ( 1 ) - Outmixr and XP3D filt is IDLED when roam is set

Outbuft (1) - Outmixl and XP3D filt is IDLED when loam is set

Outbufr ( 1 ) - Outmixr and XP3D filt is IDLED when roam is set

The routing of an accelerator 139 data to DAC1 or DAC2 depends on the system operating mode. In DOS protected mode game environments where the accelerator 139 is providing the wavetable function that data combined with Sound Blaster wave data. As such the an accelerator 139 data is routed through DAC2 6401 and the Sound Blaster wave data is routed through DAC 1 110. In WTN95 operating mode, the accelerator 139 provides all the wave mixing which is routed through DAC 1 for highest audio quality output.

To utilize the DSP capability of accelerator 125 (FIGURE 1), the ability is provided to send digital audio data to accelerator 125 via a digital serial link. A mux is provided to select between two digital audio sources. These sources are the ADC and ISA Bus playback FIFO.

151 SUBSTTTUTE SHEET (RULE 26) By routing the ISA Bus generated audio data over to accelerator 125 and then selecting the accelerator 139 output as the input source into DAC 1 , digital audio data from a Sound Blaster game may be processed/enhanced and then sent back to the codec 100 for output via the line output jacks. In addition the ADC output can be selected as a source for digital data to accelerator 125.

This allows analog audio sources to be sent to the accelerator 139 for processing and then sent back over the serial link to the codec 100 for audio output via DACl. This also results in the ability to mix in ZV Port data simultaneously via DAC2. One limitation to mixer is that Intemal FM data cannot be digitally routed to the accelerator 139. To enable accelerator 125 to process both ISA Bus Wave audio and analog audio through the ADC simultaneously requires that the ISA Bus FIFO data be routed through DAC 1 , into the input mixer to create an analog sum of Wave and analog audio. The ADC output is then sent to accelerator 125 of the serial link for processing. Because DACl is used in this instance for Wave data, DAC2 must be used for converting the serial data output from the accelerator 139 to analog. In alternate embodiments, the Spatial Enhancement function is done in the analog domain. This advantageously enables all audio sources, whether digital or analog, to be spatially enhanced.

The LINE_ΓN Inputs may be removed. The eliminated analog input has been replaced by primarily digital sources such as intemal FM and extemal Wavetable. The volume control registers 118 119 associated with the removed LINE -IN function are retained for compatibility reasons. As such, accesses to these registers may affect volume changes to the FM or extemal wavetable audio streams depending on the setting of certain bits.

The output from DAC2 may be included as an input to the Input Mixer. This allows

Intemal FM, extemal wavetable, or ZV Port audio to be provided as an analog audio source into the ADC for recording purposes, he existing mute bits for the LLNE_IN (118, 119) function are changed to control the mute function of DAC2.

The MIC input may be changed to mono only. The left and right volume controls (X2, X3) are combined to operate as one. Accessing either register will affect the microphone volume. The mute controls operate similarly. The 20 dB boost stage into the output mixer may be eliminated and the existing 20dB boost stage on the MIC input drives both the output mixer and input mixer. The bits (LMBST, RMBST) associated with enabling the output mixer boost stage have been changed to also affect the enabling of the 20dB boost stage.

152 SUBSTTTUTE SHEET (RULE 26) The Volume Control Into ADC 111 may be removed. For Mode 3 operation a microphone boost amplifier is included to replace the gain amplifier that was removed. I n alternate embodiments, the Codec Register Access Redirection function is eliminated. One register mapping mode may be added to allow the AUXl volume confrol to be controlled by either register pair 12/13 or by register pair 118/119. This function is controlled by the AUX 1 R bit in register XI 8.

The register Version/ID bits at control register C 1 (default = 100111 xx) may change to reflect any changes in the alternative embodiments. FIGURE 67A and the discussion below describe the implementation of the feature. This read only register shadows the current contents of codec indirect register X25 to be read by microcontroller 103. This register holds the current chip identifier and version number.

V2-V0 Version number. As enhancements are made, the version number is changed so software can distinguish between the different versions; CID4-CID0 Chip Identification bits: Change To Allow microconfroller 103 Access to Version/ID X25

Through SFR Address Space. FIGURE 68 is a diagram of the bitfields of the FAB Port ID at Control Indirect register C17, (default = 00000100). In order to track the various FAB ports of the CS4235 this register is updated each time any changes are done to the current revision in order to accommodate FAB specific requirements.

Codec registers may not in same logical device as Control Registers. For example, Map

Control Registers may be moved into Codec Extended Register Space. This may be done by using Timer Registers 120 and 121 to map Control Base + 5 and Control Base +6 registers. The mapping of Control Base +5,6 is enabled by (set to a one) the PAE bit in Register XI 8. When the PAE =0 then registers 120 and 121 become read/write only.

FIGURE 69A is a diagram of the bitfields of Command Register (codec 121), (default =

00000000) in alternate embodiments. This register is used to control various functions of the alternate embodiments. A Command is executed after the appropriate Command identifier is written to this register. When this register is either read or written via the ISA bus an interrupt will occur to microcontroller 103 via INTI.

FIGURE 69B is a diagram of the bitfields of Program RAM Access End Register (base +6), (default = 00000000). This register is used to end access to the Program RAM memory of

153 SUBSTTTUTE SHEET (RULE 26) the altemate embodiment. When this register is written via the ISA bus, an interrupt will occur to microcontroller 103 via INTI :

Map rest of Control Base + 0,1,2,7 and Confrol Indirect Registers CI2, CI8, and CI9 into

Codec Extended Register space. Note: when accessing power down functions using the X-Mapped Control Registers the clock must never be disabled (XTAL=1).

In altemate embodiments, a New Crystal Key may be defined that allows the device to be configured uniquely when two devices coexist in the same system. Microconfroller 103 should support configuring all codec 100 physical/logical devices and downloading of resource data and RAM patch data. In addition a new pin may be defined for providing a "Hardware Strap" function for providing a power-up (RESDRV) defined I/O address for receiving either the

Plug-n-Play or Crystal Backdoor Keys. This address replaces the standard 0x279 address. This will enable motherboard devices to be configured through a specific hardware address that is different from the standard PnP address of 0x279. The HWSTRAP pin when pulled low (intemal pull-up to VDD) will force the "Key" address port to one of three fixed addresses. The fixed address is selected by pullups/pulldowns on the HWSTRAP and SCL pins. The use of pin 2

(FSYNC) which may be either an input or an output is ok since this pin operates as input when connected to extemal wavetable, and extemal wavetable tri-states, this pin when it is held reset via BRESET.

HWSTRAP and SCL are sampled on power-up when RESDRV transitions from a one to a zero. The state of these pins determines what ISA bus I/O address is used for the PnP and

Crystal Keys, TABLE 90 summarizes the relationship between HWSTRAP and FSYNC.

The following 32-byte hex sequence defines the "Crystal Key 2". Once this 32-byte sequence is detected the following 2-bytes specify the 12-bit address for the configuration read/write data port. Logic in the device will load the 12-bit address for the traditional Plug-n-Play read_data_port address decode when this 32 byte sequence is detected. Once the address for the configuration port has been specified then the CS4235 device may be configured using standard Plug-N-Play commands.

95,B1,D8,6C,36,9B,4D,A6,

D3,69,B4,5A,AD,D6,EB,75, BA,DD,EE,F7,7B,3D,9E,CF,

67,33,19,8C,46,A3,51,A8, (read_data_port address)

154 SUBSTTTUTE SHEET (RULE 26) When the Crystal Key 2 sequence is detected microcontroller 103 is interrupted via INTO and status bits are placed on IOPORT 1. When microcontroller 103 detects receipt of "Crystal Key 2" microcontroller 103 puts Codec 100 into the Plug-N-Play configuration state. The next byte (#33) sent to the "Key Port" following receipt of the 32 byte Crystal Key 2 sequence sets the Read_Data_Port address. The hardware detects this and directly writes byte #33 into the

Read_Data_Port register. Plug-N-Play commands are then sent to the Read_Data_Port to configure the various logical devices.

During Plug-n-Play sequences the IntO input to microconfroller 103 is forced active whenever a "Plug-n-Play Key" or "Crystal Key2" is received, microcontroller 103 I/O Port 1 is used to provide further Plug-n-Play status to microconfroller 103. The PnP status register configuration when Crystal Key 2 is employed is shown in FIGURE 70, where:

KEY2 0= PnP Key or Crystal 1 Key Received, 1 = Crystal Key 2 received;

KEY1/RDR 0= PnP Key Received, 1= Crystal Key 1 Received/ Resource Data Read; DRD PnP ISA Bus read from PnP Data Register pending; DWR Pnp ISA Bus write to PnP Data Command Register pending; and

ADWR Pnp ISA Bus write to PnP Address Command Register pending.

In altemate embodiments, Software uses Control Register Base + 0 and Base + 2 registers for power down. Power down values of OxCO for Control Base +0 and 0x7E for Control Base +2 may be used. For non-plug-n-play functions microcontroller 103 will automatically enter the idle state upon completion of each command. The only Plug-n-Play mode in which microcontroller 103 will enter the Idle State is Wait-For-Key.

Microconfroller 103 will only initialize registers from an initial power up state (RESDRV active). Microcontroller 103 will set a Flag upon initial power up (RESDRV active) which will be retained during power down. This Flag when = 0 indicates that microconfroller 103 has been brought out of reset via an initial power on condition (registers must be initialized). Then when

= 1 indicates that microcontroller 103 has been brought out of reset via a resume condition (registers do not have to be initialized).

Some examples of possible power down scenarios are shown below. Other combinations may be possible depending on the setting of the various power down bits. Suspend/PnP maximum power savings with data retention and PnP enabled. XTAL remains active so that microconfroller 103 can be reactivated via PnP

155 SUBSTTTUTE SHEET (RULE 26) intermpt. microcontroller 103 reverts back to Idle Mode when device returns to Wait For Key State. Suspend/

Disable through software (BIOS) allow codec mixer to be programmed and then allow device to be disabled for all ISA bus accesses including

Plug-n-Play. This enables BIOS, through the use of the Setup Utility, to remove an onboard audio device from the system, but still allow audio signals such as Speaker and CDROM to flow through. This is accomplished through the use of Crystal Key 2. XTAL off, VREF on, microcontroller 103 held reset. All other registers retain values.

Suspend/Full Maximum power savings.

XTAL off, VREF off, microcontroller 103 held reset, all registers retain data. Resume is accomplished by turning XTAL and VREF back on and restoring microcontroller 103 state. When physical devices are disabled, via activation register, their function may be powered down.

All device registers (including codec volume controls) may be made accessible independent of any power-down state when the clock is running (XTAL=0, RESDRV=0).

The registers used to control the various possible power down features are shown in FIGURES 71 A-71 C. These registers also control various functions in the altemate embodiments, as described below.

FIGURE 71 A is a diagram of the bitfields of Miscellaneous Control Register at CTRLbase +0, (default = 0x00000000). The bitfields of this register are decoded as follows: JS1, JS0 - select among four joystick operating speeds:

0 0 = slowest speed; 0 1 = medium slow speed;

1 0 = medium fast speed; and

1 1 = fastest speed;

CONS controls host interrupt generation when a context switch occurs. The interrupt will only be passed through to the ISA bus if an interrupt resource was specified for the CS4235 logical device and the Plug-n-Play configuration manager mapped the interrupt. Thus setting CONSW to a one does not necessarily guarantee that an ISA bus intermpt will get generated on a context switch:

156

SUBSTTTUTE SHEET (RULE 26) 0 = no interrupt generated on context switch) and

1 = interrupt generated on context switch; PM1 , PMO control the various power down modes:

0 0 = normal operation; 0 1 = The ADC, DAC, FM, and SRC's are powered down. Analog mixer is still active in this mode and volume confrol registers are active;

01 = normal operation; and

1 1 = In this mode the ADC, DAC, FM, SRC's, microcontroller 103, mixer including VREF are all powered down. Microcontroller 103 puts itself into IDLE mode. An interrupt to microcontroller 103 will cause microcontroller 103 to exit

IDLE mode and resume normal operation, but all other powered down functions remained powered down. No codec registers are reset; PDC Power Down Codec:

0 = Normal operation; and 1 = ADC, DAC, FM, and SRC's are powered down. In this mode the codec interface remains active and registers, including mixer registers, may be read or written; PDP Power Down Processor:

0 = Normal operation; and 1 = indicate to microcontroller 103 that it should enter idle mode, microcontroller

103 puts itself into idle mode. Any interrupts generated to microcontroller 103 (PnP, Sound Blaster, MPU-401, Context Switch) will cause microconfroller 103 to exit IDLE mode and resume normal operation. Microcontroller 103 will clear this bit when idle mode operation is exited; PDM Power Down Mixer:

0 = Normal operation; and

FIGURE 71B is a diagram of the bitfields of Power Down Confrol Register 1 at CTRLbase +2, (default = 00000000).

PDDR Full Power down with data retention. When this bit is set to decoder 100 is put into a full power down, data retention mode. All functions are

157 SUBSTTTUTE SHEET (RULE 26) disabled except reads and writes to this register. Microcontroller 103 is held reset and all clocks are disabled including the XTAL. All registers retain the values held when this power down mode is entered. No resets should be generated except for microcontroller 103. When this bit is set to zero the decoder 100 will resume normal operation after valid clocks are detected.

SRC Power down of the ADC and DAC Sample Rate Converters when set=l .

The sample rate for both capture and playback fixed is at 44100 Hz when this bit is set = 1. Since the SRC is powered down by other bits, this bit is useful for test purposes only.

VREF Power down of the reference voltage source when set =1. MIXER Power down of the mixer analog section except for the Mono-In and

AUX2 path through to the line outputs when set =1. All op amps except for the Mono-In, AUX2, and opamps required to pass the Mono-In and

AUX2 signals to the Line Out are powered down. All analog inputs and outputs are centered around VREF, if VREF is enabled and not powered down. A reset is not required to maintain the calibrated state if the mixer is powered down and VREF is powered up.

ADC Power down of the ADC, decimator, and capture SRC/FIFO. Capture timing is disabled.

DAC Power down of DACl and DAC2, switched capacitor filter, interpolator, playback SRC/FIFO, FM engine, serial port circuitry. Playback timing is disabled. FM section is reset.

Microcontroller Microconfroller 103 monitors this bit and executes a command to put microconfroller 103 into IDLE mode. No hardware power down function is directly wired to this bit. This power down mode is controlled by microcontroller 103 only. Any interrupts generated to microconfroller

103 (PnP, Sound Blaster, MPU-401, Context Switch) when microconfroller 103 is in IDLE will cause microcontroller 103 to automatically exit IDLE mode and resume normal operation.

FM Power down of the FM synthesis engine when set =1. When this bit is set

=1 the entire FM block is held reset.

158

SUBSTTTUTE SHEET (RULE 26) FIGURE 71 C is a diagram of the bitfield of Power Down Control Register 2 at Control Indirect + 0x9, (default = 00000000):

CI9EN Control Indirect Register 9 Enable. When this bit is set to 1 the CS4235 is enabled to be powered down by bits located in this register and by microcontroller 103, SRC, and FM bits located in CTRL_base +2. Power down functions controlled by other bits located in Confrol Base +0,2 are nonfunctional when CI9EN=1. The specific power down mode is defined by the state of the other bits in this register. Once the power down function is defined by bits D6..D0, this bit may be toggled to enable/disable the power down function. CI9EN means power down to state defined by bits D6..D0. CI9EN = 0 means ignore bits D6..D0 and no power down functions are performed by this register;

XTAL The crystal oscillator is disabled when XTAL=1. All functions are disabled except reads and writes to this register. Microcontroller 103 is held reset and all clocks are disabled. All registers should retain the values held when this power down mode is entered. No resets should be generated except for microcontroller 103. When this bit is set to zero Codec 100 will resume normal operation after valid clocks are detected;

VREF Power down of the reference voltage source when set = 1; MIXER Power down of the mixer analog section except for the Mono-In and AUX2 path through to the line outputs when set=l . All op amps except for the Mono-In, AUX2, and opamps required to pass the Mono-In and AUX2 signals to the Line Out are powered down. All analog inputs and outputs are centered around VREF, if VREF is enabled and not powered down. A reset is not required to maintain the calibrated state if the mixer is powered down and VREF is powered up;

ADC Power down of the A/D converter, decimator, and capture SRC/FIFO. Capture timing is disabled;

DACl Power down of the playback FIFO/SRC, Wave-DAC, switched capacitor filter, interpolator when set=l. Playback timing is disabled;

159

SUBSTTTUTE SHEET (RULE 26) DAC2 Power down of the FM/external wavetable/ZVPORT Dae when set=l:

Setting this bit to a one also powers down the FM block. FM section is reset; and SPORT Power down of the extemal wavetable, ZVPORT, and DSP serial interfaces when set = 1.

To handle situations in which the IOCHRDY is asserted and never released a Watchdog timer may be added. A signal hung IOCHRDY scenario may occur, for example, when IOCHRDY is asserted and the hardware is waiting for a response from microcontroller 103 to clear it, which does not occur for some reason. This could occur due to corrupt host down load or via a chip defect that was not caught by test vectors. Because a hung IOCHRDY is a good indicator of a system problem a host accessible status bit is provided when the Watchdog timer has timed out.

The Watchdog timer is defined to timeout 10msec sees after IOCHRDY has been asserted. If IOCHRDY has not been released by the time the Watchdog Timer times out, IOCHRDY will be released and a reset will be generated to microcontroller 103. In addition the time out flag will be set to a one.

When this option is implemented, Codec Timer is decoupled from registers 120 and 121 and used to implement the Watchdog Timer. The TE bit in Register 116 will no longer be functional and will always read a zero. The Timer Interrupt TI is also forced to be read as zero. The Watchdog Timer Status (WTS) bit is defined to reside in CTRLBase +7, bit D2, as shown in FIGURE 72. The Watchdog Timer is disabled in Primary Test Mode 4.

An additional intermpt map select bit for an additional interrupt IRQG may be added. Intemal interrupt to interrupt pin mapping consequently operates as follows. Each interrupt pin IRQA-IRQG has an index associated with it according to TABLE 86. This index value is written to the corresponding microcontroller 103 interrupt configuration register to map a specific interrupt to a specific intermpt pin. This architecture allows multiple intermpt sources to be mapped on a single interrupt pin.

FIGURE 73 is a diagram of the bitfields of the intermpt select register used to implement intermpt control. In altemate embodiments, the modem mask register shown in FIGURE 74 may be used as a CDROM Base Address Mask Register at microcontroller 103 Address 0x33. The CDROM

Base Address Mask Register provides a means to vary the number of consecutive byte locations that the CDROM decode may occupy. Each mask bit is used to prevent specific address bits^' from being decoded in generating the modem I/O decode. The valid bit combinations are as shown below. All other combinations are invalid and may cause eroneous operation. The decoding is shown in TABLE 87. The altemate embodiments, the SRS/QSound features may be replaced with the analog circuitry shown in FIGURE 75 A. This circuitry provides for spacial enhancement of stereo sources. The frequency contour is shown in FIGURE 75B.

Acoustic Crosstalk arises when a stereo signal is reproduced by two loudspeakers located to the left and right in front of the listener. Each ear receives not only the wanted signal (left ear - left signal, right ear - right signal) but, additionally, an unwanted part of the opposite channel, as a result of diffraction at the head. The amount of crosstalk is frequency dependent and diminishes with increasing frequency. As a result of this crosstalk, stereo images can only be reproduced in between the two loudspeakers. Stereo images cannot be created to the extreme right or left of the loudspeakers. The unwanted crosstalk signal can be compensated for by feeding each loudspeaker with a filtered version of the opposite channel signal inverted in sign and superimposed on the original signal. Although sophisticated frequency response shaping and phase correction can be applied to the crosstalk compensation signal to more accurately place stereo images in space, it is not the intent of this design. The intent of the design is to spread the stereo image beyond the boundaries defined by the position of the loudspeakers themselves. To this end, the frequency response shaping network has been kept simple from a circuit implementation and component count point of view. The frequency response shaping characteristic was determined from a listening perspective. Because most directional information occurs at mid-band frequencies, this frequency range will be elevated in level as compared to the low and high frequency extremes. To compensate for this effect, the mid-band frequencies are filtered to provide a 6dB dip in the response centered around 2 kHz.

As shown in FIGURE 75A, analog spacial enhancement circuitry 7500 includes an analog subtractor 7501, notch filter 7502, inverter 7503 and a pair of summers (adders) 7505 and 7506.

In the analog enhancement circuitry illustrated in FIGURE 75 A, a difference amplifier (subtractor 7501) is used to create a Left minus Right signal. This signal is then filtered by a network consisting of R16, C5, R18, and C6. This filtered signal is the crosstalk compensation signal. The signal is then summed into the main left channel (summer 7505) and inverted and

161 SUBSTTTUTE SHEET (RULE 26) summed into the main right channel (inverter 7504 and summer 7506). The left channel is thus composed of Left plus a filtered left-minus-right signal. Correspondingly the right channel is composed of Right plus a filtered right-minus-left signal. The gain of 1/2 in the summing stage is to compensate for the fact that a mono signal will result in an overall gain of 2. Thus the summer gain of 1/2 will result in an overall gain of 1 (summers 7505 and 7506) when a mono signal is present.

FIGURES 75C and 75D are respectively the modified 3D Sound/Serial Interface Control

(Codec Extended Register at XI 8, (default = 00000000) and 3D Sound Control (Control Indirect

CI3, (default = 00000000). Analog 3D enhancement is enabled by either 3DEN (bit D4) in register XI 8 or by 3DEN (bit D4) in Confrol Indirect C 13 when set = 1. When the 3DEN bit in both registers are zero then the 3D enhancement function is disabled.

In altemate embodiments, serial interface (port) 117 may be modified to simultaneously communicate with wavetable synthesizer 134 and accelerator 125 or with accelerator 139 and

ZVPORT. Specifically, either wavetable synthesizer or ZVPORT may be selected as the input to the R-ZR DAC. When the accelerator is connected to the serial port, the SVPORT data is routed to the R-ZR DAC and the accelerator data to the Delta-Sigma DAC.

The serial port 117 interface consists of seven pins. In the preferred embodiment, these pins are defined as SDATA, LRCLK, MCLK, FSYNC, SDOUT, SDIN, and SCLK. In one altemate embodiment, these pins are defined as SDATA, FSYNC(LRCLK), MCLK(SCLK), ZVLRCLK, SDOUT, ZVSDATA, ZVSCLK. TABLE 88 describes this modification, where, for the preferred embodiment:

SDATA Pin 1, Input - This pin accepts serial audio data input from wavetable synthesizer 134; LRCLK Pin 2, Input - This pin inputs the LRCLK signal from wavetable synthesizer 134;

MCLK Pin 3, Output - This pin provides a buffered 16.9344MHz clock for wavetable synthesizer 134; FSYNC Pin 4, Output - This pins provides the FSYNC signal to accelerator 139;

SDOUT Pin 5, Output - This pin provides serial audio data to accelerator 139; SDIN Pin 6, Input - This pin accepts serial audio data from accelerator 139;

SCLK Pin 7, Input - This pin provides the SCLK signal to accelerator 139;

162 SUBSTTTUTE SHEET (RULE 26) and where for the altemate embodiment:

SDATA Pin 1, Input - This pin accepts the serial audio data from wavetable synthesizer 134 or accelerator 139; LRCLK (FSYNC) Pin 2, Input/Output - This pin provides the FSYNC signal to accelerator

139 or alternately inputs the LRCLK signal from wavetable synthesizer 134; MCLK

(SCLK) Pin 3, Output - This pin provides the SCLK signal to accelerator 139 or alternately the buffered 16.9344MHz clock for wavetable synthesizer 134;

ZVLRCLK Pin 4, Input - This pin accepts the LRCLK signal from ZV Port; SDOUT Pin 5, Output - This pin provides serial audio data to accelerator 125;

ZVSDATA Pin 6, Input - This pin accepts serial audio data from ZV Port; and ZVSCLK Pin 7, Input - This pin accepts the SCLK signal from ZV Port. TABLE 89A shows the decoding of the WTEN and SPE bits which control the serial interface 117 pins in the preferred embodiment. TABLE 89B shows the decoding of the WTEN, SPEN, and ZVEN bits which control the serial interface 117 pins in the altemate embodiments. In the altemate embodiment, the accelerator DSP serial port is enabled by setting the SPE bit in codec register 116. Once this bit is set to a one the DSP Serial Port pins function as specified by the SF 1 :SF0 bits in register 116. Serial Port Mode 4 are be used to transfer ADC and playback SRC data simultaneously out the Serial Data Out pin. All other Serial Port modes support fransfer of ADC data out the Serial Data Out pin.

The wavetable synthesizer 123 serial interface is enabled by setting the WTEN bit in register C8 to a one. If both WTEN and SPE are set then the pins are forced into an accelerator 125 DSP serial port mode.

FIGURE 76 is a diagram representing the serial interface connection of accelerator 139/ZVPORT with an altemate embodiment of Codec 100.

Similarly, FIGURE 77 shows the connection of wavetable synthesizer 134 with this embodiment of Codec 100. This connection is advantageously a zero glue logic connection. Serial Port Mode 3 (SF1,0 = 11). Serial Port Mode 3 is selected by setting the SFI,0 bits in register 116 to 11. This format is a 64 bit per frame format that includes ADC as well as DAC 16-bit data. This mode is intended for use by an extemal DSP such as accelerator 139.

163 SUBSTTTUTE SHEET (RULE 26) The wavetable synthesizer 123-codec 100 combination in the alternative embodiments has several advantages:

1. This combination operates from one 16.9344MHz crystal or clock source. Codec 100 is the master clock generator for the wavetable; 2. The serial interface for the wavetable requires only three pins: MCLK, LRCLK, and SDATA. The Accelerator 139 generates only the master clock via the MCLK pin for wavetable synthesizer 134. This insures that both devices operate synchronously. Because of timing skews between codec 100 and the wavetable, codec 100 synchronizes the data sourced from the wavetable to its intemal clock. Codec 100 detects the edge of LRCLK and performs synchronization so that the digital audio from the wavetable is mixed properly with codec 100 intemal audio data before being sent to the DAC;

3. The three pins defining the Codec/wavetable serial interface. These pins are enabled by bit WTEN in Control Indirect Register CI8; and

4. BRESET - The BRESET pin is forced low when RESDRV high, when PM1, PMO are set to 10 in CTRLbase + 0, or when the BRESET is set to one in register C8.

To minimize the number of serial port timing modes required by the wavetable synthesizer 134, the serial port timing is defined to match the default intemal SCLK mode for a 384fs master clock. The SCLK frequency is 48 x 44.1 kHz. Thus the least significant 16-bits should be accepted and the rest ignored. This timing is illustrated in FIGURE 78, for the Intemal SCLK Mode, where 16-Bit Data is shown:

Data Valid is on Rising Edge of SCLK; and the INT SCLK = 48Fs if MCLK/LRCK = 384.

The ZV Port interface requires support for a 256Fs and 384Fs master clock. The timing is specified as I²S. The ZV Port interface must automatically detect the ZVLRCLK/ZVSCLK ratio and set the proper data formatting. A 384Fs, ZVMCLK results in a ZVLRCLK to ZVSCLK ratio of 32 and a 256Fs ZVMCLK results in a ZVLRCLK to ZVSCLK ratio of 48. The ZVPORT inputs are again as follows:

Pin 4 - ZVLRCLK - Input;

Pin 6 ~ ZVSDATA -Input; and Pin 7 ~ ZVSCLK - Input.

164 SUBSTTTUTE SHEET (RULE 26) The ZVMCLK is not required for ZVPORT support. Although the LRCLK SCLK ratio must be detected and automatically switched to support the 256Fs and 384Fs ZVMCLK data formats.

The ZV Port definitions are as follows: ZVLRCLK This signal determines which audio channel (left/right) is currently being input on the audio Serial Data input line. ZVLRCLK is low to indicate the left channel and high to indicate the right channel. For a ZVMCLK frequency of 384Fs the LRCLK to SCLK ratio is 48. For a ZVMCLK frequency of 256Fs the ZVLRCLK to ZVSCLK ratio is 32. ZVSDATA This signal is the digital PCM signal that carries the audio information.

Digital audio data is transferred using the I²S format. The I²S formats are in FIGURES 79A and 79B, where in FIGURE 79A ax ZVMCLK=256Fs and is assumed and ax ZVMCLK=394Fs is assumed in FIGURE 79B.

The digital audio data is left channel-MSB justified to the high-to-low going edge of the LRCLK plus one SCLK delay.

ZVSCLK This signal is the serial digital audio PCM clock.

ZVMCLK This signal is the Master clock for the digital audio. ZVMCLK is asynchronous to ZVLRCLK, ZVSDATA and ZVSCLK. The ZVMCLK must be either 256x or 384x the desired Input Word Rate (IWR). IWR is the frequency at which words for each channel are input to the DAC and is equal to the ZVLRCLK frequency. The following table illustrates several standard audio word rates and the required ZVMCLK and ZVLRCLK frequencies. The ZV Port audio DAC must support a ZVMCLK frequency of 256 times and 384 times the input word rate. This results in the frequencies shown in TABLES 93A and 93B.

FIGURE 80 is a diagram illustrating the ZV Port Audio Interface timing. TABLE 94 tabulates the AC parameters for these audio signals.

FIGURE 81 is a diagram emphasizing one digital audio path for the altemate embodiments. The Digital Audio Data Path components include the Delta Sigma ADC, Delta Sigma DACs 6401 and 6402, FIFOs 121 and 122, R-2R DACs 6401 and 6402, and Serial interface. Analog audio is digitized by the ADC, decimated, and sent to the ISA bus capture

FIFO and optionally sent out the serial output pin as defined by the SPISEL (Control Index C3 bit D5) bit. Digital audio data (.WAV) sourced from the ISA bus playback FIFO 122 is sent to the Delta Sigma DAC 110 as selected by the DACSEL (Codec Extended Register bit D3) bit through multiplexer 8101. Alternately the digital audio data sourced by the accelerator Serial Interface may also be sent to the Delta Sigma DAC 110 for conversion to analog. The data audio data sourced from the FM block 116 is summed with wavetable digital audio data at block 8102 and sent to the R-2R DAC 6401 for conversion to analog. Alternately, mux 8103 allows the accelerator 125 digital audio data to also be sent to the R-2R DACs. The serial port digital output data may be either sourced from the ADC or from the ISA bus playback FIFO 120.

FIGURE 82 depicts the bitfields of the 3D Sound/Serial Interface Control at Codec Extended Register, XI 8, (default = 00000000) in the altemate embodiments. The bitfield decoding is as follows:

PAE Control Register Enable - enables access to Control Registers Base +5,6 in Codec Extended Register (120 121) space when set=l ; res Reserved - reads back as zero; AUX1R AUXl Remap - Switches control of the AUXl volume control registers from 12 13 to 118/119 when set= 1 ; 3DEN When this bit is set to 1, the 3D Audio is enabled and will process any stereo signal output from the Output Mixer. This bit is logically OR'd with the 3 DEN bit in Control Indirect Register C3 bit D7; DSSEL1 This bit selects the source of digital data for the Delta Sigma DAC

(DACl). DSSEL1 =0 for playback FIFO, DSSEL1 =1 for the accelerator/DSP serial interface; ZOH Zero Order Hold. When this bit is set to a one the last sample is always held into the DAC when PEN is brought from a one to a zero; ZVEN This bit selects enables the ZV Port interface. ZVEN = 0 for disabled,

ZVEN = 1 for enabled. When ZVEN = 1 then the wavetable/FM input into DAC2 is disabled; and

DLBEN This bit when set to 1 selects the output of the ADC as an input to DAC 1.

As described above, the Delta Sigma DACs 110 operate at a fixed 44.1 kHz rate. As such it is assumed that the accelerator 139 input data rate will be 44.1 kHz. The inclusion of the R-2R

DACs 6401/6402 allows for asynchronous digital audio data to be accepted via serial interface

166

SUBSTTTUTE SHEET (RULE 26) 117 as is required for ZV Port support. Accelerator/DSP digital audip data may also be converted by the R-2R DAC, but some signal degradation may result.

DAC2 (R-2R) 6401/6402 is a 13-bit device. The FM and wavetable synthesizer word widths are 16-bits. To allow the FM and extemal wavetable data streams to be heard at the same time, an adder/truncator 8102 is used to combine the streams into one 13-bit data stream for input to DAC2 6401/6402. Because the volume control function only operates as part of DAC2 some method of adjusting the relative volume level between the FM and wavetable sources is desirable. Therefore, a data selector is used to specify which 13-bits of the 16-bit FM data word are selected as an input to adder/truncator 8102. Codec Extended Register XI 9 is used to confrol this function, in accordance with TABLE 95.

In altemate embodiments, logic and ROM's associated with u-Law/A-law/ADPCM/Big Endian functions 120 may be removed. In this case, Index Register 18 is changed as indicated by highlighted and italicized boxed items in TABLE 96. Formats associated with deleted functions now default to one of two supported formats: Linear, 8-bit unsigned or Linear, 16-bit two's complement, Little Endian. Additionally, index registers 117 and 123 are appropriately modified as shown in FIGURES 83 and 84, respectively.

In FIGURE 83, APAR - ADPCM Playback Accumulator Reset. While set, the Playback ADPCM accumulator is held at zero. Used when pausing a playback stream.

IN FIGURE 84, ACF ADPCM Capture Freeze. When set, the capture ADPCM accumulator and step size are frozen. This bit must be set to zero for adaptation to continue.

This bit is used when pausing a ADPCM capture stream.

Due to the ADPCM function being deleted the APAR and ACF bits are now defined to always be zero.

The Digital Joystick Assist 16-bit counters and logic as well as the DAC gain/attenuator may also be removed. In the case of removing the DAC gain-attenuator, register accesses to 16 and 17 are mapped to the digital .WAV gain-attenuation control. Extended Registers X14 and X15 no longer have any function associated with them, but retain read/write capability. When 16 or 17 are used to mute the WAV playback the corresponding output channel of the DAC is also muted. In this way the analog noise contribution of the DAC will be muted when the digital WAV playback is muted.

The Mono Out supporting logic may be eliminated and the mono input functions minimized. Mono 126 is changed as shown in FIGURE 85. The MBY and MOM bits no longer

167 SUBSTTTUTE SHEET (RULE 26) have any function associated with them. These bits remain read/write accessible. The MI A3 -MI AO bits are changed to allow 2 attenuation settings. A zero value for MI A3: MI AO specifies a OdB attenuation, a non-zero value for MIA3:MIA0 specifies an attenuation setting of -9dB. In FIGURE 85: MIA3-MIA0 Mono Input Attenuation:

0000 = OdB, 0001-1 11 1 = -9dB; rw Read/Write. No function associated with these bits res Reserved. Must write 0. Could read as 0 or 1; and

MIM Mono Input Mute. Controls the mute function on the mono input, MIN. The mono input provides mix for the "beeper" function in most personal computers.

When MIM=0, MBY should be 0:

0 - no mute; and

1 - muted.

The following additional features may be eliminated in the altemate embodiments; 1 ) LLNE_LN Analog Input and the associated volume confrol;

2) Differential Mic Analog Inputs and the opamps associated with this function;

3) ADC Digital Loopback Attenuator and the logic associated with ADC digital loopback attenuator. Registers 113 and XI 0 now have no function and should be read/write accessible from the ISA bus. The loopback function is still available in Codec Extended Register XI 8 bit DO; and

4) ADC Input Master Gain Confrol including the analog 0 - 22dB gain block between input summer and ADC. The LAG3:0 and RAG3:0 now become don't cares in the left and right ADC input control registers (codec register 10 and II). Any value read or written to these registers results in no functional change in the device. The LSS 1 :0 and RSS 1 :0 bits function as before as they select analog loopback when =1,1. The LMGE and RMGE bits currently are disabled in MODE3. The MIC Input may be modified as follows:

1 ) Change MIC input to mono only;

2) Delete MIC right channel gain block. Register X3 (Right MIC volume) accesses are now directed to X2 (Left MIC Volume). In this way software accesses to either register will result in the MIC volume being adjusted. The left MIC input

168 SUBSTTTUTE SHEET (RULE 26) should also feed both the left and right inputs to the Input Mixer. The RMlM (Right MIC mute to input mixer) should still function normally;

3) Modify output mixer so that left mic input is routed to both right and left line outputs. The RMOM (Right MIC Output Mixer Mute) should still operate as before; allowing independent mute/unmute of MIC input to left or right line outputs; and

4) Delete 20dB gain-boost amplifier from MIC right channel. Move remaining 20dB boost amplifier so that its output drives both the Input Mixer and Output Mixer. The RMBST (codec extended register X3), LMBST (codec extended register X2), LMGE (codec register 10), and RMGE (codec register II) bits now all control enabling and disabling of the 20dB boost amplifier via a Logical OR function. In the altemate embodiments, The Master Volume registers are accessible by microcontroller 103 in SFR register space (codec registers I27A, I29A) or via ISA interface 101 through the Control Port at index I27/C27 and I29/C29. One register accessible at addresses pertaining to 127/129, C27/C29, and I27A/I29A is all that is required. Left Master Volume is accessible at index registers 127 and C27 via the ISA bus and 127 and I27A via microcontroller 103. Right Master Volume accessible at index 129 and C29 via the ISA bus and 129 and I29A via microcontroller 103. An extemal 3-button and 2-button mode of Up-Down-Mute control of master volume may be provided. This function is enabled by the VCEN bit in the EEPROM Hardware Configuration Data and in bit D2 (VCEN) of microcontroller 103 Address 0x34. Extemal Master Volume 3-button/2-button is selected by bit D6 (VCFl) of the Control Indirect Register CI8 and microcontroller 103 Address 0x40. A set of defined pins (Up, Down, Mute) may be used with extemal switches to confrol the overall audio level driven out the line outputs. Each change in button state, from high-to-low, will cause the master volume register to be incremented, decremented, or muted. If a button is held down then the increment/decrement will continue to occur at 500ms intervals. The master volume confrol hardware allows access to the master volume control registers by the ISA bus and microcontroller 103 simultaneously with volume updates initiated by extemal button activity. The hardware monitors ISA/microcontroller 103 access to the master volume control registers and updates the registers between ISA microcontroller 103 cycles.

169 SUBSTITUTE SHEET (RULE 25) In both Sound Blaster mode and WSS mode, the user may change the CODEC Master Volume via pins connected to physical switches or buttons. There are currently 2 different "button schemes" which may be used. The user selects 1 of the 2 schemes by setting the VCFl and bit in the Hardware Configuration Data, Global Configuration Byte, contained in the EEPROM.

Master Volume Confrol Bits are added to the Wavetable and Serial Confrol Indirect Register CI8 indexed by Control Base + 3 and accessible at Confrol Base + 4, as depicted in FIGURE 86. This register is also read/write accessible by microconfroller 103 at address 0x40. The bitfield decodings are:

VCFl Select Between 2-button and 3-button extemal master volume control modes where 0=3 button, 1=2 button;

SBSP Sound Blaster Swap Playback - when this bit is set to a zero, the current ordering of samples for DMA playback are swapped relative to the cuπently defined format. This bit affects only 8-bit playback in Sound

Blaster mode;

SBSC Sound Blaster Swap Capture - when this bit is set to a one the current ordering of samples for DMA capture are swapped relative to the current defined format. This bit affects only 8-bit capture in Sound Blaster mode;

WTEN Wavetable Enable - When this bit is set to a one, the Serial Interface pins are enabled to support the wavetable digital interface. When this bit is a

0, the wavetable Serial Interface pins are tri-stated;

VCIE This bit enables an interrupt to be generated on a button push when this bit is set = 1 ;

MCLKDIS When this bit is set to a one, and the wavetable serial interface is enabled by WTEN = 1 , the MCLK pin to the wavetable is synchronously forced to zero. MCLK will remain a zero until MCLKDIS is set to zero. At this time, MCLK will synchronously be enabled; and

BRESET When this bit is set to a one the BRESET pin is forced to zero. This is to allow microconfroller 103 and host control of extemal devices connected to the BRESET pin.

170 SUBSTTTUTE SHEET (RULE 26) The VCEN bit, shown in FIGURE 87, which is a diagram depicting miscellaneous control bits at microconfroller address 0x34, enables the control of the master volume via the extemal buttons.

To implement the 3 -button volume control scheme, the Up, Down and Mute pins is connected to momentary SPST switches. This scheme is selected by setting VCFl = 0 in the

EEPROM configuration data. The 3 -button functioning is summarized in TABLE 97. Pushing the Up button or the Down button will un-mute the Codec if it was muted with no volume change.

To implement the 2-button scheme, the Up and Down pins connected to momentary SPST switches. The Mute pin is not connected and is ignored. This scheme is selected by setting VCFl = 1 in the EEPROM configuration data. The 2-button functioning is summarized in TABLE 98. Pushing the Up button or the Down button will un-mute the Codec if it was muted with no volume change.

In altemate embodiments, the Extemal Master Volume hardware control may support the generation of an interrupt upon detection of a button push. The intermpt is active high and is logically OR'd with the codec/SB intermpt. An ISA accessible enable bit is used to enable the generation of this intermpt. The location of this Extemal Master Volume Intermpt status is in Global Status Register (CTRLbase +7), IMV field, as shown in FIGURE 88. IMV = 1 indicates that an interrupt has been generated in response to an extemal button push. The intermpt is enabled by bit D2 (VCIE) in Control Indirect Register CI8 and at microconfroller 103 Address

0x40.

In altemate embodiments, the Karoke function may be eliminated from the mixer. Consequently, the ADC1/ADC0 bits (Hardware control register base+1) now become read/write with no associated function. The Modem Logical Device may be eliminated by removing the modem base address low

(microcontroller address 0x30), modem base address high (microconfroller address 0x31) and modem interrupt select (microconfroller address 0x35) registers.

Primary Test Mode 13 is the Clock-Off Detect mode.

The firmware functioning used in the altemate embodiments of the principles of the present invention can now be described. After initialization based on EEPROM data and other

ROM constants, the Plug and Play mode is entered where microconfroller 103 monitors PnP hardware for PnP events and then services the PnP commands through the PnP hardware.

171 SUBSTTTUTE SHEET (RULE 26) When the PnP activity is over, signaled by the host as an activate command, the firmware continues initialization and then transitions into Sound Blaster emulation mode. This part of the code consists of a polling loop (Foreground Loop) and intermpt processing. The polling loop in general looks for status bits changed in the interrupt routines. The Microcontroller 103 is interrupted from the main loop for host activity like certain SB read/write, WSS/SB context switch, certain control port commands and by other events like MIDI data receive.

The Init code and PnP code refer to the hardware configuration data area in microcontroller extemal RAM from addresses from 0x4000 to 0x4012 and the PnP resource data area from addresses 0x4013 to 0x417F for configuration and PnP resource data. RAM locations from 0x4180 to 0x42FD in microcontroller extemal RAM are dedicated to patch space.

The Firmware host command interface is accessed through ControlBase + 5 and 6. Commands are sent and data is read from ControlBase + 5. The RAM interface command is terminated by a write of ControlBase + 6 (RAM END). These commands are summarized as follows: OxAAh - RAM POINTER LOAD: Begins the RAM/ ROM/ INTERNAL start address

LOAD for Read/Write access. Command sequence is as follows: Write to ControlBase + 5 - OxAA;

Write to ControlBase + 5 - OxLL = low byte of the microcontroller 103 xData Address; Write to ControlBase + 5 - OxHH = high byte of the microcontroller 103 xData

Address;

R/W of ControlBase + 5 - Access data starting at address, auto increment; *** Access data starting at address, auto increment; and Write to ControlBase + 6 - RAM END, Terminates command; and^" 0x42h - HOLD: Puts microconfroller 103 in a tight loop, with no codec accesses;

0x43 h - GO: Causes an exit from HOLD loop and a resumption of normal code operation;

0x57h - JUMP_TO_ROM: Forces code to jump to tight loop in ROM and overwrites the patch table with microconfroller 103 RET opcodes; 0x33 h - SUSPEND: For power management, suspends execution before powerdown.

The state of microcontroller 103 is saved and made available for the HOST to read;

172 SUBSTTTUTE SHEET (RULE 26) OxCCh - RESUME: For power management, resume execution after power down (SUSPEND);

0x3Ch - microcontroller 103 POWER DOWN: Causes microconfroller 103 to enter the IDLE state, consuming less power. This IDLE state is exited after any microconfroller 103 interrupt such as SBRESET, SB mixer access, RAM load command, etc.;

0x58h - SET_READ_ROM_FLAG: Next RAM/ROM/TNTERNAL command will READ ROM. Execution of RAM END clears this state;

0x54h - SET_ACC_INT_FLAG: Next RAM/ROM/TNTERNAL command will READ/WRITE Intemal RAM. Execution of RAM_END clears this state; 0x5 Ah - UPDATE_PNP: After Hardware header information is written, causes Plug and

Play and other system variables to be synchronized. This command is issued after resource data and hardware configuration data are loaded by the host; 0x56h - DISABLE_CKD: Disable Crystal Key. The Crystal key will be ignored after this command is issued; and 0x55h - DISABLE_PNP: Disable Plug & Play Key. The Plug and Play key will be ignored after this command is issued;

0x59h - SW_RESET: Jump to location 0x0000 of the code (RESET VECTOR). Confrol Port Command Delay Requirements. Certain delay periods are required when accessing commands and functions of the Firmware: Delay between PnP or Crystal wait-for-key command and any Control Port

Command > lmS;

Delay between UPDATE_PNP and any PnP activity > lmS; Delay After RESUME command >lmS; and Delay after JUMP O_ROM command > 1 mS . A default ROM image of PnP data including default hardware header data, PnP serial ID and PnP resource data is copied from ROM to RAM at powemp, before the optional EEPROM is detected. This image in RAM is what is used for PnP resource data and hardware configuration data if no optional EEPROM is present and no host resource shoot has been done to overwrite this default image. Below is the Default ROM PnP Image for the altemate embodiments of codec 100. The default image may be replaced at powemp by the EEPROM, or at initial time by the system

173 SUBSTTTUTE SHEET (RULE 26) BIOS. A total of 384 (decimal) bytes of resource data plus hardware header may be used. This byte count does not include the 0x55, OxBB, and length fields.

EEPROM Validation Bytes

DB 055H, OBBH ; EEPROM Validation Bytes: CS4235/9

DB 001H ; EEPROM data length upper byte

DB 014H ; lower byte, Listed Size = 276

Hardware Configuration Data

DB 000H ACDbase Addr. Mask Length = 1 bytes

DB 003H COMbase Addr. Mask Length = 4 bytes

DB 080H MCB: IHCD

DB 080H GCB IFM

DB 005H Code Base Byte (family Byte) - Mahler Lite

DB 020H FM Data Select Confrol

DB 004H RESERVED

DB 008H RESERVED

DB 010H RESERVED

DB 080H RESERVED

DB 000H RESERVED

DB 000H GCB2:

Hardware Mapping Data

DB 000H 00=4/08=8 peripheral port size, XCTL0 XA2

DB 048H RESERVED

DB 075H IRQ selection A & B - B=7, A=5

DB 0B9H IRQ selection C & D - D=l 1 , C=9

DB 0FCH IRQ selection E & F - F=15, E=12

DB 010H DMA selection A & B - B= 1 , A=0

DB 003H DMA CIRQ G select. - G=0, C=3

174

SUBSTTTUTE SHEET (RULE 26) ; PnP Resource Header - PnP ID for CS4236 IC, OEM ID = 42

DB 00EH, 063H, 042H, 036H, OFFH,OFFH,OFFH,OFFH,OA9H ; CSC4236 FFFFFFFF

DB 00AH, 010H, 005H ; PnP version 1.0, Vendor version 0.5 DB 082H, OOEH, 000H, 'Crystal Codec', 000H ; ANSI ID

; LOGICAL DEVICE 0 (Windows Sound System & SBPro)

DB 015H, OOEH, 063H, 000H, 000H, 000H ; EISA ID: CSC0000

DB 082H, 007H, 000H, 'WSS/SB', 000H ; ANSI ID DB 031 H, 000H ; DF Best Choice DB 02AH, 002H, 028H DMA: 1 - WSS & SBPro

DB 02AH, 009H, 028H DMA: 0,3 - WSS & SBPro capture DB 022H, 020H, 000H IRQ: 5 Intermpt Select 0 DB 047H, OOIH, 034H, 005H, 034H, 005H, 004H, 004H ; 16b WSSbase: 534 DB 047H, OOIH, 088H, 003H, 088H, 003H, 008H, 004H ; 16b SYNbase: 388 DB 047H, 001 H, 020H, 002H, 020H, 002H, 020H, 01 OH ; 16b SBbase: 220

DB 03 IH, OOIH DF Acceptable Choice 1

DB 02AH, OOAH, 028H DMA: 1,3 - WSS & SBPro

DB 02AH, OOBH, 028H DMA: 0,1,3 - WSS & SBPro capture

DB 022H, OAOH, 09AH IRQ: 5,7,9,11,12,15 Intermpt Select 0 DB 047H, OOIH, 034H, 005H, OFCH, OOFH, 004H, 004H; 16b WSSbase: 534-FFC

DB 047H, OOIH, 088H₃ 003H, 088H, 003H, 008H, 004H; 16b SYNbase; 388 DB 047H, 001 H, 020H, 002H, 060H, 002H, 020H, 01 OH; 16b SBbase: 220-260

DB 03 IH, 002H ; DF Suboptimal Choice 1

DB 02AH, OOBH, 028H ; DMA: 0, 1 ,3 - WSS & SBPro DB 022H, OAOH, 09AH ; IRQ: 5,7,9,11,12,15 Intermpt Select 0

DB 047H, OOIH, 034H, 005H, OFCH, OOFH, 004H, 004H ; 16b WSSbase: 534-FFC

DB 047H, OOIH, 088H, 003H, 0F08, 003H, 008H, 004H; 16b SYNbase: 388-3F8

DB 047H, OOIH, 020H, 002H, 000H, 003H, 020H, 010H; 16b SBbase: 220-300 DB 038H ; End ofDF for Logical Device 0

; LOGICAL DEVICE 1 (Game Port)

DB 015H, OOEH, 063H, OOOH, 001H, OOOH ; EISA ID: CSC0001

DB 082H, 005H, OOOH, 'GAME', OOOH ; ANSI ID DB 03 IH, OOOH ; DF Best Choice

DB 047H, OOIH, OOOH, 002H, OOOH, 002H, 008H, 008H ; 16b GAMEbase: 200

DB 03 IH, OOIH ; DF Acceptable Choice 1

DB 047H, 001 H, 008H, 002H, 008H, 002H, 008H, 008H ; 16b GAMEbase: 208

DB 038H ; End of DF for Logical Device 1

; LOGICAL DEVICE 2 (Control)

DB 015H, OOEH, 063H, OOOH, 010H, OOOH ; EISA ID: CSC0010

DB 082H, 005H, OOOH, 'CTRL', OOOH ; ANSI ID

DB 047H, 001 H, 020H, 001 H, 0F8H, OOFH, 008H, 008H ; 16b CTRLbase: 120-FF8

; LOGICAL DEVICE 3 (MPU-401 ) DB 015H, OOEH, 063H, OOOH, 003H, OOOH ; EISA ID: CSC0003

DB 082H, 004H, OOOH, 'MPU', OOOH ; ANSI ID

DB 031 H, OOOH ; DF Best Choice

DB 022H, OOOH, 002H ; IRQ: 9 Intermpt Select 0

DB 047H, OOIH, 030H, 003H, 030H, 003H, 008H, 002H ; 16b MPUbase: 330

DB 03 IH, OOIH ; DF Acceptable Choice 1

DB 022H, OOOH, 09AH ; IRQ: 9,11,12,15 Intermpt Select 0

DB 047H, OOIH, 030H, 003H, 060H, 003H, 008H, 002H ; 16b MPUbase: 330-360

176 SUBSTTTUTE SHEET (RULE 26) DB 03 IH, 002H ; DF Suboptimal Choice 1

DB 047H, 001H, 030H, 003H, 0E0H, 003H, 008H, 002H ; 16b MPUbase: 330-3EO

DB 038H ; End of DF for Logical Device 3

DB 079H, 09 AH ; End of Resource Data, Resource Size = 280 To facilitate segregation of EEPROM based code shoots among the various pin compatible devices and to promote backward compatibility with host code of other embodiments of codec 100, a 'Family Byte' is defined. The family byte is located in EEPROM Hardware configuration byte 9 and RAM location 0x4004. The EEPROM byte is copied to RAM at powemp. There are two different Family Byte values; one for EEPROM load and one for Code Load.

If the Family Byte in the EEPROM does not match the expected EEPROM value, the EEPROM FIRMWARE RAM patch will be ignored. The resource data, however, will be loaded normally. The EEPROM byte is compared to a stored ROM value for a given ROM release. If the bytes do not match during EEPROM load, the load is terminated at 0x417F, after the resource data. This byte allows the firmware to ignore patch code intended for a different ROM release when the EEPROM has not been updated.

If the Family Byte in RAM does not match the expected code load value during a code load, the RAM firmware will not be overwritten. The BIOS and driver code must write the family byte before updating firmware. The ROM firmware code is written so that the RAM is entered at selected strategic points in the code. The CALLing points, scattered throughout the ROM, call RAM and return if no patches are loaded. Initialization code fills all these called locations with a RET (0x22) instruction. mRAMx macros are used to conveniently call these RAM entry points where 'x' refers to the particular entry point. The following is an example of an mRAMx macro. These macros are placed in the code source to allow RAM based code changes. mRAM2 MACRO

MOV R7, #RAMCOUNT2 ; Token passed to RAM CALL RAM_ENTRY2

177 SUBSTTTUTE SHEET (RULE 26) RAMCOUNT2 SET RAMCOUNT2 +1 ; Add 1 to token

If patches have not been loaded, the mRAMx entry table will contain a 0x22 (microcontroller 103 RET instruction). After a patch is loaded via the EEPROM or Host, the mRAMx entry table will contain jumps to code loaded into the patch RAM. Upon a RESET, SW RESET command, or JUMP_TO_ROM command, the mRAMx entry table will be filled with a RET opcode (0x22) again. The JUMP_TO_ROM command is used before loading RAM via the control port to insure code is not loaded over code that is currently executing from RAM (from a previous load).

The RAM entry point memory map is as follows:

42FF REVISION BYTE

42FE FEATURE BYTE

42FC mRAMl ENTRY

42FA mRAM2 ENTRY

42F8 mRAM3 ENTRY

42F6 mRAM4 ENTRY

42F4 mRAM5 ENTRY

42F2 mRAM6 ENTRY

42F0 mRAM7 ENTRY

42EE mRAM8 ENTRY

42EC mRAM9 ENTRY

4180 - 43E0 PATCH AREA

400C - 417F TOP OF RESOUR

4000 - 400B HARDWARE COT

.φ**φ* **:(^*****:^φ:|^:^*******φ*φ φφ****φφ

In altemate embodiments, the vendor defined registers may be redefined. These registers are accessed only in Plug and Play Configuration State and may be defined as follows:

1) Register 0x28, write only register, write a byte to this register will disable/enable PnP and Crystal keys;

178 SUBSTTTUTE SHEET (RULE 26) Register 0x28 Definition and Access Rules are as follows:

Enter codec 100 into config_state either through PnP cycle or Crystal Key 2;

Write an 0x28 to the ADDRESS port (this ADDRESS port can be either PnP ADDRESS port or the one decided by HWSTRAP and FSYNC); and

Write a byte which has the key disable information (i.e. OxAO presents

PnP key disable, OxBO presents Crystal Key disable, etc.) to the WRITE_DATA port (again, this WRITE_DATA port can be either the PnP WRITE_DATA port or the one assigned by Crystal Key 2). 2) Register 0x29, read-only register, a read to this register will obtain the port ID.

Register 0x29 Definition and Access Rules are as follows:

Put chip into config_state either through PnP cycle or Crystal Key 2; Write an 0x29 to the ADDRESS port (this ADDRESS port can be either PnP ADDRESS port or the one decided by HWSTRAP and FSYNC); and Read the ID byte from READ_DATA port (again, this READ_DATA port can be either the PnP READ_DATA port or the one assigned by Crystal Key 2).

A 7^th intermpt IRQ labelled G is supported. This IRQ which reflects host PC resource, is defined in the high byte of the 19^th byte in resource head data, exclusive of EEPROM length and validation bytes. It is recommended that if this IRQ output is used, it is mapped as IRQ 10. The IRQ mapping defaults to 0 (disabled) for backward compatibility.

Microcontroller 103 intO will not be enabled until after power-on initialization, transferring resource from microcontroller 103 ROM (or EEPROM) to its RAM, and the device be put in PnP wait_for_key state.

Crystal Key 2 will directly put codec 100 into PnP config_state without first being isolated. In this state, the codec 100 will be ready to process any PnP commands as long as they are valid in PnP config_state. After Crystal Key 2 configuration, a wait_for_key reset command is expected to put the device back to normal (wait_for_key) state.

The 0x2090 to 0x400C address translation code for Windows 3.1 driver compatibility is not included in the Firmware ROM. Confrol Port RAM writes with a start address of 0x2090 will not be written to RAM at 0x41C0. RAM writes outside the RAM memory map range.

Control Port RAM data reads or writes to addresses in the range of 0x00 to 0x004? will read or write to the hardware registers in the microcontroller xData space. This read or write of

179 SUBSTTTUTE SHEET (RULE 26) the hardware registers through the Control Port RAM interface is referred to as the 'Back Door' method.

Port PI is set to OxFF (output drivers OFF) after the EEPROM code executes. When port PI is used as an input for the IRQ vector, there will no longer be hardware contention. Whenever the firmware is not holding the ISA bus (via IOCHRDY confrol) it uses

Request Grant to perform SFR codec register access. This is accomplished by two firmware routines: SetREQandWaitForGRANT and ClearREQ. The SetREQandWaitForGRANT routine will Set the REQUEST bit in Port 3 and then poll for the GRANT bit. The routine will return to the caller when the GRANT bit becomes tme. When the GRANT bit is trae, microconfroller is free to access SFR codec registers without fear of ISA bus contention. The ClearREQ routine should be called after all SFR access is complete. It will clear the REQUEST bit in Port 3 allowing ISA bus activity to proceed.

The Suspend/Resume feature is used by host APM code (either driver or BIOS) to obtain the state of microcontroller's intemal RAM and one SFR (special function register), TCON. When the host issues a Suspend command, microconfroller intermpt is interrupted on INTI . The

ISR that runs in this case simply sets a bit (bit 1 of dSuspResmByte) and returns with all microconfroller interrupts disabled. The code returns with microconfroller interrupts disabled so microcontroller state does not change during the suspend processing. When the control returns all the way to the main foreground loop, this bit is checked. If the bit is active, then the intemal RAM is copied into extemal RAM (XRAM). Specifically, intemal RAM location x is copied into XRAM location (4000H + 0B8H - x) where x goes from 008H to 0B8H. The TCON register is copied to XRAM location 40B1H. This, of course, means that the contents of XRAM locations 4000H - 40B IH must be saved before issuing the Suspend command. After the intemal RAM is copied, microcontroller interrupts are restored to their state before the Suspend command and microcontroller processing continues as usual. At this time, the XRAM locations into which the microconfroller copied the intemal RAM, must be restored. Note that there is no microcontroller idling or powering-down "built into" the Suspend command.

The Resume command is the inverse of the Suspend command. Host APM code should use the following steps to restore the intemal state of microconfroller: 1. Save XRAM locations 4000H - 40B1H;

2. Write microconfroller 103 intemal state saved during Suspend to XRAM locations 4000H-40B1H;

180 SUBSTTTUTE SHEET (RULE 26) 3. Issue a Resume command; and

4. Restore XRAM locations 4000H - 40B 1 H with the data saved in 1.

Similar to the suspend case, the ISR that runs in the resume case sets a bit (bit 0 of dSuspResmByte) and retums with all microconfroller 103 interrupts disabled. Microcontroller 103 foreground code then copies the data that the host has already written into XRAM into intemal RAM.

Note that the method described above advantageously relieves microcontroller 103 from having to save/restore its stack since the copying of the state is not done until there is nothing on the stack. In other words, there is nothing on the stack when the suspend and resume flags (set in the respective ISR's) are checked.

FIGURE 89 is a diagram of the bitfields of Global Configuration Byte 2 at EEPROM Byte 16, (default= 00000000). This byte is a reserved byte in the preferred embodiment. The entire byte is copied to 0x400B on powerup and to XI 8. The bitfields are defined as follows:

AUX1R - AUXl Remap - Switches control of the AUXl volume control registers from 12 13 to 118 119 when set = 1;

3 DEN - When this bit is set to 1, the 3D Audio is enabled and will process any stereo signal output from the Output Mixer;

DSSEL1 - This bit selects the source of digital data for the Delta Sigma DAC (DAC 1).

DSSEL1 = 0 for playback FIFO, DSSEL1 = 1 for accelerator 139 DSP serial interface; ZVEN - ZV port Enable - This bit select enables the ZV Port interface. ZVEN = 0 for disabled, ZVEN = 1 for enabled. When ZVEN = 1, then the extemal wavetable Firmware input into DAC2 is disabled; and

Reserved - These bits are reserved for future use and should be set to zero.

FIGURE 90 is a diagram of the bitfields of DMA C,IRQ G select at EEPROM Byte. This byte in the preferred embodiment was only the DMA C select byte. In the altemate embodiments, this byte additionally defines the IRQ G mapping to PC IRQ number. This byte is copied to 0x4012 on powerup. The bitfields are defined as:

DMAC[3..0] - DMA C select - This value determines which HOST PC DMA number the hardware pins for this DMA channel are connected to; and IRQG[3..0] - IRQ G select - This value determines which HOST PC IRQ number the hardware pins for this IRQ channel are connected to.

The EEPROM TIMING in the altemate embodiments conforms to the following:

181 SUBSTTTUTE SHEET (RULE 26) Symbol Min (time in uS)

tHD:STA 4.0 tLSCL 4.7 tHSCL 4.0 tSU:STA 4.7 tHD:DAT 0 tSU:DAT 0.250 tSU:STO 4.7

]

Although the invention has been described with reference to a specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the tme scope of the invention.

182 SUBSTTTUTE SHEET (RULE 26) TABLE 1

TABLE 2

TABLE 3

MODE OPERATION INPUT INTERRUPT BITFIELDS

Sound Context ΓΝTI X I 1 o o o o x System Switch Write

Context X I 1 o o o 1 x

Switch Read

Reserved X 1 0 0 1 0 X

Reserved X I 0 0 1 1 X

Reserved X 1 0 1 0 0 X

Reserved X 1 0 1 0 1 X

Reserved X 1 0 1 1 0 X

Reserved X 1 0 1 1 1 X

Sound Config Write X 1 1 0 0 0 X Blaster

Reserved X 1 1 0 0 1 X Program RAM X 1 1 0 1 0 X Write

Program RAM X 1 1 1 0 1 1 X Read

Program RAM X 1 1 1 1 0 0 X End

Reserved X 1 1 1 1 0 1 X DMA Write X 1 1 1 1 1 0 X Reserved X 1 1 1 1 1 1 X

Sound Interrupt occurs TRO 0 0 0 0 0 0 0 0

Blaster on a write of the 0 0 0 0 0 0 1 0

ADPCM ADPCM data latch.

Plug & Play Address Port INTO Described below 0x0279 TABLE 4

TABLE 5

186 SUBST.TUTE SHEET <*M »

TABLE 6

TABLE 7

TABLE 8

Offset Field Name

Byte O Value = 00001010B (Type=0, small item name=0xl, length =2)

Byte l Plug and Play version number (in packed BCD format, major bits[7:4], minor bits[3:01 Example: Version 1.0 = 0x10, Version 2.3 = 0x23

Byte 2 Vendor specific version number

26

TABLE 11

TABLE 12

TABLE 13

TABLE 14

Offset Field Name

Byte O Value = 001 lOOOxB (Type=0, small item name=0x6, length=(0 or 1))

TABLE 15

Value Definition

Good configuration - Highest Priority and preferred configuration

Acceptable configuration - Lower Priority but acceptable configuration

Sub-optimal configuration - Functional configuration but not optimal

3 - 255 Reserved

TABLE 16

Offset Field Name

Byte O Value = 00111000B (Type=0, small item name=0x7, length=0)

SUBSTITUTE SHEET (RULE 26) TABLE 17

TABLE 18

TABLE 19

TABLE 20

SUBSTITUTE SHEET (RULE 26) TABLE 21

TABLE 22

TABLE23

_SUBST,TUT_E SHEETBOL 2S) TABLE 24

TABLE 25

TABLE 26

TABLE 27

TABLE 28

AMM[7:01 Model Decode = number of consecutive bytes

1111111 256 bytes, address bits A[7..0] are don't cares.

01 11111 128 bytes, address bit A7 is decoded. Bits A[6..Q] are don't cares.

0011111 64 bytes, address bits A7 and A6 are decoded. Bits A[5..Q] are don't cares.

0001111 32 bytes, address bits A[7.,5] are decoded. Address bits A[4..0] are don't cares.

0000111 16 bytes, address bits A[7..4] are decoded. Address bits A[3..Q1 are don't cares.

0000011 8 bytes, address bits A[7.,3] are decoded. Address bits A[2..Q1 are don't cares.

0000001 4 bytes, address bits A[7..2] are decoded. Address bits A[1..Q] are don't cares.

0000000 2 bytes, address bits A[7..1] are decoded. Address bits A[0] is a don't care.

00000000 1 byte, address bits A[7..Q] are decoded.

TABLE 29

TABLE 30

TABLE 31

NOTE: If either WTEN or SPS are set to a one then the XBUF bit in CDROM

Interface Control Register at microcontroller address 0x34 is forced to a one.

TABI -E 32

RES RES RES RES RES RES RES RES

RESERVED LOCATION AT 0 X 41

res Reserved for future use. Always read back as zero's;

TABLE 33

TABLE 34

TABLE 35

D7 D6 D5 D4 D3 D2 Dl DO

LINE IN LINE IN AUXl AUXl AUX2 AUX2 RES RES

Source Device Source Device Source Device Reserved

00 = Line 00 = Line 00 = Line

01 = FM Synth 01 = FM Synth 01 = FM Synth

10 = CD 10 = CD 10 = CD

11 = Other 11 = Other 11 = Other

TABLE 39

TABLE 36

TABLE 40

D7 D6 D5 D4 D3 D2 Dl DO

Reserved Codec 100 DRQC, DACKC Pins

,„ 0000 = DMA Channel 0

0001 = DMA Channel 1

0010 = DMA Channel 2

0011 = DMA Channel 3

0100:1111 = No Connection

^19S SUBST.TUTE SHEET BO 26) TABLE 37

TABLE 42

199 26) _iUBST.TUTE SHEET IBUUE TABLE 38

TABLE 44

201 _SUBSTlTtfTE SHEET JW*» TABLE 43

AMM[7:0] Modem Decode = number of consecutive bytes

11111111 256 bytes, address bits A[7..0] are don't cares.

01111111 128 bytes, address bit A7 is decoded. Bits A[6..Q] are don't cares.

00111111 64 bytes, address bits A7 and A6 are decoded. Bits A[5..Q] are don't cares.

00011111 32 bytes, address bits A[7..5] are decoded. Address bits A[4..0] are don't cares.

00001111 16 bytes, address bits A[7..4] are decoded. Address bits A[3..0] are don't cares.

00000111 8 bytes, address bits A[7..3] are decoded. Address bits A[2..Q] are don't cares.

00000011 4 bytes, address bits A[7.,2] are decoded. Address bits A[1..Q] are don't cares.

00000001 2 bytes, address bits A[7,.l] are decoded. Address bits A[0] is a don't care.

00000000 1 byte, address bits A[7..Q] are decoded.

TABLE 45

203 _SUBSTtTUTE SHEET (RULE 26, TABLE 46

TABLE 47A

TABLE 47B

TABLE 47C

TABLE 47D

206 _SUBSTTTOTE SHEET imn-E 26) TABLE 48A

TABLE 49A

SPC3 SPC2 SCPl SCP0 LEVEL

0 0 0 0 0 OdB

1 0 0 0 1 -1.5dB

2 0 0 1 0 -3.OdB

3 0 0 1 1 -4.5dB

4 0 1 0 0 -6.0dB

5 0 1 0 1 -7.5dB

6 0 1 1 0 -9.0dB

7 0 1 1 1 -10.5dB

8 0 0 0 -12.0dB

9 0 0 1 -13.5dB

10 0 1 0 -15.0dB

11 0 1 1 -16.5dB

12 1 0 0 -18.0dB

13 1 0 1 -19.5dB

14 1 1 0 -21. OdB

15 1 1 1 -22.5dB TABLE 48B

Indirect Re isters: CIO - CI255

Note: CI55-CI63 are only accessible in Test Mode 9 or Test Mode 10. TABLE 49B

When the SRS/MONO bit is set to a one this register is reset to 00100000.

TABLE 50

TABLE 51

SPS 0

Pin l XD7 - Bi-directional WTEN Defined

Pin 2 XD6 - Bi-directional WTEN Defined

Pin 3 XD5 - Bi-directional WTEN Defined

Pin 4 XD4 - Bi-directional FSYNC - Output

Pin 5 XD3 - Bi-directional SDOUT - Output

Pin 6 XD2 - Bi-directional SDIN - Input

Pin 7 XDl - Bi-directional SCLK - Output

Pin 8 XDO - Bi-directional XDO - Bi-directional

TABLE 54

Pushing the Up button or the Down button will NOT un-mute Codec 204 if it was muted.

SUBSTITUTE SHEET (RULE 26)

TABLE 55

Pushing the Up button or the Down button will un-mute the Codec if it was muted.

S"BSτm,T_E SH_EET(_RϋLE TABLE 53

TABLE 56

TABLE 57

Up Button Push (Mute pin) +2dB volume increase

Up Button Hold (Mute pin) +2dB volume increase every 500ms (approx.)

Down Button Push -2dB volume decrease

Down Button Hold -2dB volume decrease every 500ms (approx.)

Up and Down Button Push Toggles Mute on or off

UP and Down Button Hold No affect

SUBSTITUTE SHEET (RULE 26) TABLE 58

FMT FMT C/L Audio Data Format tD7 0 D5

D6

0 0 0 Linear, 8-bit unsigned

0 0 1 u-law, 8-bit commanded

0 1 0 Linear, 16-bit two's complement, Little Endian

0 1 1 A-law, 8-bit commanded

1 0 0 RESERVED

1 0 1 ADPCM, 4-bit, IMA compatible

1 1 0 Linear, 16-bit two's complement, Big Endian

1 1 1 RESERVED tFMTl is not available in MODE 1 (forced to 0)

TABLE 59

TABLE 60

TABLE 61

21*-

TABLE 62

217 SUBSTtTUTE SHEET (RULE 26)

TABLE 63A

TABLE 64

TABLE 66

TABLE 65

to c

CD cn

H H C H t m cn x m m

H

m t σ>

cn c

00 cn

H

H |N

C (j H m cn x m m

3 c r m

NJ

TABLE 67

cn c

CD n c H m cn x

m m

H c r m t σ>

TABLE 68

CSEL5 CSEL4 CSEL3 CSEL2 CSEL1 CSELO

TABLE 70.

When a slot is set to the rhythm mode, set KEY ON of slots 13 to 18 to zero.

TABLE 71

TABLE 72

TABLE 73

TABLE 74

TABLE 75A

TABLE 75B

CNT3 CNT2 CNT1 CNT0 LEVEL

0 0 0 0 0 OdB

1 0 0 0 1 -1.5dB

2 0 0 1 0 -3. OdB

3 ..0 0 1 1 -4.5dB

4 0 1 0 0 -6.0dB

5 0 1 0 1 -7.5dB

6 0 1 1 0 -9.0dB

7 0 1 1 1 -10.5dB

8 0 0 0 -12.0dB

9 0 0 1 -13.5dB

10 0 1 0 -15.0dB

11 0 1 1 -16.5dB

12 1 0 0 -18.0dB

13 1 0 1 -19.5dB

14 1 1 0 -21. OdB

15 1 1 1 -22.5dB

TABLE 76

TABLE 77

TABLE 82

²²⁵ _eLlppT (RV3LE 26

SUBSTITUTE SHEET (H TABLE 78

TABLE 79

²²⁷ <=ueeτ(*^υl£26. TABLE 81

TABLE 83

SUBSTITUTE SHEET (RULE 26; TABLE 84

TABLE 85

TABLE 86

Where PIN = Interrupt pin, A,B,C,D,E,F,G.

229 SHEET ( υv-ε 26

TABLE 87

TABLE 89A

TABLE 93A

TABLE 93B

TABLE 94

TABLE 95

TABLE 96

TABLE 97

TABLE 98

Claims

WHAT IS CLAIMED IS:

1. A single-chip audio system comprising: a bus interface; digital to analog converters for converting digital audio data received through said bus to analog signals; an analog mixer for mixing signals received from said digital to analog converters with an analog signal received from an external source; and analog spacial enhancement circuitry for enhancing first and second mixed analog signals output from said analog mixer.

2. The system of Claim 1 wherein said digital to analog converters comprise: first selectable digital to analog converters for selectably converting higher sound quality digital signals; and second selectable digital to analog converters for selectively converting lower sound quality digital signals.

3. The system of Claim 2 wherein said higher quality sound digital signals are received through said bus interface.

4. The audio system of Claim 3 wherein said bus interface intrefaces with an ISA.

5. The system of Claim 2 wherein said lower quality sound digital signals are received by said second digital to analog converters from an on chip FM synthesizer.

6. The system of Claim 2 wherein said lower quality sound digital signals are received by said second digital to analog converters from an external wavetable device.

7. The system of Claim 1 wherein said analog spatial enhancement circuitry comprises: a difference amplifier for generating a difference signal from said first and second signals output from said mixer;

233 SUBSTTTUTE SHEET (RULE 26) a filter for generating an acoustic crosstalk compensation signal from said difference signal; an inverter for inverting said compensation signal; a first summer for summing said inverted compensation signal with said first signal; and a second summer for summing said compensation signal with said second signal.

8. The system of Claim 1 and further comprising: mute controls for muting said signals received said mixer; and circuitry for idling said digital to analog converters when said muting controls are asserted.

9. The system of Claim 8 and further comprising circuitry for idling said mixer when said mute controls are asserted.

10. Audio spatial enhancement circuitry comprising: circuitry for generating a difference signal from left and right channel analog data streams; circuitry for generating an acoustic crosstalk compensation signal; circuitry for summing said left channel data stream with said compensation signal; and circuitry for summing said right channel data stream with an inverted said compensation signal.

11. The audio spatial enhancement circuitry of Claim 10 wherein said circuitry for generating a compensation signal comprises a filter. . .

12. The audio spatial enhancement circuitry of Claim 11 wherein said filter comprises a notch filter.

13. The audio spatial enhancement circuitry of Claim 11 wherein said filter comprises an active filter.

234 SUBSTTTUTE SHEET (RULE 26)

14. The audio spatial enhancement circuitry of Claim 10 wherein said circuitry for generating a difference signal comprises a difference amplifier.

15. The audio spatial enhancement circuitry of Claim 10 wherein said circuitry for summing said left channel data stream with said compensation signal comprises an analog summer.

16. The audio spatial enhancement circuitry of Claim 15 wherein said analog summer has a gain of one-half.

17. The audio spatial enhancement circuitry of Claim 10 wherein said circuitry for summing said right channel data stream and said inverted compensation signal comprises an analog summer and an analog inverter.

18. The audio spatial enhancement circuitry of Claim 17 wherein said analog summer has a gain of one.

19. An audio system comprising: digital to analog converters having left and right paths for converting received left and right streams of audio data; a plurality of analog data ports for receiving left and right channel streams of audio data; a mixer having left and right paths for selectively mixing respective left and right channel data passed from said converters and left and right channel data passed from said ports; muting circuitry for selectively muting said right and left channel data to passed to said mixer from said converters; and circuitry for idling a selected one of said left and right paths of said mixer when selected data passed to said mixer is muted.

20. The system of Claim 19 wherein said left path of said mixer is idled when selected left channel data passed to said mixer is muted.

21. The system of Claim 19 wherein a selected left channel data port is idled when selected left channel data passed to said mixer is muted.

235 SUBSTTTUTE SHEET (RULE 26)

22. The system of Claim 19 wherein said left path of said converters is idled when selected left channel data passed to said mixer is muted.

23. The system of Claim 19 wherein said right path of said mixer is idled when selected right channel data passed to said mixer is muted.

24. The system of Claim 19 wherein a selected right channel data port is idled when selected right channel data passed to said mixer is muted.

25. The system of Claim 19 wherein said right path of said converters is idled when selected right channel data passed to said mixer is muted.

26. Amplitude control circuitry comprising: a first register for storing received amplitude control data; a second register for storing amplitude control data transferred from said first register; output circuitry for controlling the amplitude of a received signal in response to amplitude data transferred from said second register; a sensor for determining when data stored in said first and second registers does not match; and a comparator enabled by said sensor when said data in said first and second registers does not match, said comparator comparing a signal output from said output circuitry with a reference signal, and generating a signal for enabling the transfer of data from said first register to said second register when said signal output from said output circuitry falls within a window defined by said reference voltage.

27. The circuitry of Claim 26 wherein said received signal comprises an analog audio signal.

236 SUBSTTTUTE SHEET (RULE 26)

28. The circuitry of Claim wherein said output circuitry comprises: a decoder for decoding amplitude control data from said second register; and an attenuator for attenuating said received signal in response to an output of the decoder.

29. The circuitry of Claim 28 wherein said decoder comprises a plurality of resistor taps and said decoder selects a selected one of said taps to provide selected attenuation to said received signal.

30. The circuitry of Claim 28 wherein said output circuitry further comprises an operational amplifier for driving signals output from said output circuitry.

31. The circuitry of Claim 28 and further comprising a timer, said timer enabling the transfer of data from said first to said second register a preselected number of clock cycles after said sensor detects a mismatch between the contents of the first register and the contents of the second register.

32. An audio system comprising: circuitry for generating an audio data stream; circuitry for generating digital words defining a volume control level; and volume control circuitry for controlling the amplitude of said audio data stream in response to said digital words comprising: a master register for holding digital words received from said circuitry for generating; a slave register for holding digital words selectively transferred from said master register in response to an enable signal; output control circuitry for receiving said audio data stream and applying a preselected gain defined by a said digital word held in said slave register; and circuitry for generating said enable signal when a said digital word held in said master register changes and said audio data stream output from said output control circuitry reaches a zero-crossing.

237 SUBSTTTUTE SHEET (RULE 26)

33. The audio system of Claim 32 wherein said output control circuitry applies a positive gain.

34. The audio system of Claim 32 wherein said output control circuitry applies a negative gain.

35. The audio system of Claim 32 wherein said output control circuitry comprises: a decoder for decoding a said digital word stored in said slave register; and gain control circuitry for receiving said audio data stream at a first volume level and outputing said audio at a second volume level in responses to an output of the decoder.

36. The audio system of Claim 35 wherein said gain control circuitry comprises an attenuator.

37. The audio system of Claim 32 wherein said circuitry for generating digital data words and said volume control circuitry are disposed on a single integrated circuit chip.

38. The audio system of Claim 32 wherein said circuitry for generating an enable signal comprises: a sensor for determining when first data stored in said master register does not match second data stored in said slave register; and a comparator for comparing said stream output from said output circuitry against a predetermined reference when said first and second data do not match.

39. An audio system disposed on a single chip: an output mixer having inputs for receiving first digital audio data of a first bitwidth from a first digital to analog converter, second digital audio data of a second bitwidth from a second digital to analog converter, and analog data from an external source; an output port for driving an analog signal output from said output mixer; an input mixer having inputs for receiving analog data from a plurality of sources; analog to digital converters for converting an analog output of said input mixer into digital data; and an input path for transmitting said digital data output from said analog to digital converters to an external digital bus.

238 SUBSTTTUTE SHEET (RULE 26)

40. The audio system of Claim 39 wherein said first digital audio data is input to said first digital to analog converter from said external bus.

41. The audio system of Claim 39 and further comprising an FM synthesizer, said synthesizer outputing data to an input of said second digital to analog converter.

42. The audio system of Claim 39 wherein an input to said second digital to analog converter receives data from an external wavetable generator.

43. The audio system of Claim 39 wherein an input to said second digital to analog converter receives a signal comprising mixed wavetable and FM synthesizer data.

44. The audio system of Claim 39 wherein said first bitwidth equals said second bitwidth.

45. The audio system of Claim 39 wherein said first bitwidth is greater than said second bitwidth.

46. The audio system of Claim 39 wherein an input of said first analog to digital converter receives data from an external audio accelerator.

47. A single chip audio system comprising: a microcontroller for performing system control operations; a digital to analog converter for converting data selectively received from a bus interface and an accelerator interface; a mixer for mixing an analog signal output from said digital to analog converter with an analog signal received from a second source; circuitry for idling said mixer when selected signals input to said mixer are muted; and analog spatial enhancement circuitry for spatially enhancing analog audio data coupled from said mixer operable to: generate a difference signal from first and second signals output from said mixer; generate an acoustic crosstalk compensation signal from said difference signal; invert said compensation signal;

239 SUBSTTTUTE SHEET (RULE 26) sum said inverted compensation signal with said first signal; and sum said compensation signal with said second signal.

48. The audio system of Claim 47 wherein said accelerator interface is a serial interface.

49. The audio system of Claim 47 and further comprising a digital signal processor for selectively performing digital processing operations on digital data being input to said digital to analog converters.

50. The audio system of Claim 47 wherein said bus interface includes a PNP interface.

51. The audio system of Claim 49 wherein said digital signal processor performs SRS audio processing functions.

52. Oscillator start-up circuitry comprising: a crystal oscillator having buffered and unbuffered outputs; a hysteresis buffer for generating a output signal when an unbuffered clock signal output from said unbuffered output falls within a preselected voltage range; and clock-off detection circuitry for monitoring said output signal from said hysteresis buffer and controlling output of a buffered clock presented at said buffered output in response.

53. The circuitry of Claim 52 wherein said hysteresis buffer has a center point selected to match a DC bias point of said crystal oscillator.

54. The circuitry of Claim 52 wherein said clock-off generation circuitry senses a change in logic state of said output signal from said buffer within a time-out period and generates a clock-on signal in response.

55. The circuitry of Claim 54 wherein output of said buffered clock is enabled on a first rising edge of said buffered clock after said clock-on signal is asserted.

56. The circuitry of Claim 52 wherein said clock-off generation enables output of said buffered clock when said unbuffered clock has a large magnitude swing.

241 SUBSTTTUTE SHEET (RULE 26)