WO1999018752A1

WO1999018752A1 - System and method for telecommunications bus control

Info

Publication number: WO1999018752A1
Application number: PCT/US1998/019933
Authority: WO
Inventors: Robert Scott Gammenthaler, Jr.; Bracey James Blackburn; Donald Barton Hay; Thomas Edward Cooper; Serge Francois Fourcand; Long Van Vo
Original assignee: Alcatel Usa Sourcing, L.P.
Priority date: 1997-10-02
Filing date: 1998-09-23
Publication date: 1999-04-15
Also published as: TW413989B; AU9505098A

Abstract

A system for controlling a data bus is provided. The system includes a datagram receiver that receives datagrams in parallel. A datagram storage device connected to the datagram receiver stores the datagrams. A datagram transmitter connected to the datagram storage device receives stored datagrams from the datagram storage device and transmits the datagrams over an egress bus.

Description

SYSTEM AND METHOD FOR TELECOMMUNICATIONS BUS CONTROL

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to telecommunications data switching and more particularly to a system and apparatus for controlling telecommunications buses.

BACKGROUND OF THE INVENTION

Modern telecommunications system typically utilize digitally encoded data instead of analog data. If analog data is used, it is converted to digital data for the purposes of switching the data between conducting media. Switching of data occurs at large telecommunications switches, which may receive and process hundreds or thousands of data channels. In the process of being switched, two or more individual data streams may be combined to form a single data stream. When two or more data streams are combined, the total amount of data being transmitted, or bandwidth, of the combined data stream equals the sum of the bandwidths of each of the individual data streams. Accurate control is required when combining the two or more individual data streams into a single data stream in order to prevent corruption of data on the data bus.

Although it is common to combine two or more data streams into a single data stream with equal bandwidth, it is not unusual for data transmission errors to be created when such combinations are created. Such errors prevent additional data processing from being performed on the two or more data streams while they are being combined, as the additional data processing would make such errors difficult or impossible to detect.

SUMMARY OF THE INVENTION

Therefore, a need has arisen for a system and method for combining two or more data streams that allows additional data processing to be performed on the two or more data streams while they are being combined.

In accordance with the present invention, a system and method for data bus control is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed systems and methods for combining data streams.

One aspect of the present invention is a system for combining data streams that comprises a system for controlling a data bus. The system includes a datagram receiver that receives datagrams in parallel. A datagram storage device connected to the datagram receiver stores the datagrams. A datagram transmitter connected to the datagram storage device receives stored datagrams from the datagram storage device and transmits the datagrams over an egress bus.

The present invention provides many important technical advantages. One important technical advantage of the present invention is a system for combining data streams that selects individual datagrams for storage and retransmission from a plurality of ingress buses based upon datagram addresses. Changes to the sequence in which datagrams are stored and retransmitted may be easily made by changing the corresponding address.

Another important technical advantage of the present invention is a method for controlling a data bus that includes transmitting stored asynchronous transfer mode datagrams from buffers over an egress bus in response to enable signals from application circuits. This method allows synchronous transfer mode data to be controllably transmitted with asynchronous transfer mode data over the same bus.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

FIGURE 1 is a system block diagram of a fiber optic termination module for a telecommunications switch embodying concepts of the present invention;

FIGURE 2 is a block diagram of interconnections between application circuits and bus control circuits embodying the concepts of the present invention; FIGURE 3 is a block diagram of typical connections between application circuits and bus control circuits embodying concepts of the present invention;

FIGURE 4 is a block diagram of connections between components of a bus control circuit embodying concepts of the present invention; FIGURE 5 is a functional block diagram of a bus control circuit embodying concepts of the present invention;

FIGURE 6 is a block diagram showing the connections between link buffer circuits, the header buffer, and the egress frame multiplexer first stage and second stage in accordance with teachings of the present invention;

FIGURE 7 is a diagram of an ingress bus frame format embodying concepts of the present invention; FIGURE 8 is a diagram of an egress bus frame format embodying concepts of the present invention;

FIGURE 9 is a diagram of an egress bus slot stuffing format embodying concepts of the present invention.

FIGURE 10 is a diagram of an egress slot address map embodying concepts of the present invention.

FIGURE 11 is a flow chart of a method for controlling telecommunications buses in accordance with concepts of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention are illustrated in the figures, like numbers being used to refer to like and corresponding parts of the various drawings . FIGURE 1 is a block diagram of optical fiber-capable telecommunications switch system 10 embodying concepts of the present invention. In particular, the data bus interface of the present invention is a modular system designed for incorporation into individual telecommunications components, such as the individual components of telecommunications switch system 10. The data bus interface of the present invention may also or alternatively be used in other telecommunications components that interface to data buses.

Optical fiber-capable telecommunications switch system 10 includes switch 12 connected to fiber optic connection unit (OPTICAL TERMINATOR) 14 and common controller 16. Optical telecommunications data streams, such as one or more streams of bit-serial data, byte-serial data, or serial frames of data, are received over one or more fiber optic conductors 18 at fiber optic connection unit 14. These telecommunications data streams are converted to electrical signals by fiber optic connection unit 14 and are transmitted to switch 12 for switching between data channels. Switch 12 may switch data channels of any suitable size, such as DSO, DS1, DS3, or other suitable channels. Furthermore, any stream of data may comprise one or more channels of data having a suitable format, such as DSO, DS1, DS3, or other suitable channels. Common controller 16 receives control data from and transmits control data to fiber optic connection unit 14 and switch 12.

Switch 12 is a telecommunications switch having M input channels and N output channels, where M and N are integers. Switch 12 receives telecommunications data at any of the M input channels and transfers the telecommunications data to any of the N output channels. Switch 12, as shown in FIGURE 1, is a digital switch, but may also be an analog switch. Switch 12 may include, for example, a Megahub 600E Digital Telecommunications Switch manufactured by DSC Communications Corporation of Piano, Texas. Switch 12 includes a message transport node 20 coupled to a matrix data multiplexer circuit (MDM) 22, a matrix control path verification processor (PVP) 24, a line trunk manager circuit (LTM) 26, administration circuit

(ADMIN) 28, timing generator circuit (TG) 30, and Ethernet network circuit (ENC) 32.

Matrix data multiplexer circuit 22 is further coupled to matrix control path verification processor 24 and timing generator circuit 30. Matrix data multiplexer circuit 22 is an interface circuit that may be used for coupling data channels between fiber optic connection unit 14 and the switching matrix (not explicitly shown) of switch 12. In particular, matrix data multiplexer circuit 22 provides the interface for DSO data. Matrix data multiplexer circuit 22 receives 2048 channels of DSO data from fiber optic connection unit 14 on a 10-bit parallel data channel operating at a frequency of 16.384 MHZ. These DSO data channels are then transmitted to the M input ports of the switching matrix of switch 12.

Control commands received at switch 12 from common controller 16 are used to determine the proper connections between the M input ports and the N output ports of the switching matrix. The DSO data channels are transmitted through the switching matrix after the connections have been formed. The DSO data channels received at matrix data multiplexer circuit 22 from the N output ports of the switching matrix are then transmitted back to fiber optic connection unit 14.

Matrix control path verification processor 24 is coupled to fiber optic connection unit 14 and to message transport node 20. Matrix control path verification processor 24 is a switching matrix administration and control component that processes matrix channel low level fault detection and fault isolation data.

Line trunk manager circuit 26 is coupled to fiber optic connection unit 14 and message transport node 20. Line trunk manager circuit 26 is a switching matrix control component that receives and transmits data relating to call processing functions for fiber optic connection unit 14.

Timing generator circuit 30 is coupled to matrix data multiplexer circuit 22 and common controller 16. Timing generator circuit 30 is a switch timing circuit that receives timing data from an external source, such as fiber optic connection unit 14, and transmits the timing data to components of switch 12.

Ethernet network circuit 32 is coupled to message transport node 20 and common controller 16. Ethernet network circuit 32 is a data communications interface, and transfers data between message transport node 20 and common controller 16.

Fiber optic connection unit 14 includes an optical interface circuit (OTM) 40, STSM circuits (STSM) 42, a bus control circuit (BCM) 44, a matrix interface circuit (MTXI) 46, a tone recognition circuit (TONE) 48, and a high speed line trunk processor circuit (LTP) 50. Fiber optic connection unit 14 receives digitally encoded optical data from fiber optic conductor 18, performs broadcast switching of the data streams received from fiber optic conductor 18, transmits synchronous transfer mode (STM) telecommunication data to matrix data multiplexer circuit 22 and matrix control path verification processor 24 for switching through the switching matrix of switch 12, and receives the switched telecommunications data from switch 12 for transmission over fiber optic conductor 18.

Optical interface circuit 40 is capable of terminating optical signals, for example OC-3, that are connected to the public switched network (PSN) . Optical interface circuit 40 receives digitally encoded optical telecommunications data from fiber optic conductor 18 and converts the optical signals into electrical signals, for example digital signals having an STS-l-P data format, for transmission to other components of fiber optic connection unit 14. Optical interface circuit 40 is coupled to fiber optic conductor 18 and to STSM circuits 42.

Optical interface circuit 40 may comprise a single circuit card that has plug-in connectors (not explicitly shown) to allow the card to be easily installed in a cabinet containing other component circuit cards of fiber optic connection unit 14. Alternatively, optical interface circuit 40 may comprise two or more circuit cards, or one or more discrete components on a circuit card. Application circuits are generally any telecommunications data transmission system components that are coupled to bus control circuit 44. Each application circuit may comprise a single circuit card with plug-in connectors (not explicitly shown) in order to be easily installed in a rack containing fiber optic connection unit 14. Alternatively, each application circuits may comprise multiple circuit cards, or individual components on a single circuit card.

As shown in FIGURE 1, STSM circuits 42 are configured to receive data from and transmit data to optical interface circuit 40. This data may comprise synchronous transfer mode telecommunications data. For example, STSM circuits 42 may receive a single STS-l-P channel of data that includes payload data comprising 672 DSO data channels, where each DSO data channel is a continuous stream of data equal to 64,000 bits per second. The STS-l-P data format also includes administration, control, and routing data that may be included in a commercially standard STS-1 data format, plus additional proprietary administration, control, and routing data. The administration data, control data, and routing data is used to separate the individual DSO data channels within the STS-l-P data channel, perform path verification, perform equipment diagnostic monitoring, and other suitable functions.

STSM circuits 42 may also receive asynchronous transfer mode (ATM) telecommunications data, such as data transmitted as iMPAX packet layer datagrams or other suitable data formats. An iMPAX packet layer datagram is a proprietary 512-bit data format that includes 4 bits of payload type identification data, a 76-bit header section, a 424-bit payload section, and an 8-bit control record check section. Asynchronous transfer mode data may be transmitted as a single stream of fixed bit format data frames that comprise additional streams of data. The number of data frames transmitted per second for a given data stream may be varied for asynchronous transfer mode data in order to accommodate fluctuations in the amount of data per stream and the number of data streams transferred.

Bus control circuit 44 may be coupled to a number of other application circuits with suitable functions, such as matrix interface circuit 46, tone recognition circuit 48, and high speed line trunk processor circuit 50. All application circuits transmit data to bus control circuit 44 over ingress buses 60 and receive data from bus control circuit 44 over egress buses 62. These application circuits may also comprise a modular bus interface circuit (not explicitly shown) . The modular bus interface circuit receives data from the application circuit and converts it into a predetermined format for transmission over ingress bus 60. The modular bus interface circuit also receives data in a predetermined format over egress bus 62 and converts it into a format that is useable by the application circuit associated with the bus interface circuit.

Bus control circuit 44 receives telecommunications data in a predetermined format from application circuits over ingress buses 60, multiplexes the data into a single broadcast data stream in a predetermined format, and transmits the broadcast data stream over egress buses 62. In this manner, bus control circuit 44 also operates as a broadcast switching device. Each application circuit receives the broadcast data stream containing data from other application circuits, and can process selected data in a suitable manner. For example, STSM circuit 42 may transmit the data back to optical interface circuit 40 for transmission on fiber optic conductor 18 to the network. Bus control circuit 44 may comprise a single circuit card with plug-in connectors (not explicitly shown) in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, bus control circuit 44 may comprise multiple circuit cards, or individual components on a single circuit card. Matrix interface circuit 46 provides the protocol and transport format conversion between fiber optic connection unit 14 and switch 12. Matrix interface circuit 46 is an application circuit that selects desired data channels from the broadcast data stream transmitted by bus control circuit 44, and reformats and transmits the data to switch 12. Matrix interface circuit 46 is coupled to bus control circuit 44, matrix data multiplexer circuit 22, and matrix control path verification processor 24. Matrix interface circuit 46 converts the data format of the broadcast data stream received from bus control circuit 44 and switch 12 into a data format that is compatible with switch 12 and bus control circuit 44, respectively. Matrix interface circuit 46 may comprise a single circuit card with plug-in connectors (not explicitly shown) in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, matrix interface circuit 46 may comprise multiple circuit cards, or individual components on a single circuit card. Tone recognition circuit 48 is an application circuit that is coupled to bus control circuit 44 and performs tone recognition functions for fiber optic connection unit 14. One pair of tone recognition circuits 48 may be required for every 2016 matrix ports of switch 12. Tone recognition circuit 48 interfaces with the broadcast data stream and detects data representative of keypad tones on each DSO channel that comprises the broadcast data stream, up to the maximum of 2016 DSO data channels.

Tone recognition circuit 48 has an array of digital signal processor devices (not explicitly shown) that can be configured to provide tone detection and generation. Tone recognition circuit 48 may comprise a single circuit card with plug-in connectors (not explicitly shown) in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, tone recognition circuit 48 may comprise multiple circuit cards, or individual components on a single circuit card.

High speed line trunk processor circuit 50 is the primary shelf controller for all of the circuit cards in fiber optic connection unit 14 and provides the interface between fiber optic connection unit 14 and switch 12. High speed line trunk processor circuit 50 contains a microprocessor and a communications interface to line trunk manager circuit 26.

High speed line trunk processor circuit 50 may comprise a single circuit card with plug-in connectors (not explicitly shown) in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, high speed line trunk processor circuit 50 may comprise multiple circuit cards, or individual components on a single circuit card.

Ingress buses 60 are data buses that carry a data stream with a predetermined bit structure and a predetermined frequency from an application circuit to bus control circuit 44. For example, each ingress bus 60 may comprise a data stream with 8 parallel bits operating at a frequency of 25.92 MHZ. Other bit structures and frequencies may be used where suitable.

Egress buses 62 are data buses that carry a data stream with a predetermined bit structure and a predetermined frequency to an application circuit from bus control circuit 44. For example, each egress bus 62 may comprise a data stream with 16 parallel bits operating at a frequency of 51.84 MHZ. Other bit structures and frequencies may be used where suitable.

Common controller 16 is coupled to switch 12 and fiber optic connection unit 14. Common controller 16 is a processor that receives administration, control, and routing data from switch 12 and fiber optic connection unit 14, and generates administration, control and routing data that coordinates the operation of switch 12 and fiber optic connection unit 14. Common controller 16 may alternatively be incorporated within switch 12 or fiber optic connection unit 14.

In operation, telecommunications data from the network is transmitted via fiber optic conductor 18 and received by fiber optic connection unit 14. This telecommunications data is then converted into electrical signals, such as 672 DSO data channels, and is transmitted from optical interface circuit 40 through STSM circuit 42 and to bus control circuit 44 over ingress bus 60. Bus control circuit 44 multiplexes the data received from each application circuit into a single broadcast data stream and transmits the broadcast data stream over each egress bus 62.

The broadcast data stream is transmitted is received at matrix interface circuit 46, which then transmits the data to switch 12. Switch 12 performs switching on the individual 672 DSO data channels, such as by restructuring the order in which the 672 DSO data channels are sequenced. The 672 DSO data channels are then transmitted back to matrix interface circuit 46. Matrix interface circuit 46 transmits the 672 DSO data channels to bus control circuit 44 over ingress bus 60 in a predetermined format. Bus control circuit 44 then generates the broadcast data stream, including the 672 DSO data channels that have been switched through switch 12. The broadcast data stream is received at STSM circuits 42 for retransmission through fiber optic conductor 18 via optical interface circuit 40. The broadcast data may also or alternatively be transmitted to matrix interface circuit 46, tone recognition circuit 48, high speed line trunk processor circuit 50, or other suitable circuits for suitable data processing.

FIGURE 2 is a connection diagram of a bus control system 70 showing the connections between STSM circuits 42 and bus control circuits 44. A suitable number of application circuits such as STSM circuits 42 may be coupled to multiplexer 78 (MUX) of bus control circuits 44 via ingress buses 60. Each STSM circuit 42 transmits a single data stream of encoded data to bus control circuit 44 over an associated ingress bus 60. The single data streams of encoded data received from each ingress bus 60 at multiplexer 78 are then combined by bus control circuit 44 into a broadcast data stream. The broadcast data stream is transmitted from multiplexer 78 over egress buses 62 to STSM circuits 42 and other application circuits. The broadcast data stream comprises some or all of the data from each single data stream, which is encoded in a format that allows any part of the data to be identified and located within the broadcast data stream.

Plane 72 and plane 74 of bus control system 70 may comprise components such as STSM circuits 42, ingress buses 60, bus control circuits 44, and egress buses 62. Bus control circuits 44 of plane 72 and plane 74 are coupled together via high speed links 76, which are high frequency data streams, such as 16-bit parallel data channels operating at 51.84 MHZ. The broadcast data stream received at plane 72 from plane 74 via high speed link 76 may be multiplexed in part or in whole into the broadcast data stream transmitted from plane 72 to plane 74, in response to administration, control, and routing data. The broadcast data stream received at plane 74 from plane 72 via high speed link 76 may also be multiplexed in part or in whole into the broadcast data stream transmitted from plane 74 to plane 72.

Plane 72 and plane 74 may be configured as completely redundant physical transport layers carrying redundant data streams for the telecommunications data received via fiber optic conductor 18. In this configuration, multiple failures of individual components in the redundant plane 72 and plane 74 would not interrupt data transmission as long as one complete data transmission path remains available.

Plane 72 and plane 74 may alternatively be configured as independent transport layers carrying unique telecommunications data. Individual STSM circuits 42 of plane 72 or plane 74 may also be configured in a redundant formation, such that one or more STSM circuits 42 are redundant in plane 72 and plane 74. In operation, bus control circuit 44 of plane 72 receives a plurality of single data streams in a predetermined data format from each of ingress buses 60 and multiplexes the single data streams into a first broadcast data stream having a predetermined data format. Bus control circuit 44 of plane 72 then transmits the first broadcast data stream to application circuits 42 over egress buses 62. Bus control circuit 44 of plane 72 also transmits the first broadcast data stream to bus control circuit 44 of plane 74 via high speed link 76.

Bus control circuit 44 of plane 74 receives a plurality of single data streams comprising synchronous transfer mode data and asynchronous transfer mode data from each of ingress buses 60 and the first broadcast data stream, and multiplexes the single data streams and part or all of the data from the first broadcast data stream into a second broadcast data stream. Bus control circuit 44 of plane 74 then transmits the second broadcast data stream to STSM circuits 42 over egress buses 62. Bus control circuit 44 of plane 74 also transmits the second broadcast data stream to bus control circuit 44 of plane 72 via high speed link 76. Bus control circuit 44 of plane 72 receives the second broadcast data stream, and multiplexes part or all of the data from the second broadcast data stream into the first broadcast data stream.

FIGURE 3 is a connection diagram for bus control system 90 constructed in accordance with teachings of the present invention. Bus control system 90 includes plane 72 and plane 74. Plane 74 includes STSM circuit 42, optical interface circuit 40, matrix interface circuit 46, tone recognition circuit 48, and high speed line trunk processor circuit 50, each of which are coupled as shown to bus control circuit 44 by ingress buses 60 and egress buses 62. Plane 72 includes echo canceler circuits (ECHO) 92, which are coupled to bus control circuit 44 by ingress buses 60 and egress buses 62. Bus control circuits 44 of plane 72 and plane 74 are coupled together by high speed link 76. STSM circuit 42, matrix interface circuit 46, tone recognition circuit 48, and high speed line trunk processor circuit 50 are application circuits that transmit data over ingress bus 60 and receive data over egress bus 62 in predetermined formats. This data may include synchronous transfer mode data and asynchronous transfer mode data, such as iMPAX packet layer datagrams. Each application circuit may include a modular bus interface circuit (not explicitly shown) . The modular bus interface circuit receives data from the application circuit and converts it into a predetermined format for transmission over ingress bus 60. The modular bus interface circuit also receives data in a predetermined format over egress bus 62 and converts it into a format that is useable by the application circuit associated with the bus interface circuit .

Optical interface circuit 40 receives the broadcast data stream from egress bus 62 and transmits a data stream over ingress bus 60 to bus control circuit 44. The data received and transmitted by optical interface circuit typically includes only asynchronous transfer mode data in the form of iMPAX packet layer datagrams, which are used to carry control data and control commands between the components of fiber optic connection unit 14. Synchronous transfer mode data could also be received by and transmitted to optical interface circuit 40 over ingress bus 60 and egress bus 62.

Echo canceler circuit 92 includes one or more digital signal processors (not explicitly shown) that are operable to remove echo signals from individual DSO data channels that are included in the broadcast data stream. Echo canceler circuit 92 may include a single circuit card that has plug-in connectors (not explicitly shown) to allow the card to be easily installed in a cabinet containing other component circuit cards of fiber optic connection unit 14. Alternatively, echo canceler circuit 92 may include two or more circuit cards, or one or more discrete components on a single circuit card.

Bus control circuits 44 of plane 72 and plane 74 of bus control system 90 receive single data streams from each ingress bus 60 and multiplex the data to form a first broadcast data stream and a second broadcast data stream, respectively. The first and second broadcast data streams are then transmitted to application circuits via egress buses 62, and to bus control circuit 44 of the alternate plane by high speed link 76.

In operation, data streams are received at optical interface circuit 40 and are transmitted to STSM circuits 42 for subsequent transmission to bus control circuit 44 via ingress bus 60. These telecommunications data streams are then multiplexed by bus control circuit 44 and are transmitted in a single broadcast data stream over egress buses 62 and high speed link 76 to other application circuits .

For example, the broadcast data stream of bus control circuit 44 of plane 72 may be received at tone recognition circuit 48. Tone recognition circuit 44 processes individual DSO data channels that are contained within the broadcast data stream to identify dual tone multi-frequency

(DTMF) tone signals that are included in the individual DSO data channels. Alternatively or in addition, the broadcast data stream may be received at matrix interface circuit 46 to be transmitted to switch 12 for switching of individual DSO data channels through the matrix fabric of switch 12. The first broadcast data stream may also be transmitted to echo canceler circuit 92 through high speed link 76 and subsequent multiplexing into the second broadcast data stream by bus control circuit 44 of plane 74 in order to be processed for cancellation of echo signals.

FIGURE 4 is a block diagram of bus control circuit 44 of bus control system 70 and bus control system 90. Bus control circuit 44 includes ingress interface circuit (ING) 100, which is coupled to a plurality of ingress buses 60. Ingress interface circuit 100 includes data buffers (not explicitly shown) for storing asynchronous transfer mode data and bypass connection circuits for carrying synchronous transfer mode data. The outputs of the data buffers and bypass connection circuits are coupled to the inputs to multiplexer circuit (MUX) 106. A bus interface and timing circuit (BIF) 104 is also coupled to ingress interface circuit 100. Bus interface and timing circuit 104 is a modular interface circuit that is used to receive the broadcast data stream from egress bus 62 and to transmit a single data stream over an ingress bus 60. As shown in FIGURE 4, bus interface and timing circuit 104 is used to receive the broadcast data stream from 102 and to transmit it to ingress interface circuit 100. Control data received from on-board controller circuit 114 is used to selectively control the data that is transmitted to ingress interface circuit 100 in the event that the bandwidth of the data signal on egress bus 62 is greater than the bandwidth of the data signal on ingress bus 60. Multiplexer circuit 106 includes bus slot multiplexer circuit (BSM) 112 which is coupled to link buffer circuits (LBC) 116, on-board controller circuit (OBC) 114, and dual port buffer circuit (DPB) 130. Data received from ingress interface circuit 100 and dual port buffer circuit 130 is multiplexed by bus slot multiplexer circuit 112 in response to control data received from on-board controller circuit 114. Data transmitted over ingress buses 60 and egress bus 62 includes a plurality of bus slots, where each bus slot is a 64 byte data format that may comprise a synchronous transfer mode datagram, an asynchronous transfer mode datagram, or an idle datagram. Each datagram contains control data such as packet type indicators and control record check data that is used by the ingress interface circuit 100 or egress interface circuit 108 for diagnostic purposes, such as to verify frame alignment, detect control record check errors, detect frame synchronization/presence errors, detect packet type indicator errors, or other suitable diagnostic purposes. On-board controller circuit 114 is a modular control circuit that may be installed on the same circuit card as bus controller circuit 44, or on an attached daughtercard. On-board controller circuit 114 is coupled to bus interface circuit 104, arbiter circuit 110, multiplexer circuit 106, egress interface 108, and other components of bus controller circuit 44. On-board controller circuit 114 receives control data from and transmits control data to arbiter circuit (ARB) 110 that is used to provide control data to bus slot multiplexer circuit 112 and an egress frame multiplexer circuit (EFM) 118. Arbiter circuit 110 is used to programmably allocate the bandwidth for each of the data streams received from the plurality of ingress buses 60 received at ingress interface circuit 100. For example, each of the ingress buses 60 may transmit an 8-bit data channel operating at a frequency of 25.92 MHZ, with an effective data bandwidth of approximately 200 million bits per second. The egress bus 62 may transmit a 16-bit data channel operating at a frequency of 51.84 MHZ, with an effective data bandwidth of approximately 800 million bits per second. Control data received from arbiter circuit 110 is used to allocate data bandwidth for each of the ingress buses received at ingress interface circuit 100 in the event that greater than 800 million bits per second of data are received from all of the ingress buses 60.

Dual port buffer circuit 130 receives a broadcast data stream from a bus control circuit 44 via high-speed link 76, which is a 16-bit parallel data channel operating at 51.84 MHZ. A high-speed link receiver circuit (HSLR) 134 is coupled to high-speed link 76 and transfers the broadcast data stream to egress reformatter circuit (ERC) 132, which converts the broadcast data channel into two 8-bit parallel data channels operating at a frequency of 25.92 MHZ. The converted broadcast data stream is then provided to multiplexer circuit 112 by dual port buffer circuit 130. Arbiter circuit 110 also controls the allocation of bandwidth for the broadcast data stream provided by dual port buffer circuit 130.

Data received at multiplexer circuit 112 is multiplexed by selectively storing the data in one of four link buffer circuits 116 in response to control data received from arbiter circuit 110. Data from link buffer circuits 116 is then multiplexed with egress header data by egress frame multiplexer 118 to form a broadcast data stream. The broadcast data stream is transmitted to egress interface (EIF) 108, which includes an egress processor circuit (EPC) 120, a broadcaster circuit (BX) 122, and a broadcaster interface circuit (BXI) 124. The broadcast stream is transmitted from broadcaster circuit 122 to egress reformatter circuit 132 for transmission to high speed transmitter circuit (HST) 136 and high-speed link 76. Broadcaster interface circuit 124 transmits sixteen redundant broadcast data streams to egress bus drivers 102, which boost the signal strength of the broadcast data stream for transmission over egress buses 62.

In operation, a plurality of single data streams are received at ingress interface circuit 100 of bus control circuit 44 from ingress buses 60. Administration and control data is extracted and diagnostic data analysis is performed on the administration and control data. Asynchronous transfer mode data is temporarily stored in data buffers, and synchronous transfer mode data is transmitted directly to bus slot multiplexer 112. In addition, broadcast data stream data received from one or more other bus control circuits 44 is also transmitted to bus slot multiplexer 112. Asynchronous transfer mode data from data buffers in ingress interface circuit 100 is transmitted to bus slot multiplexer circuit 112 on a rotating priority as determined by arbiter circuit 110. In this manner, a data channel may be received from

STSM circuit 42, transmitted through bus control circuit 44, and routed to other application circuits for data processing, such as switching, echo cancellation, tone detection, or other suitable data processing. The DSO data may then be routed back to bus control circuit 44, and may ultimately be transmitted back to STSM circuit 42. The bandwidth of data received from any given application circuit may be controlled, and data processing may be performed on the data while it is being combined with other data without preventing errors from being detected or interfering with error detection and diagnostic functions.

Bus slot multiplexer circuit 112 stores multiplexed data in link data buffer circuits 116 in response to control data received from arbiter circuit 110 as programmed by the on-board controller circuit 114. Link data buffer circuits 116 then transfer data to egress frame multiplexer circuit 118, which combines the data from the link data buffer circuits 116 with egress header data to form a broadcast data stream. The broadcast data stream is then transmitted by high speed link 76 to one or more bus control circuits 44, and by egress bus driver circuits 102 to egress buses 62.

FIGURE 5 is a block diagram showing the connections between ingress buses 60, ingress interface circuit 100, and multiplexer circuit 106 in accordance with teachings of the present invention. Each ingress bus 60 is coupled to an ingress data buffer circuit (IDB) 150, which is a data storage device that selectively stores and transmits data. Asynchronous transfer mode data in the single data stream received at ingress interface circuit 100 from an ingress bus 60 is temporarily stored in the corresponding ingress data buffer circuit 150 for subsequent transmission to bus slot multiplexer circuit 112.

Synchronous transfer mode data from each single data stream is transmitted to bus slot multiplexer circuit 112. Synchronous transfer mode data from the broadcast data stream is received from dual port buffer circuit 130 and transmitted directly to bus slot multiplexer circuit 112. Each bus slot multiplexer circuit 112 is a 34:1 multiplexer that selectively stores received data in the associated link buffer circuit 116. The output from link buffer circuits 116 is a 16-bit parallel data stream.

In operation, asynchronous transfer mode data is stored in ingress data buffer circuits 150 until the asynchronous transfer mode data is selected for transmission, based upon an iMPAX packet layer datagram enable signal that is transmitted from each of the application cards to the bus control circuit 44. The iMPAX packet layer datagram enable signal may be sent over a dedicated data line, or may be included in one or more predetermined time slots of a data bus.

Each ingress data buffer circuit 150 has a predetermined data storage capacity and stores new asynchronous transfer mode data while transmitting presently stored data. This asynchronous transfer mode data is transmitted to bus slot multiplexer circuits 112 along with synchronous transfer mode data. Control data for selecting by multiplexer 112 is derived from control data generated by arbiter circuit 110. Storage of multiplexed data in link buffer circuits 116 is controlled in order to perform broadcast switching of both synchronous transfer mode data and asynchronous transfer mode data. FIGURE 6 is a block diagram showing the connections between link buffer circuits 116, header buffer circuit 152, and egress frame multiplexers first stage 118A and second stage 118B in accordance with teachings of the present invention. Link data buffer circuits 116 are coupled to egress frame multiplexer first stage 118A, which multiplexes data streams from the four link data buffer circuits 116 into an intermediate data stream. Frame header data stored in header buffer circuit 152 is then multiplexed with the intermediate data channel by egress frame multiplexer second stage 118B to form the broadcast data channel. The broadcast data channel is then transmitted to egress interface circuit 108.

FIGURE 7 is a diagram of an ingress bus frame format 160 embodying concepts of the present invention. Data transmitted over ingress bus 60 may be encoded in the format of ingress bus frame format 160, or in other suitable formats.

Ingress bus frame format 160 has a period of 125 microseconds, and includes a frame header block comprising 32 bytes of data. An 8-byte pad data block is included to aid in clock synchronization. Ingress bus frame format 160 also includes fifty 64-byte bus slots. Each bus slot may be transmitted on an 8-bit wide data stream operating at a frequency of 25.92 MHZ, to provide a bandwidth of approximately 200 Mb/s. Other suitable data stream formats and frequencies may be used, such as a data stream having a width of any integer value between 1 and 128, greater or lesser bus slots having a greater or lesser number of bytes, and operating frequencies between 10 kHz and 200 MHZ, in 1 Hz increments. FIGURE 8 is a diagram of an egress bus frame format

170 embodying concepts of the present invention. Data transmitted over egress bus 62 may be encoded in the format of egress bus frame format 170, or in other suitable formats.

Egress bus frame format 170 has a period of 125 microseconds, and includes a frame header block comprising 32 bytes of data. Egress bus frame format 170 also includes two hundred and two 64-byte bus slots. Each bus slot may be transmitted on a 16-bit wide data stream operating at a frequency of 51.84 MHZ, to provide a bandwidth of approximately 800 Mb/s. Other suitable data stream formats and frequencies may be used, such as a data stream having a width of any integer value between 1 and 128, greater or lesser bus slots having a greater or lesser number of bytes, and operating frequencies between 10 kHz and 200 MHZ, in 1 Hz increments.

FIGURE 9 is a diagram of an egress bus slot stuffing format 180 embodying concepts of the present invention. Egress bus slot stuffing format 180 shows the sequence in which data from the four link data buffer circuits 116 of multiplexer circuit 106 is transmitted over egress bus 62 in egress bus frame format 170. After the 32-byte egress bus header is transmitted, link A transmits a datagram comprising 32 16-bit data packets, which form one 64-byte egress bus slot. This datagram may be a synchronous transfer mode datagram, an asynchronous transfer mode datagram such as an iMPAX packet layer datagram, an idle datagram, or other suitable datagrams. Link B, link C, and link D then each transmit a 32 16-bit data datagram. The process then repeats every four bus slots until 200 egress bus slots have been transmitted. Two idle datagrams are then transmitted to complete the 202-byte payload of egress bus frame format 170.

In this manner, bus slot data from ingress bus frame format 160 may be accumulated in the four link data buffer circuits 116 until they are filled. The data is stored in the four link data buffer circuits 116 such that link A may transmit a first 64-byte egress bus slot, followed in sequence by link B, link C, and link D. The data received from the bus slots of the 16 ingress buses 60 may be stored in the four link buffer circuits 116 in a suitable order, as long as each link buffer has a complete 64-byte set of data to transmit at the appropriate time. Thus, while link A is transmitting, link D may be filling if link B is already filled. Then, while link B is transmitting, link C and link A may be filling, and so forth.

FIGURE 10 is a diagram of an egress slot address map 190 embodying concepts of the present invention. Egress slot address map 190 may be stored in a random access memory of arbiter circuit 110 of FIGURE 4. Egress slot address map 190 is a 202 byte address map that contains the address of an ingress bus 60 bus slot source for each of the egress bus 62 bus slots.

The 200 bus slots of one egress bus frame format 170 may include 50 link A datagrams, 50 link B datagrams, 50 link C datagrams, and 50 link D datagrams, in the order shown. The address of the ingress bus 60 bus slot that will be used to provide the datagram for the corresponding location of egress slot address map 190 is stored in egress slot address map 190. For example, egress bus slot Al may be filled with a synchronous transfer mode datagram from the bus slot of the 13th of 16 ingress buses 60. The address for this ingress bus source will be stored in the Al map location of egress slot address map 190. If a switching change is required, such as to store an iMPAX packet layer datagram from the 3rd of 16 ingress buses 60 in egress bus slot Al, then the address of the new ingress bus source is stored in egress slot address map 190. Arbiter circuit 110 then generates appropriate commands such that the four link buffer circuits 116 and egress frame multiplexer first stage 118A place the appropriate ingress bus slot in egress bus slot Al.

FIGURE 11 is a flow chart of a method 200 for controlling telecommunications buses in accordance with concepts of the present invention. Method 200 begins at step 202, where a plurality of ingress bus bus slots are received at a bus control circuit. These ingress bus bus slots may include synchronous transfer mode datagrams, asynchronous transfer mode datagrams, and idle datagrams. In addition to the plurality of ingress bus bus slots, egress bus bus slots containing asynchronous transfer mode data from another bus control circuit and a bus interface circuit may also be received. At step 204, frame header data is extracted from each of the ingress bus frame formats by the bus control circuit. The frame header data may include routing, control, and other administrative data that is used by an on-board controller circuit to determine egress bus bus slot assignments for ingress bus bus slots. The method then proceeds to step 206, where asynchronous transfer mode datagrams are stored in ingress data buffer circuits of the bus control circuit.

At step 208, datagrams are stored in link buffer circuits in accordance with address data stored in an egress slot address map. The method then proceeds to step 210, where egress bus header data is generated and sequenced onto an egress data bus. At step 212, datagrams are sequenced into bus sots of an egress bus in accordance with the address data. At step 214, the egress bus data is transmitted to an interface of the bus control circuit. The egress bus data is then converted into ingress bus data at step 216 in response to commands received from an on-board controller. The method then returns to step 202 where the ingress bus data is transmitted to the ingress data buffer circuit of the bus control circuit, in addition to the plurality of ingress bus bus slots and egress bus bus slots containing asynchronous transfer mode data from the other bus control circuit. In operation, method 200 is used to received 16 ingress buses at a first bus control circuit, in addition to an egress bus from a second bus control circuit. Synchronous transfer mode datagrams from the 16 ingress buses are combined with asynchronous transfer mode datagrams from the 16 ingress buses, the second bus control circuit, and a bus interface circuit of the first bus control circuit into a new sequence of datagrams. The new sequence of datagrams is then transmitted over an egress bus. The new sequence of datagrams is transmitted through the bus interface circuit of the first bus control circuit to the input of the first bus control circuit, and is also transmitted to the input of a second bus control circuit.

The present invention provides many important technical advantages. One technical advantage of the present invention is a data bus controller with the ability to control both synchronous transfer mode data and asynchronous transfer mode data. Another advantage of the present invention is a system for data bus control that allows multiple incoming data buses to be multiplexed into a single outgoing data bus.

Although several embodiments of the present invention and its advantages have been described in detail, it should be understood that mutations, changes, substitutions, transformations, modifications, variations, and alterations can be made therein without departing from the teachings of the present invention, the spirit and scope of the invention being set forth by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A system for controlling a data bus comprising: a datagram receiver operable to receive a plurality of datagrams in parallel; a datagram storage device coupled to the datagram receiver, the datagram storage device operable to store the datagrams received by the datagram receiver; and a datagram transmitter coupled to the datagram storage device, the datagram transmitter operable to receive stored datagrams from the datagram storage device and to transmit the datagrams .

2. The system of Claim 1 wherein the datagram storage device further comprises: a plurality of asynchronous transfer mode datagram buffers coupled to the datagram receiver, the plurality of asynchronous transfer mode datagram buffers operable to selectively store and transmit asynchronous transfer mode datagrams; a selector coupled to the datagram receiver and the plurality of asynchronous transfer mode datagram buffers, the selector operable to select one datagram from the datagram receiver or the plurality of asynchronous transfer mode datagram buffers; and an output buffer coupled to the selector and the datagram transmitter, the output buffer operable to receive and store the selected datagram from the selector, and to output the selected datagram to the datagram transmitter.

3. The system of Claim 1 further comprising a datagram configuration mapper coupled to the datagram storage device, the datagram configuration mapper operable to store an address map containing the address of each datagram that is to be stored by the datagram storage device, and the order in which each datagram is to be stored.

4. The system of Claim 1 further comprising an ingress header receiver coupled to the datagram receiver, the ingress header receiver operable to receive a header data block that precedes a plurality of datagrams.

5. The system of Claim 1 further comprising a plurality of ingress buses coupled to the datagram receiver, wherein each ingress bus is operable to sequentially transmit single datagrams to the datagram receiver .

6. The system of Claim 1 further comprising: a plurality of ingress buses coupled to the datagram receiver, wherein each ingress bus is operable to sequentially transmit single datagrams to the datagram receiver; a plurality of asynchronous transfer mode datagram buffers, each asynchronous transfer mode datagram buffer coupled to a single ingress bus, each asynchronous transfer mode datagram buffers operable to selectively store and transmit asynchronous transfer mode datagrams; a selector coupled to the plurality of ingress buses and the plurality of asynchronous transfer mode datagram buffers, the selector operable to select a datagram from one of the plurality of ingress buses or the plurality of asynchronous transfer mode datagram buffers; and an output buffer coupled to the selector and the datagram transmitter, the output buffer operable to receive and store the selected datagram from the selector, and to output the selected datagram to the datagram transmitter.

7. The system of Claim 1 further comprising a bus interface coupled to the datagram transmitter and the datagram receiver, the bus interface operable to transmit data from the datagram transmitter to the datagram receiver.

8. A system for controlling a data bus comprising: a datagram receiver operable to receive a plurality of datagrams in parallel; a datagram storage device coupled to the datagram receiver, the datagram storage device operable to store the datagrams received by the datagram receiver; a datagram transmitter coupled to the datagram storage device, the datagram transmitter operable to receive stored datagrams from the datagram storage device and to transmit the datagrams; and a datagram configuration mapper coupled to the datagram storage device, the datagram configuration mapper operable to store an address map containing the address of each datagram that is to be stored by the datagram storage device, and the order in which each datagram is to be stored.

9. The system of Claim 8 further comprising an ingress header receiver coupled to the datagram receiver, the ingress header receiver operable to receive a header data block that precedes a plurality of datagrams.

10. The system of Claim 8 further comprising a bus interface coupled to the datagram transmitter and the datagram receiver, the bus interface operable to transmit data from the datagram transmitter to the datagram receiver.

11. A method for controlling a data bus comprising: receiving a plurality of datagrams from a plurality of ingress buses; storing selected datagrams in a plurality of first buffers; and outputting the datagrams in a predetermined sequence on a single egress bus.

12. The method of Claim 11 wherein receiving a plurality of datagrams comprises: receiving a plurality of synchronous transfer mode datagrams, a plurality of asynchronous transfer mode datagrams, and a plurality of idle datagrams; storing each of the plurality of asynchronous transfer mode datagrams to one of a plurality of second buffers; and transmitting each of the plurality of asynchronous transfer mode datagrams to one of the first buffers in response to an enable signal.

13. The method of Claim 11 wherein storing selected datagrams comprises: retrieving a datagram source address for each of the plurality of second buffers from an address map; and storing a datagram having the associated datagram source address in each of the plurality of second buffers.

14. The method of Claim 11 wherein storing selected datagrams further comprises storing egress header data in an egress header buffer.

15. The method of Claim 11 wherein outputting the datagrams further comprises: outputting egress header data; and outputting the datagrams stored in each of the plurality of first buffers in a predetermined sequence.

16. The method of Claim 11 wherein outputting the datagrams further comprises: outputting egress header data; and outputting the datagrams stored in each of the plurality of first buffers in a predetermined sequence until a complete egress frame has been output; and outputting two idle datagrams.

17. The method of Claim 11 further comprising receiving the output from the single egress bus at an ingress bus interface.

18. The method of Claim 11 further comprising: receiving the output from the single egress bus at a bus interface; selecting predetermined data from the output from the single egress bus; transmitting the predetermined data over an ingress bus to an ingress bus interface.

19. A method for controlling a data bus comprising: receiving a plurality of synchronous transfer mode datagrams, a plurality of asynchronous transfer mode datagrams, and a plurality of idle datagrams; storing each of the plurality of asynchronous transfer mode datagrams to one of a plurality of second buffers; transmitting each of the plurality of asynchronous transfer mode datagrams to one of the first buffers in response to an enable signal; retrieving a datagram source address for each of the plurality of second buffers from an address map; storing a datagram having the associated datagram source address in each of the plurality of second buffers; outputting egress header data; and outputting the datagrams stored in each of the plurality of first buffers in a predetermined sequence.

20. The method of Claim 19 wherein storing selected datagrams further comprises storing egress header data in an egress header buffer.

21. The method of Claim 19 further comprising receiving the output from the single egress bus at an ingress bus interface.

22. The method of Claim 19 further comprising: receiving the output from the single egress bus at a bus interface; selecting predetermined data from the output from the single egress bus; transmitting the predetermined data over an ingress bus to an ingress bus interface.