WO1999017225A1 - Method of address search in an unbalanced and partly occupied binary tree - Google Patents

Method of address search in an unbalanced and partly occupied binary tree Download PDF

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Publication number
WO1999017225A1
WO1999017225A1 PCT/DE1998/002550 DE9802550W WO9917225A1 WO 1999017225 A1 WO1999017225 A1 WO 1999017225A1 DE 9802550 W DE9802550 W DE 9802550W WO 9917225 A1 WO9917225 A1 WO 9917225A1
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Prior art keywords
entry
search
level
address
tree
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PCT/DE1998/002550
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German (de)
French (fr)
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Roland BRÜCKNER
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Siemens Aktiengesellschaft
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/742—Route cache; Operation thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags

Definitions

  • the subject of the application relates to a method for locating an address in a partially occupied, unbalanced binary tree.
  • a possible approach to address the problems outlined is based on a restriction of address allocation. Ever larger address areas are being allocated at once. However, this leads to poor utilization of the available memory area. In addition, subsequent changes to the assigned address area are difficult or impossible afterwards.
  • Another approach to address the problems outlined is based on the use of a CAM (Content Addressable Memory) as a hardware solution.
  • this ASIC element is not a standard element and the use is therefore associated with relatively high costs.
  • the blocks currently available usually only support an address range for lk to 8k connections.
  • Another approach to counter the problems outlined is based on the construction and use of a search tree (binary tree) to iteratively determine the address.
  • the search time depends on the height of the tree.
  • the minimum number of search accesses is proportional to log 2 N. By balancing the tree, the building structure can be minimized.
  • Search time t A * 1.44 * log 2 N is minimal (A duration of a single access, 1.44 Fibonacci number as a limit for AVL trees, 3 accesses for a rotation double rotation step), but the balancing requires a maximum of approx.
  • a minimal tree structure does have a minimal search time, in order to maintain the minimal tree structure when deleting or inserting addresses, extensive processing of algorithms is necessary, which takes up a corresponding amount of time.
  • the object of the application is based on the problem of specifying a method which has an optimization of the search for valid addresses.
  • the object of registration In the case of the object of registration, the time required to search for an entry is shorter or at most the same time as the time required to search for an entry in a maximum search tree. In addition, the object of the application achieves an increase in the comparison speed compared to search methods in which each address addressed is compared with the address sought.
  • the subject of registration which is not a balancing and thus minimal search depth (M instead of N), has a minimized processing function and thus offers a cost-effective implementation in hardware (ASIC or FPGA), whereby scaling with the available technology is given.
  • ASIC or FPGA cost-effective implementation in hardware
  • the subject of the application also allows the search for minima and maxi a.
  • the use of RAM structures and a user-definable comparator offers additional options for linking to status bits, which can be used for additional selection criteria.
  • the object of registration which is based on a division of the search tree in the first level in accordance with the MSB (Most Significant Bit) 0 or 1, the first level (level 0) branches in accordance with the first bit position of the address sought .
  • MSB Mobile Bit
  • This requirement allows the use of a particularly simple hardware (circuitry-related) comparator.
  • the entries of the first level (level 0) and subsequent levels (level I, II 7) are mapped in an area of the RAM memory. This measure brings a shortening of the M search tree with direct address mapping.
  • 2 shows as an example a number of 10 valid address entries ⁇ 0,1,2,7,8,9,11,13,15,25 ⁇ .
  • 3 shows the address entries from FIG. 2 in binary representation 4 shows the partially filled resulting from FIG. 1
  • FIG 5 shows the minimal, balanced search tree
  • FIG 6 shows the replacement process in the partially filled search tree
  • FIG 7 shows a circuit arrangement for shortening the
  • 1 shows the basic structure of a binary field with levels I, II, III and IV.
  • FIG. 3 shows the address entries from FIG. 2 in binary representation.
  • an entry has the following structure:
  • the balanced search tree has a height which is 1 less than that in FIG. 4.
  • U «N * log 2 N operations are necessary in the worst case.
  • P_upper is corrected if necessary. However, this has no influence on the worst case search speed, because in this case (at least one level is not occupied) the entry was reached too early, so to speak.
  • the parallel comparison across all processed bit positions can also take place “slowly” from ⁇ i> to ⁇ i + l>, since in the event of a mismatch in V bit positions, V search positions are consequently over- jumps and thus as many comparison operations were saved.
  • Entry ⁇ 8 ⁇ receives the stored pointers on Entry ⁇ 7 ⁇ - P_lower and Entry ⁇ 7 ⁇ - P_upper (action_2), the pointer Entry ⁇ 11 ⁇ - P_lower also receives the value Entry ⁇ 8 ⁇ - P_upper (action_3).
  • the deletion process therefore requires 3 actions more than a comparable pure search access.
  • the proposed algorithm not only allows a search comparable to CAM access, it also offers the option of sorting e.g. targeted to the smallest or largest
  • Access entry An extended use e.g. for sorting data cells based on sequence numbers (blessing number or timestamp, healing with random routing) can be supported.
  • One way to shorten the search process is to shorten the search depth.
  • the search Since the arrangement is sorted, the upper part of the search tree can be mapped directly in a RAM (random access memory) area. With 2 ⁇ n entries, the search only has to start at level n. If, for example, 16k memory entries are available, the search depth is reduced by 14. Alternatively, all possible entries of level n + 1 can also be stored in the 16k DirectMappings. The search depth is then reduced by 15; if you search above level 15, the search starts at the root.
  • Another way to speed up the search process is to extend the search principle to more than 2 pointers.
  • a tree height of H log 2 M / i results.
  • FIG. 7 shows a hardware implementation for a search with 4 pointers, in which it is not absolutely necessary to bring the pointer values to the comparator.
  • An entry RAM is addressed via a tristate bus by exactly the pointer RAM from a plurality of pointer RAMs (pointer 1 RAM .. pointer i RAM), the output of which is activated via a chip select signal. If P_upper and P_lower are in the same pointer RAM, which means that it is not possible to select a tristate bus via chip select, an external multiplexer can be provided. The output of the entry RAM is connected to the comparator.

Abstract

Disclosed is a method of address search in an unbalanced and partly occupied binary tree, whereby when investigation is ramified for searching the wanted address, a comparison for the purposes of identifying correspondence is carried out to enable entry into the next deep plane. When applying such a method, the time needed for an entry attempt is shorter or at least not as long as for an entry attempt in a tree of maximum search depth.

Description

Beschreibungdescription
Verfahren zum Aufsuchen einer Adresse in einem teilbesetzten, nicht-balancierten Binären BaumMethod of finding an address in a partially populated, unbalanced binary tree
Der Anmeldungsgegenstand betrifft ein Verfahren zum Aufsuchen einer Adresse in einem teilbesetzten, nicht-balancierten Binären Baum.The subject of the application relates to a method for locating an address in a partially occupied, unbalanced binary tree.
Vor allem im Bereich ATM ( Asynchroner Transfer Mode) und auch des Ethernet Routings muß bei einem großen Adressbereich (typ. M=2Λ33 Adressen) schnell und effizient festgestellt werden können, ob eine Adresse gültig ist. Die Anzahl gültiger Adressen ist hierbei mit N=2Λ14 = 16000 meist relativ klein. Während somit die Speicherung der gültigen Daten mit wenigen Mbyte Speicher behandelt werden kann, ist eine Behandlung des gesamten Adressvorrates mit mehreren Gigabyte Speicher nicht wirtschaftlich möglich. In der Vermittlungs- technik tritt zudem die Anforderung auf, bislang gültige Adressen zu löschen und neue gültige Adressen einzufügen.Especially in the area of ATM (Asynchronous Transfer Mode) and also Ethernet routing, it must be possible to quickly and efficiently determine whether an address is valid with a large address range (typically M = 2 Λ 33 addresses). The number of valid addresses is usually relatively small with N = 2 Λ 14 = 16000. While the storage of the valid data can thus be handled with a few Mbytes of memory, it is not economically feasible to handle the entire address pool with several gigabytes of memory. In switching technology, there is also a requirement to delete previously valid addresses and to insert new valid addresses.
Ein möglicher Ansatz, der aufgezeigten Problematik zu begegnen basiert auf einer Restriktion der Adressvergabe. Es werden immer größere Adressbereich auf einmal vergeben. Dies führt jedoch zu einen schlechten Ausnutzung des verfügbaren Speicherbereiches, zudem sind nachträgliche Änderungen des vergebenen Adressbereiches im nachhinein nur noch schwer, oder nicht mehr möglich.A possible approach to address the problems outlined is based on a restriction of address allocation. Ever larger address areas are being allocated at once. However, this leads to poor utilization of the available memory area. In addition, subsequent changes to the assigned address area are difficult or impossible afterwards.
Ein weiterer Ansatz, der aufgezeigten Problematik zu begegnen basiert auf dem Einsatz eines CAM (Content Adressable Memory) als Hardwarelösung. Dieses ASIC Element ist jedoch kein Standardelement und der Einsatz daher mit relativ hohen Kosten verbunden. Die derzeit verfügbaren Bausteine unterstützen meist nur einen Adressbereich für lk bis 8k Verbindungen. Ein weiterer Ansatz, der aufgezeigten Problematik zu begegnen basiert auf dem Aufbau und der Verwendung eines Suchbaumes (Binary tree) , um iterativ die Adresse zu bestimmen. Die Suchdauer ist hier von der Höhe des Baumes abhängig. Die mi- ni ale Anzahl von Suchzugriffen liegt proportional zu log2N. Durch Balancierung des Baumes ist eine Minimierung der Baura- struktur erreichbar.Another approach to address the problems outlined is based on the use of a CAM (Content Addressable Memory) as a hardware solution. However, this ASIC element is not a standard element and the use is therefore associated with relatively high costs. The blocks currently available usually only support an address range for lk to 8k connections. Another approach to counter the problems outlined is based on the construction and use of a search tree (binary tree) to iteratively determine the address. The search time depends on the height of the tree. The minimum number of search accesses is proportional to log 2 N. By balancing the tree, the building structure can be minimized.
Bisherige Implementierungen eines Suchverfahrens setzen auf einen Suchbaum über die Zielmenge N auf. Die erreichbarePrevious implementations of a search method are based on a search tree using the target set N. The attainable
Suchdauer t=A* 1,44 * log2N ist zwar minimal ( A Dauer eines Einzelzugriffes, 1,44 Fibonacci Zahl als Limit für AVL Bäume, 3 Zugriffe für Rotations- Dopppelrotationsschritt) , die Balancierung benötigt jedoch maximal ca. tN=3*A*l,44 * log2N=69*A.Search time t = A * 1.44 * log 2 N is minimal (A duration of a single access, 1.44 Fibonacci number as a limit for AVL trees, 3 accesses for a rotation double rotation step), but the balancing requires a maximum of approx. T N = 3 * A * l, 44 * log 2 N = 69 * A.
Eine minimale Baumstruktur weist zwar eine minimale Suchzeit auf, zur Aufrechterhaltung der minimalen Baumstruktur bei Löschen oder Einfügen von Adressen ist eine umfangreiche Abar- beitung von Algorithmen erforderlich, die mit einem entsprechenden Zeitbedarf einhergeht .A minimal tree structure does have a minimal search time, in order to maintain the minimal tree structure when deleting or inserting addresses, extensive processing of algorithms is necessary, which takes up a corresponding amount of time.
Dem Anmeldungsgegenstand liegt das Problem zugrunde, ein Verfahren anzugeben, das ein Optimierung der Suche von gültigen Adressen aufweist.The object of the application is based on the problem of specifying a method which has an optimization of the search for valid addresses.
Das Problem wird bei dem Anmeldungsgegenstand durch die Merkmale des Anspruchs 1 gelöst.The problem is solved in the subject of the application by the features of claim 1.
Beim Anmeldungsgegenstand ist der Zeitbedarf für das Aufsuchen eines Eintrages kürzer oder allenfalls gleich lang als der Zeitbedarf für das Aufsuchen eines Eintrages in einem maximalen Suchbaum. Darüberhinaus erzielt der Anmeldungsgegenstand gegenüber Suchverfahren, bei denen jede angesteuert Adresse mit der gesuchten Adresse verglichen wird, eine Steigerung der Vergleichsgeschwindigkeit mit sich. Der Anmeldungsgegenstand, der nicht von einer Balancierung und damit minimaler Suchtiefe ( M statt N) ausgeht, weist eine minimierte Abarbeitungsfunktion auf und bietet somit eine kostengünstige Implementierung in Hardware ( ASIC oder FPGA) , wobei eine Skalierung mit der jeweils verfügbaren Technologie gege- ben ist. Neben dem allgemeinen Suchen erlaubt der Anmeldungsgegenstand auch das Suchen nach Minima und Maxi a . Durch den Einsatz von RAM-Strukturen und einem benutzerdefinierbaren Vergleicher ergeben sich weitergehende Möglichkeiten zur Verknüpfung mit Statusbits, welche für zusätzliche Selektions- kriterien verwendet werden können.In the case of the object of registration, the time required to search for an entry is shorter or at most the same time as the time required to search for an entry in a maximum search tree. In addition, the object of the application achieves an increase in the comparison speed compared to search methods in which each address addressed is compared with the address sought. The subject of registration, which is not a balancing and thus minimal search depth (M instead of N), has a minimized processing function and thus offers a cost-effective implementation in hardware (ASIC or FPGA), whereby scaling with the available technology is given. In addition to the general search, the subject of the application also allows the search for minima and maxi a. The use of RAM structures and a user-definable comparator offers additional options for linking to status bits, which can be used for additional selection criteria.
Gemäß einer besonderen Weiterbildung des Anmeldungsgegenstandes, die von einer Aufteilung des Suchbaumes in der ersten Ebene nach Maßgabe des MSB (Most Signifikant Bit) 0 oder 1 ausgeht, erfolgt in der ersten Ebene (level 0) eine Verzweigung nach Maßgabe der ersten Bitstelle der gesuchten Adresse. Diese Maßgabe erlaubt den Einsatz eines besonders einfachen Hardware (schaltungstechnisch ausgeführten) Komparators .According to a special development of the object of registration, which is based on a division of the search tree in the first level in accordance with the MSB (Most Significant Bit) 0 or 1, the first level (level 0) branches in accordance with the first bit position of the address sought . This requirement allows the use of a particularly simple hardware (circuitry-related) comparator.
Gemäß einer besonderen Weiterbildung des Anmeldungsgegenstandes werden die Einträge der ersten Ebene (level 0) und sich daran anschließender Ebenen (level I, II...) in einem Bereich des RAM-Speichers gemappt . Diese Maßmnahme bringt durch direktes Adressmapping eine Verkürzung des M-Suchbaumes mit sich.According to a special development of the subject of the application, the entries of the first level (level 0) and subsequent levels (level I, II ...) are mapped in an area of the RAM memory. This measure brings a shortening of the M search tree with direct address mapping.
Der Anmeldungsgegenstand wird im folgenden als Ausführungs- beispiel in einem zum Verständnis erforderlichen Umfang anhand von Figuren näher beschrieben. Dabei zeigen: FIG 1 zeigt den prinzipiellen Aufbau eines Binären Feldes der Tiefe 4 mit 2Λ4 = 16 Elementen, also gewissermaßen den gesamten Wertevorrat . FIG 2 zeigt als Beispiel eine Anzahl von 10 gültigen Adresseinträgen { 0,1,2,7,8,9,11,13,15,25 }. FIG 3 die Adresseinträge aus FIG 2 in Binärdarstellung FIG 4 zeigt den aus FIG 2 sich ergebenden teilgefülltenThe subject of the application is described in more detail below as an exemplary embodiment to the extent necessary for understanding with reference to figures. 1 shows the basic structure of a binary field of depth 4 with 2 Λ 4 = 16 elements, that is to say the entire range of values. 2 shows as an example a number of 10 valid address entries {0,1,2,7,8,9,11,13,15,25}. 3 shows the address entries from FIG. 2 in binary representation 4 shows the partially filled resulting from FIG
Suchbaum FIG 5 zeigt den minimalen, balancierten Suchbaum FIG 6 zeigt den Ersetzungsvorgang im teilgefüllten Suchbaum FIG 7 zeigt eine Schaltungsanordnung zur Verkürzung desSearch tree FIG 5 shows the minimal, balanced search tree FIG 6 shows the replacement process in the partially filled search tree FIG 7 shows a circuit arrangement for shortening the
Suchvorgangs .Search.
In den Figuren bezeichnen gleiche Bezeichnungen gleiche Elemente .In the figures, the same designations denote the same elements.
FIG 1 zeigt den prinzipiellen Aufbau eines Binären Feldes mit den Leveln I, II, III und IV.1 shows the basic structure of a binary field with levels I, II, III and IV.
FIG 2 zeigt einen im Beispiel mit 10 gültigen Adresseinträgen { 0,1,2,7,8,9,11,13,15,25 } teilbesetzten Suchbaum. Durch die Verwendung des vollständigen binären Feldes ist die Position jedes Eintrages genau festgelegt. Die maximale Suchlänge ist durch die Höhe des Baumes mit H=log2M bestimmt .2 shows a search tree which is partially occupied in the example with 10 valid address entries {0,1,2,7,8,9,11,13,15,25}. By using the complete binary field, the position of each entry is precisely defined. The maximum search length is determined by the height of the tree with H = log 2 M.
FIG 3 zeigt die Adresseinträge aus FIG 2 in Binärdarstellung.3 shows the address entries from FIG. 2 in binary representation.
Ein Eintrag hat im Prinzip folgenden Aufbau:In principle, an entry has the following structure:
P_lower 14 Bit P_upper 14 Bit „Pointer links" „Pointer rechts"P_lower 14 bit P_upper 14 bit "pointer left" "pointer right"
Eintrag (Entry) 32 Bit „Vergleichswert"Entry 32 bit "comparison value"
In einem Adressraum mit M=2Λ33 Adressen benötigt die Durchführung der Suche bei Verwendung der Binären Suche im teilbesetzten binären Feld bei typ. Anwendungen mit KM = log2M= 33 Zugriffe, statt KN = logN= 16. Dennoch ist bei einer Verkürzung des Suchbaumes um z.B. C=13 Höhen (d.h. 2X3=8k direkte Pointer, 4 Zugriffe für ersten Pointerzugriff) mit tMax=A/2* (4+log2 (M-C) ) =22*A ein günstigeres worst case Zeitverhalten erreichbar. FIG 4 zeigt den aus FIG 2 sich ergebenden teilgefüllten Suchbaum. Der Suchbaum ist zwar in der Höhe nicht minimal, jedoch ist seine maximale Höhe auf H beschränkt .In an address space with M = 2 Λ 33 addresses, the search must be carried out using the binary search in the partially occupied binary field for typical applications with KM = log 2 M = 33 accesses instead of KN = logN = 16. Nevertheless, there is a shortening the search tree by e.g. C = 13 heights (ie 2X3 = 8k direct pointer, 4 accesses for first pointer access) with t Max = A / 2 * (4 + log 2 (MC)) = 22 * A a more favorable worst case time behavior can be achieved. 4 shows the partially filled search tree resulting from FIG. The search tree is not minimal in height, but its maximum height is limited to H.
FIG 5 zeigt den minimalen balancierten Suchbaum wie er sich für das Beispiel aus Fig 2 ergeben würde. Der balancierte Suchbaum hat in diesem Falle eine um 1 geringere Höhe als der in FIG 4. Um diesen Suchbaum zu erhalten müssen viele Positionen umsortiert werden. U « N*log2N Operationen sind im schlimmsten anzunehmenden Fall (worst case) notwendig.5 shows the minimal balanced search tree as it would result for the example from FIG. In this case, the balanced search tree has a height which is 1 less than that in FIG. 4. In order to obtain this search tree, many positions have to be re-sorted. U «N * log 2 N operations are necessary in the worst case.
Falls nicht alle Binärwurzeln besetzt sind, so ergibt sich als Resultat stets eine Verkürzung des maximalen Baumes.If not all binary roots are occupied, the result is always a shortening of the maximum tree.
Bei der Suche nach einem Eintrag in dem in FIG2 bzw. in FIG3 dargestellten Suchbaum ist für die Entscheidung in Level 0 lediglich die (2Λm-0) erste Bitstelle relevant, daher ist die Breite des Komparators stark reduzierbar. Dies macht sich insbesondere bei Einsatz eines Hardwarevergleichers (schaltungstechnisch ausgeführten Vergleichers) vorteilhaft bemerkbar.When searching for an entry in the search tree shown in FIG2 or FIG3, only the (2 Λ m-0) first bit position is relevant for the decision in level 0, so the width of the comparator can be greatly reduced. This is particularly noticeable when using a hardware comparator (circuit comparator).
Für die Suche nach Eintrag {25} (Entry{25}) erfolgt der Vergleich im i-ten Rekursionsschritt entsprechend an der Bit- stelle- <2Am-i>. Durch fehlende Einträge in der binären Liste (missing link) erfolgt hier also die Bewertung ansich an einer nicht zutreffenden Bitposition. Durch Einbeziehung der bereits abgearbeiteten Stellen mit fehlenden Einträgen in einem parallel durchgeführten Vergleich ist dies erkennbar und berücksichtigbar, wobei die Pointerselektion ( P_lower,For the search for entry {25} (Entry {25}), the comparison in the i-th recursion step takes place accordingly at the bit position <2 A mi>. Missing entries in the binary list (missing link) mean that the evaluation takes place at an incorrect bit position. By including the already processed positions with missing entries in a comparison carried out in parallel, this can be recognized and taken into account, the pointer selection (P_lower,
P_upper ) gegebenenfalls korrigiert wird. Dies hat jedoch keinen Einfluß auf die worst case Suchgeschwindigkeit, da in diesem Falle ( mindestens eine Ebene ist nicht besetzt ) sozusagen der Eintrag zu früh erreicht wurde. Der parallele Vergleich über alle abgearbeiteten Bitpositionen kann ebenfalls „langsam,, von <i> nach <i+l> erfolgen, da bei einem Missmatch in V Bitpoεitionen, folglich V Suchpositionen über- spungen und damit ebensoviele Vergleichsoperationen gespart wurden.P_upper) is corrected if necessary. However, this has no influence on the worst case search speed, because in this case (at least one level is not occupied) the entry was reached too early, so to speak. The parallel comparison across all processed bit positions can also take place “slowly” from <i> to <i + l>, since in the event of a mismatch in V bit positions, V search positions are consequently over- jumps and thus as many comparison operations were saved.
FIG 6 zeigt den Ersetzungsvorgang im teilgefüllten Suchbaum. Soll z.B. der Entry{7} aus einer bestehenden Liste entfernt werden, so übernimmt der nächstgrößte Entry dessen Position. Im vorliegenden Falle muß somit bis zum Entry{7} gesucht werden, dessen Position wird gespeichert; anschließend wird unter Entry{7} - P_upper nach dem kleinsten Entry ( am weite- sten links ) gesucht, und Entry{15} - P_lower nun neu auf die Position von Entry{8} gesetzt (Aktion_l) . Entry{8} erhält die gespeicherten Pointer auf Entry{7} - P_lower und Entry{7} - P_upper (Aktion_2) , der Pointer Entry{11} - P_lower erhält gegebenenfalls noch den Wert Entry{8} - P_upper (Aktion_3) .6 shows the replacement process in the partially filled search tree. Should e.g. the entry {7} is removed from an existing list, the next largest entry takes its position. In the present case, you have to search up to entry {7}, its position is saved; then the smallest entry (furthest left) is searched under Entry {7} - P_upper, and Entry {15} - P_lower is now set to the position of Entry {8} (Aktion_l). Entry {8} receives the stored pointers on Entry {7} - P_lower and Entry {7} - P_upper (action_2), the pointer Entry {11} - P_lower also receives the value Entry {8} - P_upper (action_3).
Der Löschvorgang benötigt also 3 Aktionen mehr, als ein vergleichbarer reiner Suchzugriff .The deletion process therefore requires 3 actions more than a comparable pure search access.
Ein anschließender Einfügevorgang für Entry{7}, mit neuem En- try{7}, Aktualisierung von Entry{9} .P_lower und Entry{15} .P_lower benötigt ebenfalls 3 Aktionen.A subsequent insertion process for Entry {7}, with a new Try {7}, updating Entry {9} .P_lower and Entry {15} .P_lower also requires 3 actions.
Der vorgeschlagene Algorithmus erlaubt nicht nur eine Suche vergleichbar mit CAM Zugriffen, er bietet ebenso die Möglich- keit sortiert z.B. gezielt auf den kleinsten oder größtenThe proposed algorithm not only allows a search comparable to CAM access, it also offers the option of sorting e.g. targeted to the smallest or largest
Eintrag zuzugreifen. Ein erweiterter Einsatz z.B. zur Sortierung von Datenzellen anhand von Folgenummern ( Segencenumber oder Timestamp, Ausheilen bei Random Routing) ist unterstütz- bar.Access entry. An extended use e.g. for sorting data cells based on sequence numbers (blessing number or timestamp, healing with random routing) can be supported.
Wie bereits erwähnt benötigt in einem Adreεsraum mit M=2Λ33 Adressen die Durchführung der Suche bei Verwendung der Binären Suche im teilbesetzten binären Feld bei typ. Anwendungen mit KM = log2M= 33 Zugriffe, statt KN = log2N= 16.As already mentioned, in an address space with M = 2 Λ 33 addresses, the search must be carried out using the binary search in the partially occupied binary field for typical applications with KM = log 2 M = 33 accesses instead of KN = log 2 N = 16.
Eine Möglichkeit zur Verkürzung des Suchvorganges ist durch eine Verkürzung der Suchtiefe gegeben. Bei einer Verkürzung des Suchbaumes um z.B. C=13 Höhen (d.h. 2A13=8k direkte Pointer, 4 Zugriffe für ersten Pointerzugriff) mit tMax=A/2* (4+log2 (M-C) ) =22*A ist ein günstigeres worst case Zeitverhalten erreichbar.One way to shorten the search process is to shorten the search depth. With a shortening the search tree by e.g. C = 13 heights (ie 2 A 13 = 8k direct pointer, 4 accesses for first pointer access) with t Max = A / 2 * (4 + log 2 (MC)) = 22 * A is a cheaper worst case Time behavior achievable.
Da die Anordnung sortiert erfolgt, kann z.B. der obere Teil des Suchbaumes direkt in einem RAM (Random Access Memory, Speicher mit wahlfreiem Zugriff) Bereich gemappt werden. Mit 2Λn Einträgen muß dann die Suche erst ab Level n beginnen. Stehen beispielsweise 16k Speicherentries zur Verfügung reduziert sich die Suchtiefe um 14. Alternativ hierzu sind in den 16k DirectMappings auch alle möglichen Entries des Levels n+1 speicherbar. Die Suchtiefe reduziert sich dann um 15; bei einer Suche oberhalb von Level 15 beginnt die Suche bei der Ur- wurzel .Since the arrangement is sorted, the upper part of the search tree can be mapped directly in a RAM (random access memory) area. With 2 Λ n entries, the search only has to start at level n. If, for example, 16k memory entries are available, the search depth is reduced by 14. Alternatively, all possible entries of level n + 1 can also be stored in the 16k DirectMappings. The search depth is then reduced by 15; if you search above level 15, the search starts at the root.
Eine weitere Möglichkeit zur Beschleunigung des Suchvorganges ist dadurch gegeben, daß das Suchprinzip auf mehr als 2 Pointer erweitert wird. Bei Verwendung von zweckmäßigerweise 2X Pointern ergibt sich eine Baumhöhe von H=log2M/i.Another way to speed up the search process is to extend the search principle to more than 2 pointers. When using 2X pointers appropriately, a tree height of H = log 2 M / i results.
Fig 7 zeigt eine Hardwarerealisierung für eine Suche mit 4 Pointern, bei der es nicht zwingend notwendig ist, die Poin- terwerte an den Vergleicher heranzuführen.7 shows a hardware implementation for a search with 4 pointers, in which it is not absolutely necessary to bring the pointer values to the comparator.
Ein Entry-RAM wird über einen Tristate Bus von genau der Pointer RAM aus einer Mehrzahl von Pointer RAM's (Pointer 1 RAM ..Pointer i RAM) adressiert, deren Ausgang über ein Chip- Selekt - Signal wirksamgeschaltet ist. Liegen P_upper und P_lower in der selben Pointer RAM, womit keine Selektion eines Tristate Busses über Chipselekt möglich ist, kann ein externer Multiplexer vorgesehen sein. Der Ausgang des Entry-RAM ist mit dem Vergleicher verbunden.An entry RAM is addressed via a tristate bus by exactly the pointer RAM from a plurality of pointer RAMs (pointer 1 RAM .. pointer i RAM), the output of which is activated via a chip select signal. If P_upper and P_lower are in the same pointer RAM, which means that it is not possible to select a tristate bus via chip select, an external multiplexer can be provided. The output of the entry RAM is connected to the comparator.
Beispiel: stehen wie bei STMl 64 Takte zur Auflösung eines Entries aus 8k möglichen zur Verfügung, so kann dies durch Verwendung eines 1Mbit RAMs 32k*32 erreicht werden. In 16k stehen 32k DirectMappings zur Verfügung (2 Takte) ; Reduzierung der Suchtiefe um 15. Bei 3 Zugriffen zur Bewertung des Entries (Anlegen Adresse; Lesen Entry; Lesen Pointer) werden für die Suche in 17 Level 16*3=51 Takte benötig. Verbindungs- aufbau und Abbau ist in Leerzyklen möglich, maximal sollten hierfür 51+2+3=56 Takte erforderlich sein. Example: As with STMl, 64 cycles are available for resolving an entry from 8k possible, this can be achieved by using a 1Mbit RAM 32k * 32. In 16k 32k DirectMappings are available (2 cycles); Reduction of the search depth by 15. With 3 accesses to evaluate the entry (create address; read entry; read pointer), the search in 17 levels requires 16 * 3 = 51 cycles. Connection establishment and disconnection is possible in empty cycles, a maximum of 51 + 2 + 3 = 56 cycles should be required.

Claims

Patentansprüche claims
1. Verfahren zum Aufsuchen einer Adresse in einem teilbesetzten, nicht-balancierten Binären Baum, demzufolge - mit jedem gültigen Eintrag in einem Suchbaum mindestens zwei Zeiger (pointer lower, pointer upper) abspeicherbar sind, die jeweils auf einen gültigen Eintrag einer tieferen Ebene (level 0, I, II, III, IV) verweisen1.Procedure for finding an address in a partially populated, unbalanced binary tree, according to which - with each valid entry in a search tree, at least two pointers (pointer lower, pointer upper) can be stored, each of which points to a valid entry at a lower level (level 0, I, II, III, IV) refer
- bei Erreichung eines Eintrags in einer Ebene nach Maßgabe des Vergleichsergebnisses zwischen gesuchter Adresse und vorliegenden Zeigern in Richtung auf den gesuchten Eintrag zu einem Eintrag der nächst tieferen Ebene verzweigt wird- When an entry is reached in one level in accordance with the comparison result between the searched address and the pointers in the direction of the searched entry, an entry to the next lower level is branched off
- parallel mit dem Verzweigungsvorgang zu einem Eintrag in die nächst tiefere Ebene ein Vergleich des Eintrags mit der gesuchten Adresse auf Übereinstimmung durchgeführt wird.- In parallel with the branching process to an entry in the next lower level, a comparison of the entry with the searched address is carried out for agreement.
2 . Verfahren nach Anspruch 1 , d a d u r c h g e k e n n z e i c h n e t , dass in der ersten Ebene (level 0) eine Verzweigung nach Maß- gäbe der ersten Bitstelle der gesuchten Adresse erfolgt.2nd A method according to claim 1, so that a branching takes place in the first level (level 0) in accordance with the first bit position of the searched address.
3. Verfahren nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, dass3. The method according to any one of the preceding claims, characterized in that
- die Einträge der ersten Ebene (level 0) und sich daran an- schließender Ebenen (level I, II...) in einem Bereich des- the entries of the first level (level 0) and subsequent levels (level I, II ...) in an area of the
RAM-Speichers gemappt werdenRAM memory can be mapped
- bei der Suche nach einer Adresse geprüft wird, ob sie sich in einer tieferen Ebene als der, für die die Einträge gemappt sind, befindet und gegebenenfalls in der entsprechen- den Wurzel weitergesucht wird- When searching for an address, a check is carried out to determine whether it is at a lower level than the one for which the entries are mapped and whether it is searched for in the corresponding root, if necessary
- andernfalls die Suche in der Urwurzel begonnen wird.- otherwise the search is started in the root.
4. Verfahren nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, dass für jeden Eintrag mehr als zwei Zeiger abspeicherbar sind. 4. The method according to any one of the preceding claims, characterized in that more than two pointers can be stored for each entry.
PCT/DE1998/002550 1997-09-30 1998-08-31 Method of address search in an unbalanced and partly occupied binary tree WO1999017225A1 (en)

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