WO1999014884A3 - Configuration de circuit et procede de correction d'erreur sans circuit de retour - Google Patents

Configuration de circuit et procede de correction d'erreur sans circuit de retour Download PDF

Info

Publication number
WO1999014884A3
WO1999014884A3 PCT/DE1998/002743 DE9802743W WO9914884A3 WO 1999014884 A3 WO1999014884 A3 WO 1999014884A3 DE 9802743 W DE9802743 W DE 9802743W WO 9914884 A3 WO9914884 A3 WO 9914884A3
Authority
WO
WIPO (PCT)
Prior art keywords
error correction
forward error
circuit
hierarchical system
digital synchronous
Prior art date
Application number
PCT/DE1998/002743
Other languages
German (de)
English (en)
Other versions
WO1999014884A2 (fr
Inventor
Detlef Stoll
Original Assignee
Siemens Ag
Detlef Stoll
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Detlef Stoll filed Critical Siemens Ag
Priority to CA002304249A priority Critical patent/CA2304249A1/fr
Priority to JP2000512306A priority patent/JP2001517019A/ja
Publication of WO1999014884A2 publication Critical patent/WO1999014884A2/fr
Publication of WO1999014884A3 publication Critical patent/WO1999014884A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Pour permettre la correction d'erreur sans circuit de retour dans les systèmes de transport de données, les données d'un cadre de transport sont regroupées en blocs de correction d'erreur et des éléments binaires de parité prévus à cet effet: Ces éléments binaires de parité sont ensuite intégrés à un secteur libre de surdébit de section du même bloc de correction d'erreur.
PCT/DE1998/002743 1997-09-17 1998-09-16 Configuration de circuit et procede de correction d'erreur sans circuit de retour WO1999014884A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002304249A CA2304249A1 (fr) 1997-09-17 1998-09-16 Configuration de circuit et procede pour faire suivre la correction d'erreur
JP2000512306A JP2001517019A (ja) 1997-09-17 1998-09-16 フォワード順方向誤り補正回路装置及び方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19740935.0 1997-09-17
DE1997140935 DE19740935A1 (de) 1997-09-17 1997-09-17 Schaltungsanordnung und Verfahren zur Vorwärtsfehlerkorrektur

Publications (2)

Publication Number Publication Date
WO1999014884A2 WO1999014884A2 (fr) 1999-03-25
WO1999014884A3 true WO1999014884A3 (fr) 1999-06-17

Family

ID=7842677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/002743 WO1999014884A2 (fr) 1997-09-17 1998-09-16 Configuration de circuit et procede de correction d'erreur sans circuit de retour

Country Status (4)

Country Link
JP (1) JP2001517019A (fr)
CA (1) CA2304249A1 (fr)
DE (1) DE19740935A1 (fr)
WO (1) WO1999014884A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6683855B1 (en) * 1998-08-31 2004-01-27 Lucent Technologies Inc. Forward error correction for high speed optical transmission systems
DE102008004728A1 (de) 2008-01-16 2009-07-23 Henkel Ag & Co. Kgaa Phosphatiertes Stahlblech sowie Verfahren zur Herstellung eines solchen Blechs

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
GROVER W D ET AL: "DESIGN AND CHARACTERIZATION OF AN ERROR-CORRECTING CODE FOR THE SONET STS-1 TRIBUTARY", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 38, no. 4, 1 April 1990 (1990-04-01), pages 467 - 476, XP000136588 *
PAXAL V ET AL: "ERROR-CORRECTION CODING FOR HIGH-SPEED OPTICAL TRANSMISSION SYSTEMS BASED ON THE SYNCHRONOUS DIGITAL HIERARCHY", EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS AND RELATED TECHNOLOGIES, vol. 4, no. 6, 1 November 1993 (1993-11-01), pages 623 - 628, XP000433719 *
SEOK CHANG KIM ET AL: "PARALLEL SHIFT REGISTER GENERATORS: THEORY AND APPLICATIONS TO PARALLEL SCRAMBLING IN MULTIBIT-INTERLEAVED MULTIPLEXING ENVIRONMENTS", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 43, no. 2/04, PART 03, 1 February 1995 (1995-02-01), pages 1844 - 1853, XP000505657 *
TOMIZAWA M ET AL: "FORWARD ERROR CORRECTING CODES IN SYNCHRONOUS FIBER OPTIC TRANSMISSION SYSTEMS", JOURNAL OF LIGHTWAVE TECHNOLOGY, vol. 15, no. 1, January 1997 (1997-01-01), pages 43 - 51, XP000642276 *

Also Published As

Publication number Publication date
WO1999014884A2 (fr) 1999-03-25
DE19740935A1 (de) 1999-04-08
JP2001517019A (ja) 2001-10-02
CA2304249A1 (fr) 1999-03-25

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