WO1999009687A1 - Systeme et dispositif permettant de generer et de commander les signaux de synchronisation - Google Patents

Systeme et dispositif permettant de generer et de commander les signaux de synchronisation Download PDF

Info

Publication number
WO1999009687A1
WO1999009687A1 PCT/US1998/015975 US9815975W WO9909687A1 WO 1999009687 A1 WO1999009687 A1 WO 1999009687A1 US 9815975 W US9815975 W US 9815975W WO 9909687 A1 WO9909687 A1 WO 9909687A1
Authority
WO
WIPO (PCT)
Prior art keywords
timing
signal
circuit
network
timing signal
Prior art date
Application number
PCT/US1998/015975
Other languages
English (en)
Inventor
James H. Bond
David J. Streett
Dwight W. Doss
Original Assignee
Alcatel Usa Sourcing, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Usa Sourcing, L.P. filed Critical Alcatel Usa Sourcing, L.P.
Priority to AU86793/98A priority Critical patent/AU8679398A/en
Publication of WO1999009687A1 publication Critical patent/WO1999009687A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node

Definitions

  • the present invention relates in general to telecommunications data switching and more particularly to a system and apparatus for generating and controlling a timing signal for use with telecommunications equipment.
  • Modern telecommunications systems typically use digitally encoded data instead of analog data. If analog data is used, it is converted to digital data for the purposes of switching the data between conducting media. Switching of data occurs at large telecommunications switches, which may receive and process hundreds or thousands of data channels. Large telecommunications switches usually comprise a large number of devices. For example, a large telecommunications switch may require conductor interfaces, data transmission components, control system components, administration system components, data processing components, and switching matrix components. In order for the large telecommunications switch to function properly, it is necessary to accurately synchronize each component of the switch with the other components.
  • a large telecommunications switch is used in conjunction with a telecommunications network, such as the public switched telecommunications network.
  • the telecommunications signals transferred over such telecommunications networks may be synchronized, such that any components that interact with the network must also be synchronized with the network signals.
  • a system and apparatus for timing signal generation and control is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed timing signal generators.
  • the timing generator includes clock circuitry for generating a local timing signal.
  • Network timing interface circuitry is connected to the clock circuitry and receives a network timing signal.
  • the network timing signal is transmitted to the clock circuitry, which outputs the local timing signal when the clock circuitry and the network timing signal are synchronized.
  • Switch timing output circuitry coupled to the clock circuitry receives the local timing signal and generates a switch timing output signal.
  • Timing generator that is operable to receive an optical network timing signal and to generate a system timing signal for use by a telecommunications switch.
  • the timing generator also generates an optical system timing signal for use by other components, and an optical system timing signal test signal that allows the accuracy of the timing signal to be tested while the system is in use.
  • Another advantage of the present invention is a system for timing generation that derives a timing signal from a plurality of optical network interfaces.
  • the system selects one of the optical network timing signals, and synchronizes a timing signal from the local oscillator with the selected optical network timing signal.
  • FIGURE 1 illustrates a fiber optic termination module for a telecommunications switch embodying concepts of the present invention
  • FIGURE 2 is a diagram of a system for timing signal generation embodying concepts of the present invention
  • FIGURE 3 is a diagram of a system timing generator circuit embodying concepts of the present invention.
  • FIGURE 4 is a flow chart of a method for generating a timing signal embodying concepts of the present invention.
  • FIGURE 1 is a system diagram of optical fiber-capable telecommunications switch system 10.
  • Optical fiber-capable telecommunications switch system 10 includes switch 12 connected to fiber optic connection unit 14 and common controller 16.
  • Optical telecommunications data channels such as a stream of bit-serial data, byte-serial data, or serial frames of data, are received and transmitted over one or more fiber optic conductors 18 at fiber optic connection unit 14. These telecommunications data channels are converted to electrical signals by fiber optic connection unit 14 and are transmitted to switch 12 for switching between data channels.
  • Switch 12 may switch data channels of any suitable size, such as DSO, DS1, DS3, or other suitable channels.
  • Common controller 16 receives control data from and transmits control data to fiber optic connection unit 14 and switch 12.
  • Switch 12 is a telecommunications switch having M input channels and N output channels, where M and N are integers. Switch 12 receives telecommunications data at any of the M input channels and transfers the telecommunications data to any of the N output channels.
  • Switch 12, as shown in FIGURE 1, is a digital switch, but may also be an analog switch.
  • Switch 12 may include, for example, a Megahub 600E Digital Telecommunications Switch manufactured by DSC Communications Corporation of Piano, Texas.
  • Switch 12 includes a message transport network 20 coupled to a matrix data multiplexer circuit (MDM) 22, a matrix control path verification processor (PVP) 24, a line trunk manager circuit (LTM) 26, administration circuit (ADMIN) 28, timing generator circuit (TG) 30, and Ethernet network circuit (ENC) 32.
  • MDM matrix data multiplexer circuit
  • PVP matrix control path verification processor
  • LTM line trunk manager circuit
  • ADMIN administration circuit
  • TG timing generator circuit
  • ENC Ethernet network circuit
  • Matrix data multiplexer circuit 22 is further coupled to matrix control path verification processor 24 and timing generator circuit 30.
  • Matrix data multiplexer circuit 22 is an interface circuit that may be used for coupling data channels between fiber optic connection unit 14 and the switching matrix (not explicitly shown) of switch 12.
  • matrix data multiplexer circuit 22 provides the interface for DSO data.
  • Matrix data multiplexer circuit 22 receives 2048 channels of DSO data from fiber optic connection unit 14 on a 10-bit parallel data channel operating at a frequency of 16.384 MHZ. These DSO data channels are then transmitted to the M input ports of the switching matrix of switch 12.
  • Control commands received at switch 12 from common controller 16 are used to determine the proper connections between the M input ports and the N output ports of the switching matrix.
  • the DSO data channels are transmitted through the switching matrix after the connections have been formed.
  • the DSO data channels received at matrix data multiplexer circuit 22 from the N output ports of the switching matrix are then transmitted back to fiber optic connection unit 14.
  • Matrix control path verification processor 24 is coupled to fiber optic connection unit 14 and to message transport network 20.
  • Matrix control path verification processor 24 is a switching matrix administration and control component that processes matrix channel low level fault detection and fault isolation data.
  • Line trunk manager circuit 26 is coupled to fiber optic connection unit 14 and message transport network 20.
  • Line trunk manager circuit 26 is a switching matrix control component that receives and transmits data relating to call processing functions for fiber optic connection unit 14.
  • Timing generator circuit 30 is coupled to matrix data multiplexer circuit 22 and common controller 16. Timing generator circuit 30 is a switch timing circuit that receives timing data from an external source, such as fiber optic connection unit 14, and transmits the timing data to components of switch 12.
  • Ethernet network circuit 32 is coupled to message transport network 20 and common controller 16.
  • Ethernet network circuit 32 is a data communications interface, and transfers data between message transport network 20 and common controller 16.
  • Fiber optic connection unit 14 includes an optical interface circuit 40, application circuits (AC) 42, a bus control circuit 44, a matrix interface circuit (MIF) 46, a tone recognition circuit (TONE) 48, and a high speed line trunk processor circuit (LTP) 50.
  • Fiber optic connection unit 14 receives digitally encoded optical data from fiber optic conductor 18, performs broadcast switching of the data channels received from fiber optic conductor 18, transmits synchronous transfer mode (STM) telecommunication data to matrix data multiplexer circuit 22 and matrix control path verification processor 24 for switching through the switching matrix of switch 12, and receives the switched telecommunications data from switch 12 for transmission over fiber optic conductor 18.
  • STM synchronous transfer mode
  • Optical interface circuit 40 is capable of terminating optical signals carrying external data, for example SONET or SDH, connected to the public switched network (PSN) .
  • Optical interface circuit 40 receives digitally encoded optical telecommunications data from fiber optic conductor 18 and converts the optical signals into electrical signals, for example STS-1, for transmission to other components of fiber optic connection unit 14.
  • Optical interface circuit 40 is coupled to fiber optic conductor 18 and to application circuits 42.
  • Optical interface circuit 40 may include a single circuit card with electronic circuit subcomponents (not explicitly shown) that have plug-in connectors to allow the card to be easily installed in a cabinet containing other component circuit cards of fiber optic connection unit 14.
  • optical interface circuit 40 may include two or more circuit cards, or one or more discrete components on a circuit card.
  • Application circuits 42 are telecommunications data transmission system components which are coupled to bus control circuit 44. Each application circuit 42 may have a separate circuit card (not explicitly shown) with plug-in connectors in order to be easily installed in a rack containing fiber optic connection unit 14. Alternatively, application circuits 42 may include multiple circuit cards, or individual components on a single circuit card.
  • application circuits 42 are configured to receive data from and transmit data to optical interface circuit 40.
  • This data may comprise synchronous transfer mode telecommunications data.
  • application circuits 42 may receive a single STS-1 channel of data that includes a plurality of DSO data channels, where each DSO data channel is a continuous stream of data equal to 64,000 bits per second. This data would be received in a predetermined format.
  • Application circuits 42 may also receive asynchronous transfer mode (ATM) telecommunications data.
  • Asynchronous transfer mode data may be transmitted as a single channel of fixed bit format data frames that comprise additional channels of data.
  • the number of data frames transmitted per second for a given data channel may be varied for asynchronous transfer mode data m order to accommodate fluctuations in the amount of data per channel and the number of data channels transferred.
  • Bus control circuit 44 may be coupled to a number of other application circuits with more specific functions, such as matrix interface circuit 46, tone recognition circuit 48, and high speed line trunk processor circuit 50. Nevertheless, the common characteristic of application circuits 42 is that they are operable to transmit data to bus control circuit 44 over ingress buses 60 and to receive data from bus control circuit 44 over egress buses 62.
  • Bus control circuit 44 receives telecommunications data from applications circuits 42 over ingress buses 60, multiplexes the data into a single broadcast data channel, and transmits the broadcast data channel over egress buses 62. In this manner, bus control circuit 44 also operates as a broadcast switching device. Each application circuit 42 receives the broadcast data channel containing data from other application circuits, and can then process the data or transfer the data back to optical interface circuit 40 for transmission on fiber optic conductor 18 to the network.
  • Bus control circuit 44 may be a separate circuit card with plug-in connectors m order to be easily used m a rack containing fiber optic connection unit 14. Alternatively, bus control circuit 44 may include multiple circuit cards, or individual components on a single circuit card.
  • Matrix interface circuit 46 provides the protocol and transport format conversion between fiber optic interface circuit 14 and switch 12.
  • Matrix interface circuit 46 is an application circuit that is used to transmit data received from the broadcast data channel transmitted by bus control circuit 44 to switch 12.
  • Matrix interface circuit 46 is coupled to bus control circuit 44, matrix data multiplexer circuit 22, and matrix control path verification processor 24.
  • Matrix interface circuit 46 converts the data format of the broadcast data channel received from bus control circuit 44 and switch 12 into a data format that is compatible with switch 12 and bus control circuit 44, respectively.
  • Matrix interface circuit 46 may be a separate circuit card with plug-m connectors in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, matrix interface circuit 46 may include multiple circuit cards, or individual components on a single circuit card.
  • Tone recognition circuit 48 is an application circuit that is coupled to bus control circuit 44 and performs tone recognition functions for fiber optic connection unit 14. One pair of tone recognition circuits 48 may be required for every 2016 matrix ports of switch 12. Tone recognition circuit 48 interfaces with the broadcast data channel and detects data representative of keypad tones on each DSO channel that comprises the broadcast data channel, up to the maximum of 2016 DSO data channels.
  • Tone recognition circuit 48 has an array of digital signal processor devices (not explicitly shown) that can be configured to provide tone detection and generation. Tone recognition circuit 48 may be a separate circuit card with plug-in connectors in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, tone recognition circuit 48 may include multiple circuit cards, or individual components on a single circuit card.
  • High speed line trunk processor circuit 50 is the primary shelf controller for all of the circuit cards in fiber optic connection unit 14 and provides the interface for call control between fiber optic connection unit 14 and switch 12.
  • High speed line trunk processor circuit 50 contains a microprocessor, a communications interface to all circuit cards of fiber optic connection unit 14, and a communications interface to line trunk manager circuit 26.
  • High speed line trunk processor circuit 50 may be embodied as a separate circuit card with plug-in connectors in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, high speed line trunk processor circuit 50 may be multiple circuit cards, or individual components on a single circuit card.
  • Ingress buses 60 are data buses that are operable to carry a data channel with a predetermined bit structure and at a predetermined frequency from an application card to bus control circuit 44.
  • each ingress bus 60 may comprise a single data channel with 8 parallel bits operating at a frequency of 25.92 MHZ. Other bit structures and frequencies may be used where suitable.
  • Egress buses 62 are data buses that are operable to carry a data channel with a predetermined bit structure and at a predetermined frequency to an application card from bus control circuit 44.
  • each egress bus 62 may comprise a single data channel with 16 parallel bits operating at a frequency of 51.84 MHZ. Other bit structures and frequencies may be used where suitable.
  • Common controller 16 is coupled to switch 12 and fiber optic connection unit 14.
  • Common controller 16 is a processor that receives administration, control, and routing data from switch 12 and fiber optic connection unit 14, and generates administration, control and routing data that coordinates the operation of switch 12 and fiber optic connection unit 14.
  • Common controller 16 may alternatively be incorporated within switch 12 or fiber optic connection unit 14.
  • telecommunications data from the network is transmitted via fiber optic conductor 18 and received by fiber optic connection unit 14.
  • This telecommunications data is then converted into electrical signals and transmitted through optical interface circuit 40 to application circuit 42 for broadcast switching through bus control circuit 44.
  • the broadcast data is then switched back to application circuit 42 for retransmission through fiber optic conductor 18 via optical interface circuit 40.
  • the broadcast data may also be received by matrix interface circuit 46, tone recognition circuit 48, high speed line trunk processor circuit 50, or other suitable circuits to perform specific functions thereon.
  • Application circuits 42 are operable to receive the broadcast data and to selectively retransmit all or a portion of the data through optical interface circuit 40 to fiber optic conductor 18. In this manner, switching of telecommunications data received from fiber optic conductor 18 may be accomplished by bus control circuit 44 without the need for transmitting the data to switch 12 for switching.
  • FIGURE 2 is a diagram of a system 80 for timing signal generation embodying concepts of the present invention.
  • System 80 comprises application circuits (AC1 through ACN) 42, which receive network signals 82 and derive the network timing signal from the network signals 82.
  • Application circuits 42 are coupled to bus control circuits (BC) 44 and transmit the derived network timing signals to bus control circuits 44.
  • Bus control circuits 44 select one of the network timing signals received from application circuits 42 in response to administration and control system data and transmit the selected network timing signal to a clock distribution circuit (CD) 84.
  • CD clock distribution circuit
  • Clock distribution circuits 84 are timing system components that are operable to receive and transmit timing signals to system components. Each clock distribution circuit 84 is coupled to a redundant clock distribution circuit 84, to a bus control circuit 44, and to both system timing generator circuits (STGS) 86. Clock distribution circuit 84 may comprise a separate circuit card with plug- in connectors in order to be easily used in a rack containing fiber optic connection unit 14. Alternatively, clock distribution circuit 84 may comprise multiple circuit cards, or individual components on a single circuit card. The network timing signal received at each clock distribution circuit 84 is also transmitted to the redundant clock distribution circuit 84. One of the network timing signals received at clock distribution circuits 84 is selected as the primary network timing signal, and is transmitted to each of two redundant system timing generator circuits 86. Up to sixteen pairs of signals from clock distribution circuits 84 may be received by system timing generator circuits 86.
  • System timing generator circuits 86 are timing generation circuits that are operable to receive external timing signals, to select one of the external timing signals as the primary external timing signal, to synchronize the external timing signal to an internal high- accuracy time signal generator, and to output a local timing signal that may be used for switch timing, auxiliary timing, timing signal testing, and other suitable purposes.
  • Each system timing generator circuit 86 may comprise a separate circuit card with plug-in connectors in order to be easily used in a rack containing fiber optic connection unit 14 or switch 12. Alternatively, each system timing generator circuit 86 may comprise multiple circuit cards, or individual components on a single circuit card.
  • the local timing signal generated by each system timing generator circuit 86 is output to the mate system timing generator circuit 86, and one of the redundant local timing signals is selected as the primary local timing signal.
  • the primary local timing signal is then transmitted back to each clock distribution circuit 84, which transmits the primary local timing signal to each bus control circuit 44.
  • the bus control circuits 44 synchronize the broadcast data signals to the primary local timing signal and transmit the broadcast data signals to each application circuit 42 over egress buses 62.
  • network data signals are received at application circuits 42, which derive the network timing signal from the network data signal and transmit the network timing signal to bus control circuits 44.
  • Bus control circuits 44 select one of the redundant network timing signals to be the primary network timing signal, and transmit that primary network timing signal to the redundant clock distribution circuits 84.
  • One of the primary network timing signals received at the redundant clock distribution circuits 84 is then selected for transmission to system timing generator circuits 86, which synchronize the local oscillator to the primary network timing signal.
  • the local timing signal is then transmitted to the mate system timing generator circuit 86.
  • One of the redundant local timing signals is selected as the primary local timing signal, and is transmitted to the clock distribution circuits 84, the bus control circuits 44, and eventually to the application circuits 42.
  • FIGURE 3 is a diagram of a system timing generator circuit 100 embodying concepts of the present invention.
  • System timing generator circuit 86 may be identical to system timing generator circuit 100, or may alternatively be other suitable timing circuits.
  • Each system timing generator circuit 100 may comprise a separate circuit card with plug-in connectors in order to be easily used in a rack containing fiber optic connection unit 14 or switch 12. Alternatively, each system timing generator circuit 100 may comprise multiple circuit cards, or individual components on a single circuit card.
  • a plurality of primary network timing signals such as 6.48 MHz signals received from clock distribution circuits 84, are received at redundant selector circuits (SEL) 102. Redundant selector circuits 102 select one of the primary network timing signals as the derived timing signal and transmit the derived timing signal to redundant timing derivation circuits (TDC) 104.
  • Timing derivation circuits 104 receive the derived timing signal and transmit the derived timing signal to clock circuit (CLOCK) 106 through selector circuit (SEL) 124 and divider circuits (/N) 126. The divided network timing signal is also transmitted to selector circuit (SEL) 108.
  • Clock circuit 106 comprises a high accuracy clock, such as STRATUM 3E clock. The output of clock circuit 106 is frequency locked to the derived timing signal received at clock circuit 106. The output of clock circuit 106 is selected by selector circuit 108 only when the clock output of clock circuit 106 is frequency locked to the derived timing signal.
  • Selector circuit 108 is used to controllably select between the output of clock circuit 106, either of the two derived timing signals from divider circuits 126, and the timing signal received from the redundant parallel system timing generator circuits 100.
  • the selected reference clock signal is provided to phase locked loop (PLL) 110 and phase locked loop (PLL) 112, which generate a 16.384 MHz and a 12.960 MHz frequency reference signal, respectively.
  • the frequency reference signals are provided to clock set driver circuit (CSD) 114, which provides a signal output and a framing signal to the redundant system timing generator circuit 100, to a telecommunications switch timing system input of matrix 12, and to clock distribution circuits 84.
  • CSD clock set driver circuit
  • the signal provided to the redundant system timing generator circuit 100 allows both system timing generator circuits to be aligned within several nanoseconds of each other. If the system timing generator circuit 100 selected as the primary timing generator circuit is disabled, the switchover to the redundant system timing generator circuit 100 occurs without any interruption in the delivery of the timing signal. Control of the dynamic alignment of the redundant system timing generator circuits 100 is provided by processor 134.
  • the local timing signal provided to clock distribution circuits 84 is an optical frame timing signal output that is used to align optical frames transmitted by fiber optic connection unit 14, and an optical system timing signal output that is used by the components of fiber optic connection unit 14 to synchronize their operation.
  • Clock set driver circuit 114 comprises a plurality of data frame output ports, each data frame output port operable to transmit a switch timing output signal.
  • redundant selector circuits 102 The output of redundant selector circuits 102 is also provided to redundant selector circuits (SEL) 130 through redundant divider circuits (/N) 128. Redundant selector circuits also receive clock signals from the mate system timing generator circuit 100, and from the output of clock circuit 106.
  • the local clock signal output from redundant selector circuits 130 is provided to redundant network clock signal drivers (CSD) 132. Clock signal drivers 132 provide a phase locked loop circuit that outputs a signal that is locked to the local clock signal.
  • the clock signal output from one of redundant network clock signal drivers 132 is an optical system timing signal output that may be provided to other local telecommunications components.
  • the clock signal output from the second network clock signal driver 132 is an optical system timing signal test signal that may be used to test the accuracy of clock circuit 106 while system timing generator circuit 100 is in operation.
  • Clock signal drivers 132 also output a DS1 and El signal.
  • system timing generator circuit 100 may also receive timing signals from redundant Loran C or Cesium beam sinewave circuits (SINE) 116, redundant Tl span circuits (DS1) 118, redundant El span circuits (El) 120, or redundant 8 kHz signals derived from Tl trunk circuits (8kHz) 122. Any of these additional signals may be used to provide a reference frequency by sending an appropriate control command to selector circuit 124 from microprocessor (PROC) 134.
  • SINE Loran C or Cesium beam sinewave circuits
  • DS1 redundant Tl span circuits
  • El redundant El span circuits
  • 8 kHz signals derived from Tl trunk circuits
  • Microprocessor 134 is a processor that is operable to receive and process data and control commands from the components of system timing generator circuit 100 over bus 150, and to transmit data and control commands over bus 150 to the components of system timing generator circuit 100. Microprocessor 134 also performs dynamic alignment of the redundant system timing generator circuits 100, and also processes synchronization status messages retrieved from SONET overhead, the DS1 Tl span, and other suitable sources. Microprocessor 134 may be, for example, a Motorola MPC860 processor, or other suitable processors. Microprocessor 134 receives control commands and control data over redundant ethernet interfaces (El) 138 or other suitable communications interfaces from common controller 16.
  • El redundant ethernet interfaces
  • Microprocessor 134 also receives control commands and control data from serial management controller interface (MCI) port 136 and distributed self-diagnostics circuitry (DI) 140. Status and alarm signals may be transmitted to and received from status and alarm circuitry (S&AC) 142.
  • Arbitration circuitry (ARB) 144 receives data and control commands from microprocessor 134 and provides control commands to selector circuit 108.
  • Time of day interrupt circuit (TOD) 146 receives timing data from the output of selector circuit 108, and transmits time of day interrupt signals to microprocessor 134 over bus 150.
  • Microprocessor 134 is also operable to transmit commands over bus 150 to selector circuits 102, 124, and 130.
  • timing signals are derived from network data signals received over fiber optic conductor 18 of FIGURE 1.
  • One of these derived timing signals is selected by bus control module 44 and is transmitted to clock distribution circuits 84.
  • Up to sixteen clock distribution circuit pairs 84 may provide input to system timing generator circuits 86, which provide the system timing signals for switch 12 and fiber optic connection unit 14.
  • One of the signals received from clock distribution circuits 84 is synchronized with a local Stratum 3E oscillator in clock circuit 106 to generate a local timing signal.
  • This local timing signal is then distributed back to components of switch 14 and fiber optic connection unit 14, such as through clock distribution circuits 84 and bus control circuits 44.
  • FIGURE 4 is a flow chart of a method 170 for generating a timing signal in accordance with the present invention.
  • Method 170 begins at step 172, where network timing signals are received at a system timing generator circuit from clock distribution circuits. At step 174, one of the network timing signals is selected as the derived timing signal, based upon synchronization status messages encoded in the network timing signals or other suitable methods . At step 176, it is determined whether a control command has been received to use the derived timing signal. If the derived network timing signal is selected, the method proceeds to step 178, where the derived network timing signal is transmitted through the selector circuit to a clock circuit. In addition, the derived network timing signal is also transmitted to the network timing output selector circuit at step 180. The method then proceeds to step 184.
  • an alternate external timing signal may be transmitted through the selector circuit to the clock circuit.
  • a clock circuit received from a Tl telephone line, a Loran C or Cesium beam sinewave, or other suitable timing signals may be used. The method then proceeds to step 184.
  • a high accuracy local oscillator circuit is frequency locked to the timing signal received at the clock circuit.
  • the system timing generator circuit attempts to switch to the redundant system timing generator circuit. If the redundant system timing generator circuit is available, the transfer occurs without interruption of service because the two redundant system timing generator circuit timing signals are maintained withm several nanoseconds of each other by a local microprocessor controller. The method then proceeds to step 196, where the timing signal is transmitted to the clock distribution circuits .
  • step 192 it is determined whether the primary timing generator circuit can generate a timing signal based upon a holdover frequency.
  • the holdover frequency circuit is operable to maintain the frequency of the network timing signal or other applied timing signal after that signal is lost. If the holdover timing signal is available, the method proceeds to step 196 where the holdover frequency is transmitted to the clock distribution circuits.
  • a controller may monitor synchronization status messages included withm network data signals to determine if the loss of frequency lock is due to problems with the received timing signal. If other received timing signals are available, the system timing generator circuit may attempt to lock to one of these other received timing signals while the system is in holdover. If the holdover circuit loses accuracy or is unavailable, the method proceeds to step 194. At step 194, the network timing signal or other timing signal, if available, may be selected for transmission to the clock distribution circuits and to input circuitry for a telecommunications switch timing system. The method then proceeds to step 196. If no holdover source is available, the method terminates at step 198.
  • step 196 the selected timing signal is transmitted to the clock distribution circuits.
  • the method then returns periodically to step 190, to check for availability of either redundant timing generator circuit, the holdover signal, or the alternate source.
  • step 186 the method proceeds to step 200, where a local timing signal is generated by the clock circuit.
  • step 202 the local timing signal is transmitted to the clock distribution circuits and to the telecommunications switch timing system inputs.
  • the local timing signal may be transmitted to a network timing signal output of the system timing generator circuit, or to a timing signal test circuit.
  • network data signals are received at a telecommunications switching system, such as at an optical connection module.
  • a representative network data signal is then transmitted to a clock distribution circuit, which provides the data signal to a system timing generator circuit.
  • the system timing generator circuit receives data signals from up to sixteen pairs of clock distribution circuits, and derives a network timing signal from a representative data signal.
  • a high accuracy local oscillator is then synchronized with the network timing signal to create a local timing signal.
  • This local timing signal is then transmitted to the clock distribution circuits, and is also made available at a local timing signal output for additional applications that may require a local timing signal.
  • a local timing signal test output is also provided that allows the high accuracy local oscillator to be tested while the system is in operation.
  • Timing generator that is operable to receive an optical network timing signal and to generate a local timing signal for use by a telecommunications switch.
  • Another advantage of the present invention is a system for timing generation that allows the accuracy of the timing signal to be tested while the system is in operation without disturbing network traffic .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un générateur de synchronisation (86, 100) destiné à un système de communication de données. Le générateur (86, 100) comprend un circuit d'horloge (106) qui génère un signal de synchronisation locale. Un circuit d'interface de synchronisation de réseau (104), connecté au circuit d'horloge (106), reçoit un signal de synchronisation de réseau. Le signal de synchronisation de réseau est transmis au circuit d'horloge (106), qui génère le signal de synchronisation locale. Un circuit de sortie de synchronisation de commutation (114, 132), couplé au circuit de synchronisation (106), reçoit le signal de synchronisation locale et génère un signal de sortie de synchronisation de commutation.
PCT/US1998/015975 1997-08-13 1998-07-30 Systeme et dispositif permettant de generer et de commander les signaux de synchronisation WO1999009687A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU86793/98A AU8679398A (en) 1997-08-13 1998-07-30 System and apparatus for timing signal generation and control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US91069897A 1997-08-13 1997-08-13
US08/910,698 1997-08-13

Publications (1)

Publication Number Publication Date
WO1999009687A1 true WO1999009687A1 (fr) 1999-02-25

Family

ID=25429197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/015975 WO1999009687A1 (fr) 1997-08-13 1998-07-30 Systeme et dispositif permettant de generer et de commander les signaux de synchronisation

Country Status (5)

Country Link
AR (1) AR013943A1 (fr)
AU (1) AU8679398A (fr)
CO (1) CO4790201A1 (fr)
PE (1) PE103299A1 (fr)
WO (1) WO1999009687A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170907B1 (en) 2002-02-15 2007-01-30 Marvell Semiconductor Israel Ltd. Dynamic alignment for data on a parallel bus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0316228A1 (fr) * 1987-11-09 1989-05-17 Js Telecommunications Circuit de base de temps
EP0368123A1 (fr) * 1988-11-03 1990-05-16 Alcatel Business Systems Agencement de synchronisation pour autocommutateur numérique privé raccordé à un réseau RNIS
WO1995018514A1 (fr) * 1993-12-30 1995-07-06 Dsc Communications Corporation Systeme d'interconnexion multicadence integre
US5577075A (en) * 1991-09-26 1996-11-19 Ipc Information Systems, Inc. Distributed clocking system
WO1997012457A2 (fr) * 1995-09-29 1997-04-03 Telefonaktiebolaget Lm Ericsson (Publ) Utilisation et entretien de reseaux de distribution de signaux d'horloge ayant une redondance

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0316228A1 (fr) * 1987-11-09 1989-05-17 Js Telecommunications Circuit de base de temps
EP0368123A1 (fr) * 1988-11-03 1990-05-16 Alcatel Business Systems Agencement de synchronisation pour autocommutateur numérique privé raccordé à un réseau RNIS
US5577075A (en) * 1991-09-26 1996-11-19 Ipc Information Systems, Inc. Distributed clocking system
WO1995018514A1 (fr) * 1993-12-30 1995-07-06 Dsc Communications Corporation Systeme d'interconnexion multicadence integre
WO1997012457A2 (fr) * 1995-09-29 1997-04-03 Telefonaktiebolaget Lm Ericsson (Publ) Utilisation et entretien de reseaux de distribution de signaux d'horloge ayant une redondance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170907B1 (en) 2002-02-15 2007-01-30 Marvell Semiconductor Israel Ltd. Dynamic alignment for data on a parallel bus
US7664146B1 (en) 2002-02-15 2010-02-16 Marvell Israel (M.I.S.L.) Ltd. Dynamic alignment for data on a parallel bus

Also Published As

Publication number Publication date
PE103299A1 (es) 1999-10-24
CO4790201A1 (es) 1999-05-31
AU8679398A (en) 1999-03-08
AR013943A1 (es) 2001-01-31

Similar Documents

Publication Publication Date Title
EP0559090B1 (fr) Element de réseau comprenant une matrice d'interconnexion et un serveur
US5926303A (en) System and apparatus for optical fiber interface
US5901136A (en) System and method for controlling timing in a distributed digital cross-connect system
US7463626B2 (en) Phase and frequency drift and jitter compensation in a distributed telecommunications switch
US6320877B1 (en) System and method for data bus interface
US6816818B2 (en) Method, clock generator module and receiver module for synchronizing a receiver module
WO1999018698A1 (fr) Systeme et dispositif de commande d'un bus de telecommunications
US7110353B1 (en) Distributed digital cross-connect system and method
WO1997016047A1 (fr) Systeme de transconnexion numerique a bande large
CA2357944A1 (fr) Systeme et methode de commande multilogement pour element de reseau
US7653052B2 (en) System and method for a control services link for a multi-shelf node in a communication switch
US6246681B1 (en) System and method for plane selection
US6044088A (en) System and circuit for telecommunications data conversion
US6285687B1 (en) Timing system and method for distributing a timing signal
WO1999018753A1 (fr) Systeme et dispositif destines a une interface de bus de donnees
CA2274068C (fr) Systeme et procede de controle de synchronisation dans un systeme brasseur-repartiteur numerique distribue
WO1999009687A1 (fr) Systeme et dispositif permettant de generer et de commander les signaux de synchronisation
US7613164B2 (en) Method and apparatus for generating and distributing an internal clock for radio network controller
WO2003081818A1 (fr) Gestion simplifiee de largeur de bande pour hierarchie numerique synchrone/reseau optique synchrone (hns/sonet)
KR100256691B1 (ko) 임의 조합의 종속신호를 수용하는 광전송 장치
GB2213024A (en) Data transmission system
EP0638223B1 (fr) Procede et agencement de connexion tranversale pour une commutation exempte d'erreurs d'une matrice de connexion transversale
EP0950334B1 (fr) Repartiteur numerique distribue et procede
KR19980061853A (ko) 전전자 교환기의 망동기 장치 시험 장치
KR0153951B1 (ko) 비동기 전달모드 기준클럭을 이용한 일반 전화 서비스용 클럭 발생 장치

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
NENP Non-entry into the national phase

Ref country code: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA