WO1999005791A1

WO1999005791A1 - Signal clamping circuit with level shifting and error detection for multiple inputs

Info

Publication number: WO1999005791A1
Application number: PCT/US1998/015060
Authority: WO
Inventors: Calvin C. Perkins; Terry L. Wetherbee; David D. Bie
Original assignee: Mackie Designs Inc.
Priority date: 1997-07-22
Filing date: 1998-07-21
Publication date: 1999-02-04
Also published as: AU8503998A

Abstract

An electronic circuit for keeping a transistor (236) from saturating while minimizing the time required for the transistor to transition between a conducting state and non-conducting state by having an open-loop clamping circuit (D1) connected between a first terminal of the transistor (C) and a first voltage source (+VCC), wherein the clamping circuit (D1) is operable in a first mode to isolate the first signal terminal (C) from the first voltage source (+VCC) and in a second mode to present an impedance between the first terminal (C) and the first voltage source (+VCC) to limit the voltage on the first signal terminal (C) to a selected value.

Description

SIGNAL CLAMPING CIRCUIT WITH LEVEL SHIFTING AND ERROR DETECTION FOR MULTIPLE INPUTS

Related Application

This application is a continuation-in-part of and claims priority of U.S. provisional application Serial No. 60/053,361, filed July 22, 1997, entitled "Output Signal Clamping Circuit With Level Shifting and Error Detection for Multiple Inputs."

Field Of The Invention

The present invention generally relates to an apparatus and a method for improving the switching speed of a transistor, and more specifically, to the use of clamping circuitry to prevent a transistor in a large signal drive stage of an audio amplifier from reaching a saturation voltage.

Background Of The Invention

A significant limitation on the performance of a high speed electronic circuit is the relatively long "on-to-off time delay that occurs when the voltage drop across a transistor reaches an intrinsic saturation voltage. Also, a saturated transistor tends to behave in a non-linear fashion, i.e., the transistor's output signal will deviate from an ideal scaled input signal. However, there are several measures in the prior art that have been taken to circumvent the problems caused by transistor saturation. One prior art solution to this problem is to insure that the potential across a transistor never reaches a saturation voltage. For example, a "Baker Clamp" can be employed to prevent a transistor from reaching its saturation voltage by coupling a

SUBSTITUTE SHEET (RULE 25) "clamping" diode from the base to the collector of the transistor. This technique was originally developed to improve the switching speed for digital circuits, but has also found use in high speed analog circuit designs. The basic concept of the Baker Clamp is to shunt current away from the base when the collector is nearing saturation, so that the forward voltage drop across the transistor will always be less than the voltage drop across the collector-base junction.

An electronic circuit 10 that uses a simple version of a Baker Clamp is shown in FIGURE 1. A cathode of a diode 12 is coupled to a collector of an NPN transistor 16, which forms an output node 18. An input node 19 is coupled to an anode of diode 12 and an anode of a diode 14. The cathode of diode 14 is connected to a base of transistor 16. An emitter of transistor 16 is connected to a common ground 17. The base-emitter voltage drop (V_be) is about 0.5 volts for transistor 16, which is approximately equal to a forward biased voltage drop (V_D) of 0.65 volts. Thus, when the value of a signal at input node 19 reaches the amplitude of the two forward biased diode voltage drops (V_be+ V_D), transistor 16 will start to conduct.

When transistor 16 is conducting, the voltage at output node 18 will try to drop to the characteristic saturation voltage of the transistor. Typically, this saturation voltage is a function of the current and the design of the device and is usually less then 0.5 volts, or typically 0.1-0.3 volts. If the voltage at the collector drops below the voltage applied to the base, the collector-to-base region of transistor 16 will no longer be reverse biased, which is a condition necessary for proper operation of the transistor. However, since the voltage drop across diodes 12 and 14 is essentially the same, and the base voltage is clamped at the value of two forward biased diode voltage drops, the voltage drop across diode 12 insures that the collector voltage will never drop below the base voltage. Additionally, the current supplied to diodes 12 and 14 is provided by the same input signal. As transistor 16 approaches a saturation voltage, diode 12 will start conducting, which will provide a shunt through the collector for the input signal current. By applying Kirchoff s voltage law around the base-emitter and collector-emitter loops, it can be shown that V_CE=V_BE+V₁₄-V₁₂ because V₁₂=V_I4 and V_CE=V_BE. Therefore, a current feedback loop that supplies the correct amount of input signal current to the base of transistor 16 is provided by the Baker Clamp to maintain a constant on-state voltage, while preventing the transistor from saturating.

In FIGURE IB, a graph 20 of the input signal voltage (along a y-axis 22) vs. time (along an x-axis 24) is illustrated. Starting at time equal to zero, the input voltage has a zero value until at time t₀, a rising edge 26 transitions into a step waveform 28, which lasts until a time t„ when a falling edge 30 returns the input voltage to a zero value. In FIGURE 1C, a graph 32 of the output signal voltage (along a y-axis 34) is displayed relative to time (along an x-axis 36). The output voltage level is at V_out from time zero until time t₀, which lasts until a time t,. At time t„ a rising edge 44 returns the output voltage to V_out. The voltage level across the base- emitter for the inverse step waveform 40 is greater than a saturation voltage 42, as shown in the Figure.

A conventional Baker Clamp introduces a slight delay in the on-to-off transition times. In FIGURE 2A, an electronic circuit that provides fast on-to-off transition times is shown. An input 48 is coupled to an anode of a diode 52, and anode of a diode 54, and a cathode of a diode 56. A cathode of diode 54 and an anode of diode 56 are coupled to a base of an NPN transistor 57. A cathode of diode 52 is coupled to a collector of transistor 57 and to an output 50. An emitter of transistor 57 is connected to a common ground 58. Diode 54 and diode 56 provide bi-directional current flow into and out of the base of transistor 57. A turn-on voltage for transistor 57 is provided by a positive signal at input 48, and a turn-off voltage is produced by a negative signal. When the value of the input signal is negative, diode 56 will conduct and provide a path to discharge any internal built-up electrical charge in the capacitance of the base-emitter junction of transistor 57, which was stored during the conduction (on state) of the transistor.

FIGURE 2B is a graph 60 of the input signal waveform over time. The input voltage is along a y-axis 62 and time is indicated along an x-axis 64. Beginning at a time equal to zero, an input signal is represented by a negative level 66 until a time t₀, when a rising edge 68 transitions the signal to a positive step waveform 70. At a time t„ a falling edge 72 transitions the input signal to negative level 66. FIGURE 2C illustrates a graph 74 showing an output voltage along a y-axis 76 and time along an x-axis 78. Starting at time zero, the signal has a positive level 80 until a time t₀, when a falling edge 82 transitions the value of the output signal to an inverse step waveform 86 corresponds to the value of the base-emitter voltage (V_be). Also, the value of the base-emitter voltage is clearly more positive than a saturation voltage level 88.

FIGURE 3A illustrates a side-by-side comparison of the difference between the turn-on and turn-off times for both the input and output voltage signals of circuit 10 (shown in FIGURE 1A). A graph 90 displays the input voltage signal along a y- axis 92 and time along an x-axis 94. The input signal has a zero voltage level 96 until time t_on, when a rising edge 98 transitions the signal to a positive step waveform 100. At time t_off, a falling edge 102 returns the value of the input signal to zero voltage level 96.

A graph 104 in FIGURE 3 A displays the output voltage signal along a y-axis 106 and time along an x-axis 108. The output voltage signal has a positive level 110 until a time t₀, when a falling edge 112 transitions to an inverted (but positive level) step waveform 114 that has a magnitude equal to the base-emitter voltage (V_be) of transistor 16. Moving from time t_ofT, the value of the output signal, increases slightly along a slope 116 that continues until the end of a storage time period t_s. Next, the value of the output signal ramps up along a slope 118 over a time t_f, at which the signal is again at level 110.

For comparison to FIGURE 3 A, in FIGURE 3B, the turn-on and turn-off times are illustrated for both the input and output voltage signals of circuit 46 (shown in FIGURE 2A). A graph 120 plots the input voltage along a y-axis 120 and time along an x-axis 126, until at time t_on, a rising edge 128 transitions the value of the signal to a positive step waveform 130. Next, at time t_off, a falling edge 132 transitions the input signal back to negative level 126.

A graph 134 in FIGURE 3B illustrates the value of the output voltage along a y-axis 136 and time along an x-axis 138. From a time equal to zero, the value of the output signal is at a positive level 140, until a time t_on, when a falling edge 142 transitions the signal to an inverse step waveform 144, which has a value equal to the base-emitter voltage (V_be) of transistor 57. At a time t_off, the value of the output signal rises slightly along a slope 146 for a storage time period t_s. At the end of the storage time, the output signal rises rapidly along a ramp 148 until a time t_f, when the signal is again at positive level 140.

In FIGURE 3 A, a comparison of graph 90 and graph 104 illustrates the relationship between the input and output signals of circuit 10. It is important to note that the output signal closely follows the transitions of the input signal when moving from an off state to an on state., However, the output signal experiences two relatively long time delays before completing the on-to-off transition. During the first time period or delay (t_s), the built-up electrical charge in the base emitter junction is being discharged by transistor 10. Once most of the stored electrical charge has drained away, transistor 16 begins the transition (ramp) from a conductive (on) to a non-conductive (off) state. The time period or delay for this on to off ramp is known in the art as the fall time t_f of a transistor.

By contrast, in FIGURE 3B, the comparison of graph 120 and graph 134 for the input and output signals, respectively, shows that the use of a negative reverse bias turn-off input voltage and the disposition of diode 56 between the base and input 48 considerably shorten the amount of time for both the storage and fall times for transistor 57. A reduction in both the storage and fall time periods has determine the maximum operating frequency of the circuit. In large signal audio amplifiers, reliability and sonic performance is negatively impacted by relatively long storage and fall times.

FIGURE 4 shows a graph 150 that plots the relationship between the output voltage (V_ce) of a transistor (shown along a y-axis 152) as a function of base input current (show along an x-axis 154). As the input current to the base increases, the output voltage falls to a uniform voltage that is then independent of the input current - for a clamped signal 158. For a non-clamped signal 156, the output voltage continues to fall until it reaches a potential below that of the transistor's base. FIGURE 5 displays the storage time of a transistor (along a y-axis 162) as a function of input base current (along an x-axis 164). AS the input current to the base increases, the storage time increases linearly for a clamped signal 166, but increases almost exponentially for a non-clamped signal 168. FIGURE 6 shows the fall time of a transistor (along a y-axis 172) as function of input base current (along an x-axis 174). As the input current to the base increases, the fall time remains almost constant for a clamped signal 176, but increase almost exponentially for a non-clamped signal 178. Therefore, it is quite evident from FIGURES 4, 5, and 6 that clamping the voltage across a transistor so that the saturation voltage does not occur decreases the time for the transistor to switch from the conductive (on) to the non-conductive (off) state.

In large signal audio amplifiers, any time delays incurred by internal transistor stages switching from on-to-off are exacerbated by the use of negative feedback. Negative feedback is used in approximately 99% of all large signal audio amplifiers, because it provides an inexpensive method for stabilizing the operating point of internal circuitry and reduces distortion in the outputted signal. In FIGURE 7, three different cases showing the output signals of large signal audio amplifier as a function of time are illustrated. Graph 180 shows an output voltage signal comprising an undipped high frequency sine wave 183. Output voltage is indicated along a y-axis 182 and time and phase are indicated along an x-axis 184.

Graph 187 illustrates the effect of applying a Baker Clamp to the circuitry of the amplifier. Output voltage is indicated along a y-axis 186 and time along an x-axis 188. A sine wave output voltage signal 185 displays "clean" clipping of the positive and negative peaks of the signal, which are "flat topped" because the output signal of the amplifier cannot track the full amplitude of the signal being input. An amplifier's output voltage swing is always limited by the rails of the amplifier's power supply. It should also be noted that a time interval t, is symmetrically centered on the 90° and

270° points of signal 185, which indicates that there is no appreciable turn-off delay.

A graph 191 illustrates the clipping that occurs when an output voltage signal clamp is not used in the circuitry of an amplifier. The output voltage is indicated along a y-axis 190 and time and phase are indicated along an x-axis 192. An asymmetric clipped sine wave 189 is shown in graph 191. The time interval t₂ following the 90° and 270° points is considerably longer than time t, before these points, and the waveform is not as cleanly clipped as waveform 185, which is shown in graph 187. After a finite storage delay time t₂ there is an abrupt transition or notch 193 in the negative direction for the positive-going half of the sine wave. The converse is also true for the negative portion of the waveform. This phenomena is commonly referred to as "sticking." Any delay in the turn-off time of the amplifier circuitry has a deleterious effect on reliability, because the amplifier's output stage will transition into a state referred to as common mode conduction. When output stage transistors enter the region of common mode conduction catastrophic destruction of the devices can occur. Additionally, a non- linear clipped signal causes the amplifier to produce an intermodulation spectra that is very audible and undesirable when heard on a loudspeaker. In the prior art, Baker Clamps are often employed in the manner illustrated in

FIGURE 8. In this Figure, an electronic circuit 194 is shown that uses a typical implementation of a Baker Clamp in a large signal drive stage of a power amplifier. In particular, diodes 202 and 204 are used as the Baker Clamp for the negative output. These Baker Clamps operate in substantially the same manner as discussed for circuit 10 above.

From the foregoing, it will be apparent that a clamping circuit for use with large signal amplifiers is required that does not introduce unacceptable delay, i.e., a circuit that provides for fast turn on and turn off times relative to the input signal. The simple prior art Baker Clamp does not meet this requirement.

Summary Of The Invention

According to one aspect of the present invention, an open-loop clamping circuit prevents saturation of a transistor in an audio amplifier. It is desirable to prevent saturation of such transistors due, in part, to the increased turn off time of a saturated transistor. The clamping circuit is coupled between a signal terminal of the transistor and a first voltage source, and operates in a first mode during small signal swings on the first signal terminal to isolate the first signal terminal from the first voltage source. During large signal swings on the first signal terminal, the clamping circuit presents a low impedance between the first signal terminal, limiting the voltage on the first signal terminal to a predetermined value to prevent saturation of the transistor. The clamping circuit enables the transistor to turn off in a reduced time relative to transistors that use negative current feedback to prevent saturation, and may be utilized in a variety of audio amplifier configurations and with different transistor types. According to another aspect of the present invention, the total harmonic distortion (THD) of the audio amplifier introduced by the clamping circuit may be shifted beyond the audible frequency range of human hearing, effectively eliminating the deleterious effects of such THD.

According to further aspects of the invention, audio amplifiers including level shifting, error detection, and multiple inputs for the large signal drive stages are provided.

Brief Description Of The Drawings

The objects and features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The present invention, both as to its organization and manner of operation, together with further objects and advantages, may best be understood by reference to the following description, taken in connection with the accompanying drawings, in which:

FIGURE 1A (PRIOR ART) is a schematic diagram of an electronic circuit employing a Baker Clamp; FIGURE 1 A is a graph of input voltage versus time for the electronic circuit using the Baker Clamp;

FIGURE 1C is a graph of output voltage versus time for the electronic circuit using the Baker Clamp; FIGURE 2A is a schematic diagram of a clamp electronic circuit that provides a more rapid turn-off than a simple Baker Clamp;

FIGURE 2B is a graph of input voltage versus time for the electronic circuit of FIGURE 2A; FIGURE 2C is a graph of output voltage versus time for the electronic circuit of FIGURE 2A;

FIGURE 3 A is a graphical comparison of input voltage versus time and output voltage versus time and output voltage versus time for the prior art electronic circuit using the Baker Clamp shown in FIGURE 1 A; FIGURE 3B is a graphical comparison of input voltage versus time and output voltage versus time for the clamp electronic circuit of FIGURE 2A;

FIGURE 4 is a graph of output voltage versus input current for a clamped and an undamped output voltage signal;

FIGURE 5 is a graph of storage time versus input current for a clamped and an undamped output voltage signal;

FIGURE 6 is a graph of fall time versus input current for a clamped and an undamped output voltage signal;

FIGURE 7 is a graphical comparison of the output voltage signal as a function of time for an undistorted sine wave produced by an amplifier, a clipped sine wave produced by an amplifier that is controlled by a Baker Clamp, and a clipped asymmetric sine wave that is produced by an amplifier that is not controlled by a

Baker Clamp;

FIGURE 8 (PRIOR ART) is a schematic diagram of an electronic circuit that employs a Baker Clamp and is used in the voltage drive stage of a power amplifier; FIGURE 9 is a schematic diagram of an electronic circuit in accord with the present invention, for use in the drive stage of a power amplifier;

FIGURE 10 is a schematic diagram of an alternative embodiment (the positive half) for an electronic circuit in accord with the present invention, which is intended for use in the large signal drive of a power amplifier; FIGURE 11 is a schematic diagram of another embodiment of an electronic circuit n accord with the present invention;

FIGURE 12A includes a plurality of graphs illustrating the performance of the preferred embodiment of FIGURE 11 for positive signal swings; and FIGURE 12B includes a plurality of graphs illustrating the performance of the preferred embodiment of FIGURE 11 for negative signal swings.

Description Of The Preferred Embodiments

A clamping circuit, and in particular, an open-loop clamping circuit is described in detail below. In the following description, numerous specific details are set forth, such as wave forms, applications in an audio amplifier, etc., to provide a thorough understanding of the invention. One skilled in the relevant art will readily recognize that the invention can be practiced without one or more of the specific details, or with other wave forms, applications, etc. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention.

In FIGURE 9, a circuit 230 illustrates a first preferred embodiment of the present invention for implementing the desired functionality of a Baker Clamp, and which does not employ the current feedback loop taught in the prior art. In the positive half of circuit 230, and input resistor 232 has one end coupled a varying input signal source and the other end coupled to a resistor 234 and a power supply that has a voltage Vcc equal to +10 volts. The other end of resistor 234 is coupled to the emitter of a PNP transistor 236. The base of transistor 236 is coupled to the node between resistor 232 and the input signal source. The collector of transistor 236 is connected to the anode of a diode 238 whose cathode is coupled to another power supply that has an output voltage equal to Vcc. Also, the collector of transistor 236 is coupled to the anode of a diode 240, which has its cathode coupled to the anode of a diode 242. The cathode of diode 242 and the anode of a diode 246 are connected to a positive drive output 244, which is coupled to output transistors (not shown). The cathode of diode 246 is connected to the anode of a diode 248, which has its cathode coupled to the anode of a diode 250. The cathode of diode 250 is connected to the anode of a diode 252, having a cathode coupled to the anode of a diode 258 and a negative drive output 256, which is connected to the output transistors (not shown). Significantly, diodes 246, 248, 250, and 252 collectively provide a biasing circuit 254 between the positive and negative halves of circuit 230. The physical configuration of the negative half of circuit 230 is substantially similar to the positive half discussed above. However, a diode 262 couples -Vcc to the collector of a transistor 268, and a resistor 266 couples the emitter of the transistor to - Vcc.

Instead of employing a current feedback loop to clamp the voltage drop (V_be) across a transistor, circuit 230 clamps the voltage with diode 238 and diode 262 that are coupled to the collectors of transistor 236 and a transistor 268, respectively. For small signal swings, both diode 238 and diode 262 are reverse biased and do not affect the performance of the circuit. However, at high frequencies, the diode junction capacitance begins to introduce high frequency non-linearities, as evidenced by an increase in the total harmonic distortion for circuit 230. Further, when large signal swings occur, the maximum peak values of the output signal voltage at the collectors of transistors 236 and 268 are limited to one diode drop voltage (approximately 0.65 volts) above and below their power supply voltages of a +Vcc and a -Vcc, respectively. To prevent the loss of maximum output signal swing capability (as determined by the primary supply voltages set by a positive Vcc and negative Vcc) two additional "boosted" power supply voltages are added, which are typically set from 5 to 15 volts above the primary supply voltages. In FIGURE 9, these supplies are labeled +Vcc (+10 V) and -Vcc (-10 V), respectively.

The maximum positive signal swing at the collector of transistor 236 is +Vcc + V₂₃₈ and the maximum negative signal swing at the collector of transistor 268 is - Vcc-V₂₆₂. Analyzing the positive half of circuit 230 only, the collector to emitter voltage of transistor 236 is set by the relationship V_ce=(Vcc+10V)-(V_rN-V_be). The maximum value of V_m occurs during high frequency slewing or during severe input overdrive. During these aforementioned conditions, Y_m is double its quiescent value. Under the worst case conditions, the operating points are chosen such that V_ce is never less than 2.5 volts, which insures that there is no stored electrical charge in transistor 236. Diodes 240 and 242 limit the positive drive to the output transistors (not shown) to a finite value of one diode voltage drop below the power supply and prevent output stage saturation. Under voltage clamping conditions, power dissipation in transistor 236 is well within the safe operating limits of the device. The same analysis applies to the negative half of circuit 230, which supports the operation of transistor 268.

In FIGURE 10, a positive half 270 of another embodiment that implements the functionality of circuit 230, but which incorporates additional circuitry for enhanced functionality, is displayed. In this embodiment, the cathode of diode 238 is connected to the emitter of a PNP transistor 274 having a base that is coupled +Vcc. The collector is coupled to one end of a limit resistor 276, which has its other end coupled to a sense resistor 278. The other end of sense resistor 278 is coupled to ground. Significantly, the maximum positive output voltage signal swing at the collector of transistor 236 is effectively clamped at a value of two diode voltage drops above +Vcc (V ₃₈ ⁺V_be27 ⁼l-3 volts). To compensate for the increase in the output voltage signal, the anode of a diode 272 is coupled to the cathode of diode 242 and the cathode of diode 272 both to positive drive output 244 and the anode of diode 246. In this way, the operation for the negative half of the circuit is substantially the same except that the polarities are reversed for the added components (added relative to the embodiment of FIGURE 9).

Diode 238 is connected to the emitter of transistor 274, and their total junction capacitance is less than the capacitance of diode 238 alone. Also, junction capacitance is non-linear and will vary as a one-third power of the applied voltage. Further, the changes in the junction capacitance of diode 238 will cause the Total Harmonic Distortion (THD) to increase at higher frequencies because the modulated junction capacitance impresses a non-linear load on transistor 236. The addition of transistor 274 effectively moves any distortion cause by these non-linearities above 20 kHz, which is beyond the audible range of human hearing. The use of transistor 274 as an additional diode junction in series with diode 238 also enables the level shifting of the clamped portion of the signal to another point of reference (in this particular case, ground). The level shifted error signal may be used for additional signal processing, such as gain reduction or signal status indication. During normal operation, a portion of the signal current (I_q) will split at the collector of transistor 236 into branches (I_Q3 and I_QB). One branch of current (I_Q3) flows through transistor 274, which operates as a common base amplifier, to ground through sense resistor 278. A corresponding voltage drop (V_sense) is developed, which is limited to an arbitrary value by the voltage division ratio established by limit resistor 276 and sense resistor 278. An error signal is thus produced with a finite predetermined amplitude, and the error signal is pulse width modulated by the percentage of time that the voltage clamp is active. In other words, the duty cycle of the pulse width modulated detected error signal of transistor 274 accurately mirrors the percentage of time that the output signal is clipped. FIGURE 11 shows a preferred embodiment of the present invention that provides for simultaneously clamping the output signal, level shifting, and detecting any form of a bipolar DC or AC clipped signal waveform. As discussed above, diode 238 and transistor 274 perform the functions of clamping and level shifting for positive output signal swings. In similar fashion, diode 262 and a transistor 284 perform the same functions for negative output signal swings. When the positive output signal swing (+_e0) ^at the collector of transistor 236 exceeds +Vcc by the voltage drop of diode 238 and transistor 274, transistor 274 will start to conduct and develop a pulse width modulated voltage drop across limit resistor 276 and sense resistor 278. Limit resistor 276 provides power dissipation limiting for transistor 274. The voltage drop across sense resistor 278 is limited to the forward bias "on" voltage of a diode 296. Similarly, diode 262, transistor 284, a limit resistor 286, a sense resistor 288, and a diode 298 provide the same functionality for negative output voltage signal swings for generating a negative pulse width modulated signal across sense resistor 288. Also, since level shifting is accomplished via collector outputs (common nodes of transistor 274) and a transistor 290 or transistor 284 and a transistor 306), it is easy to sum multiple channels into one sensing loop if desired. This summation property is highly desirable in products that utilize multi-way power amplification, so that a real time indication of a clipped output signal can be provided and the gain of the output signal can be controlled. For example, a bi-amplified, two- way amplified speaker system could use the sum peak detection to trigger an overload status light and/or initiate gain reduction. In FIGURE 11, the combination of two channels is done by the collector OR'ing of transistor 274 and transistor 290 for positive clipping detection, and of transistor 284 and transistor 306, for negative clipping detection. A comparator 304 is used to detect either the positive or negative error

(clipping) signals generated by the clamping action. An end of resistor 294 is coupled to a power supply having a voltage signal equal to +15 volts. The other end of resistor 294 is coupled to the end of limit resistor 276, which is also coupled to the anode of diode 296 and to an end of sense resistor 278. Resistor 294 biases the voltage at the coupling of the anode of diode 296 and the end of sense resistor 278 to a voltage level below the turn-on voltage of diode 296. In this case, the voltage bias level is equal to about -300mV. In similar fashion, a resistor 302 biases the voltage at the coupling of sense resistor 288 and diode 298 to a value equal to about +300mV. Thus, a negative bias voltage is impressed at the negative input of comparator 304, together with a positive bias voltage presented at the positive input, which causes the comparator's output to be high (+14 volts) during quiescent conditions. Additionally, if there is a positive signal detected by comparator 304, which occurs when the voltage +_eo exceeds +Vcc by approximately 1.2 volts, transistor 274 will conduct. When transistor 274 conducts, the voltage at the negative input to the comparator will increase from about -300mV to about +0.65 volts, while the positive input to the comparator stays the same (about -300m V). The normally high comparator output voltage (typically one to two volts below the comparator's power supply voltage), changes state to a negative output voltage for the duration of the clamped (limited) signal. Second negative and positive channel inputs are also provided by the preferred embodiment. In the positive half of circuit 300, a collector of transistor 290 is coupled to the collector of transistor 274 and an end of limit resistor 276. The emitter of transistor 290 is connected to the cathode of a diode 292, and the base of transistor 290 is coupled to +Vcc. The base of transistor 274 is also coupled to +Vcc. Accordingly, the anode of diode 292 is provided couple to a second positive channel input. Except for the polarities being reversed, the negative half of circuit 300 incorporates the multiple channel circuitry of the positive half in substantially the same manner and provides for the same functionality. In FIGURE 12 A, an example of a signal detected by the present invention for positive signal swings is illustrated with a plurality of graphs. A graph 310 shows an undamped sine wave output voltage signal 316 with a positive value of +_eυ. The output voltage is indicated along a y-axis 312 and time is indicated along an x-axis 314. In a graph 320, there is no positive current (+ ) flowing. Further, current is indicated along a y-axis 318 and time along an x-axis 322. A graph 324 displays a sine wave output voltage signal 328 that has a value of +_eβ, which has exceeded +Vcc by at least the voltage drop across diode 238 and the V_be voltage of transistor 274. A flat top 329 further illustrates that the maximum limit has been reached, because the top of the sine wave is cleanly clipped by the action of the clamping circuitry. During the time duration of the clamping action, graph 338 shows the maximum positive current +i flowing through transistor 274. Current is disposed along a y-axis 332 and time is indicated along an x-axis 334. The peak value of the positive current +/. The peak value of voltage +_eo developed by +/^' at the positive input of comparator 304 is limited by the voltage drop across diode 296. In a graph 341, the value of the pre-established bias voltage at the negative input of comparator 304 is shown changing in value from -300mV to +0.65 volts. A y-axis 340 ranges between +e and -e, and time is indicated along an x-axis 342. Starting at a time zero, a waveform 344 representing a -V_B biasing voltage transitions to a positive step waveform 346 during the time period associated with the maximum positive current +i flowing through transistor 274. A graph 351, shows the voltage E_out changing from a value of +14 volts to- 14volts when comparator 304 changes state. Voltage is indicated along a y-axis 348 and time is indicated along an x-axis 350. From a time zero, a positive level 352 that represents the output of comparator 304 has a value of about +14 volts and transitions to an inverse step waveform 344 that has a value of -14 volts during the period of time that the maximum positive current + is flowing through transistor 274.

In FIGURE 12B, an example of a signal detected for negative output signal swings is illustrated with a plurality of graphs. A graph 356 shows an undamped sine wave signal 362 having a maximum negative voltage -_eQ of a sine wave signal 378 that has exceeded -Vcc by the voltage drop across diode 262 and the V_be voltage of transistor 284. A flat top 380 on the negative portion of sine wave 378 shows that the maximum negative voltage limit has been exceeded because the top has been cleanly clipped by the action of the clamping circuitry.

During the time duration of the clamping action, a graph 382 shows the maximum negative current -i that flows through transistor 284. The peak value of -/ is set by the value of a -Vcc and by the total resistance of limit resistor 286 and sense resistor 288. Current is indicated along a y-axis 384 and time is indicated along an x- axis 386. The peak value of -e developed by - at the positive input of comparator 304 is limited by the voltage drop across diode 298. In a graph 392, voltage is indicated along a y-axis 394 and time along an x- axis 396. The value of the pre-established biasing voltage +V_B at the positive input of comparator 304 can change in value from about +300mV to about -0.65 volts. Starting at a time equal to zero, a positive level 398 having a value of V_B transitions to an inverse step waveform 400 that has a value of -e during the period of time that a maximum negative current - flows through transistor 284.

A graph 402, shows the voltage E_out changing from a value of +14 volts to -14 volts when comparator 304 changes state in accord with the period of time that a maximum negative current -i is flowing through transistor 284. Voltage is indicated along a y-axis 404 and time is indicated along an x-axis 406. Starting at time equal to zero, a positive level 408 that has a value of +14 volts transitions to an inverse step waveform 410 having a value of -14 volts during the period of time that the maximum negative current -i is flowing. Significantly, the detection and clamping of either the negative or positive output signal swings will result in the same pulse modulated signal, which can be used for control purposes.

Claims

1. An open-loop clamping circuit for preventing saturation of a transistor in an audio amplifier, the transistor having a control terminal and first and second signal terminals and the clamping circuit being coupled between the first signal terminal and a first voltage source, the clamping circuit operable in a first mode to isolate the first signal terminal from the first voltage source, and operable in a second mode to present an impedance between the first signal terminal to limit the voltage on the first signal terminal to a selected value.

2. The clamping circuit of claim 1 comprising a diode having its cathode coupled to the first voltage source and anode coupled to the first signal terminal.

3. The clamping circuit of claim 1 comprising: a diode having an anode coupled to the first signal terminal and a cathode; and another transistor having a first signal terminal coupled to the cathode, a second signal terminal coupled to a second voltage source, and a control terminal adapted to receive a third voltage source.

4. The clamping circuit of claim 1 wherein the transistor is an NPN bipolar junction transistor.

5. An audio amplifier, comprising: a first transistor having a control terminal adapted to receive a first input signal, a first signal terminal coupled to a first positive voltage source, and a second signal terminal; a first clamping circuit coupled between the second signal terminal and a second positive voltage source, the first clamping circuit operable in a first mode to isolate the second signal terminal from the second positive voltage source, and operable in a second mode to present an impedance between the second signal terminal and the second positive voltage source to limit the voltage on the second signal terminal to a predetermined value; a first limiting circuit coupled between the second signal terminal and a first output node and operable to limit the voltage on the first output node relative to the second positive voltage source; a bias circuit coupled between the first output node and a second output node; a second transistor having a control terminal adapted to receive a second input signal, a first signal terminal coupled to a first negative voltage source, and a second signal terminal; a second clamping circuit coupled between the second signal terminal of the second transistor and a second negative voltage source, the second clamping circuit operable in a first mode to isolate the second signal terminal from the second negative voltage source, and operable in a second mode to present an impedance between the second signal terminal and the second negative voltage source to limit the voltage on the second signal terminal to a predetermined value; and a second limiting circuit coupled between the second signal terminal of the second transistor and the second output node and operable to limit the voltage on the second output node relative to the second negative voltage source.

6. The audio amplifier of claim 5 wherein the first and second clamping circuits are respective diodes.

7. The audio amplifier of claim 5 wherein the first transistor is a PNP bipolar transistor and the second transistor is an NPN bipolar transistor.

8. The audio amplifier of claim 5 wherein the bias circuit comprises a plurality of diodes connected in series.

9. The audio amplifier of claim 5 wherein the first and second limiting circuits each comprise a plurality of diodes connected in series.