WO1999003237A1 - Cellule mta augmentee de donnees tampon - Google Patents

Cellule mta augmentee de donnees tampon Download PDF

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Publication number
WO1999003237A1
WO1999003237A1 PCT/SE1998/001288 SE9801288W WO9903237A1 WO 1999003237 A1 WO1999003237 A1 WO 1999003237A1 SE 9801288 W SE9801288 W SE 9801288W WO 9903237 A1 WO9903237 A1 WO 9903237A1
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WO
WIPO (PCT)
Prior art keywords
cell
atm cell
switch
atm
buffer circuit
Prior art date
Application number
PCT/SE1998/001288
Other languages
English (en)
Inventor
Gunnar Larsson
Clarence Fransson
Raimo Sissonen
Original Assignee
Telefonaktiebolaget Lm Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Priority to JP2000502606A priority Critical patent/JP2001510303A/ja
Priority to GB0000450A priority patent/GB2342811B/en
Priority to AU83626/98A priority patent/AU8362698A/en
Publication of WO1999003237A1 publication Critical patent/WO1999003237A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H04L49/203—ATM switching fabrics with multicast or broadcast capabilities
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/505—Corrective measures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags

Definitions

  • This invention pertains to telecommunications, and particularly to the handling of cells in a switching node of a telecommunications network operating in the asynchronous transfer mode.
  • B- ISDN Broadband .Integrated Service JDigital Network
  • ATM Asynchronous Transfer Mode
  • Packets are called cells and have a fixed size.
  • An ATM cell consists of 53 octets, five of which form a header and forty eight of which constitute a payload"S or information portion of the cell.
  • the header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier) .
  • VPI Virtual Path Identifier
  • VCI Virtual Channel Identifier
  • the virtual path is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
  • an ATM network is connected to terminal equipment, e.g., ATM network users.
  • Switches Between ATM network termination points are a plurality of switching nodes (e.g., ATM switches) having ports which are connected together by physical transmission paths. In traveling from an origin terminal equipment to a destination terminal equipment, ATM cells forming a message may travel through several switching nodes.
  • switching nodes e.g., ATM switches
  • the switching nodes each typically have several functional parts, including a switch core.
  • the switch core essentially functions like a cross-connect between ports of the switch.
  • the switch core includes space switching circuits which, based on routing information, send incoming cells of a message through the switch core to an intended output port.
  • the switching nodes facilitate travel of the cells of the message from the originating terminal equipment ultimately to the destination terminal equipment.
  • Port connection e.g., routing through the switch core
  • functions such as address translation, policing, buffering, etc.
  • Data necessary for performing these other functions must be available (e.g., by table lookup) to constituent components of the ATM switch.
  • functions of the switch are generally distributed to a plurality of circuits.
  • a conventional ATM switch upon arrival of a ATM cell at the switch the VPI/VCI quantities in the ATM cell header and link identification information are utilized in a table look-up operation (e.g., by a first cell-handling circuit of the switch) to obtain both a routing tag and an internal channel number for use in the switch.
  • the routing tag and internal channel number are then added to the ATM cell for use in other ones of the plurality of circuits in the switch.
  • the internal channel number is used for further table-look up operations involving external memory.
  • the routing tag is used for further table-look up operations involving internal (e.g., on chip) or external memory.
  • table lookups have to be performed in several circuits.
  • the number of look-up operations essentially increases the number of memories required, which is undesirable e.g., in view of the cost of memories, the added complexity and cost of the circuits needing interfaces for such memories, the premium for switch size, power dissipation requirements, and memory access time.
  • one approach to simplifying cell handling by an ATM switch is to limit the total amount of data needed for transport of a cell through the switch. Such limiting can be accomplished either (1) by limiting the data per connection or (2) by decreasing the number of allowed connections. While the first solution maintains the number of allowed connections, the ATM parameters become more course. These two approaches will only decrease the memory size, and still require table lookups. What is needed therefore, and an object of the present invention, is effective and efficient cell handling in an ATM switch with a minimal amount of look-up memory.
  • An Asynchronous Transfer Mode (ATM) switch comprises a controller which augments an ATM cell with buffering data.
  • the controller fetches the buffering data using VPI/VCI and link ID as an index in a look-up operation conducted using a look-up table.
  • a first buffer circuit connected to the controller receives an augmented ATM cell and stores the augmented ATM cell in a buffer cell memory in accordance with the buffering data.
  • the ATM cell Upon extraction from the buffer cell memory, the ATM cell is routed through a switch core. During cell egress from the switch, the cell leaves the switch core, travels through a switch port, and is received at a second buffer circuit. The second buffer circuit stores the augmented ATM cell in a cell buffer memory in accordance with the buffering data at egress.
  • the look-up operation performed by the controller is the only look-up operation performed relative to the ATM cell on the ingress side of the switch (i.e., prior to being routed through the switch core) . If buffering data with which the ATM cell is augmented also includes buffering data for the second buffer circuit, the look-up operation performed by the controller is the only look-up operation using external memory performed in the entire switch.
  • a second look-up operation is performed on an egress side of the switch so that the second buffer circuit can assign a new VPI/VCI to the egressing cell.
  • Fig. 1 is a schematic view of an ATM switch according to an embodiment of the invention.
  • Fig. 2 is a diagrammatic view of ATM cell content and transmission through the ATM switch of Fig. 1.
  • Fig. 3 is a schematic view of an ingress buffering section usable with the ATM switch of Fig. 1.
  • Fig. 4 is a schematic view of a database for use with the ATM switch of Fig. 1.
  • Fig. 5 is a diagrammatic view of an exemplary internal switch cell, the format being applicable for a cell on an ingress side of an ATM switch which employs a sixteen bit interface.
  • Fig. 6 is a flowchart showing operations performed in a buffer circuit included in the ATM switch of Fig. 1.
  • Fig. 7 is a schematic view of another embodiment of an exchange terminal for the ATM switch of Fig. 1.
  • Fig. 8A is a diagrammatic view of an exemplary format of routing information parameter RI for a Cross Point Addressing mode.
  • Fig. 8B is a diagrammatic view of an exemplary format of routing information parameter RI for a Table Addressing mode.
  • Fig. 1 shows an ATM switch 20 which primarily includes a switch core 22 and a plurality of device boards or exchange terminals 24 ⁇ - 24 n .
  • Each exchange terminal is connected to other portions of an ATM network, e.g., other nodes, by a set of ingress physical links 30 and a set of egress physical links 31.
  • exchange terminal 24 ⁇ is shown with ingress physical links 30 x and egress physical links 31 ⁇ .
  • exchange terminals 24 Although only two exchange terminals 24 are shown in Fig. 1, it should be understood that many other such exchange terminals are provided and are connected to switch core 22 in the same manner shown with respect to the illustrated exchange terminals. Moreover, unsubscripted reference to an exchange terminal or a constituent element of an exchange terminal is intended to refer to any such exchange terminal or element generically, and not to one specific exchange terminal or element .
  • a primary function of switch core 22 is to perform space switching, e.g., to route ATM cells received at one input terminal thereof to an appropriate output terminal (s) of switch core 22, so that an ATM transmission (potentially comprising many ATM cells) can occur between origination terminal equipment (the sender) and destination terminal equipment (the intended receiver) .
  • Fig. 1 shows switch core 22 connecting two ports so that cells on link 30 ⁇ incoming to switch 20 are ultimately transmitted to egress link 31 n .
  • Switch core 22 also performs copying of ATM cells and distribution of ATM cells to appropriate output terminals thereof in the case of point-to- multipoint cells, also known as multicast cells.
  • the structure and operation of switch core 22 is understood by the person skilled in the art and accordingly is not detailed further herein.
  • Exchange terminals 24 of switch 20 each include line termination equipment (L.T.) 40 for interfacing with ingress physical links 30 and egress physical links 31.
  • L.T. line termination equipment
  • each exchange terminal 24 has links 42 which connect line termination equipment 40 with an ATM controller 44.
  • An output terminal of controller 44 is connected to first buffer circuit 46, which in turn is connected to a switch port ingress input terminal 48 of switch port 50.
  • Switch port 50 has an ingress output terminal 52 which is connected to a suitable one of a plurality of switch core ingress input terminals 54 by a switch core ingress input interface 56.
  • Switch core 22 has a plurality of egress output terminals 64 which are paired with its ingress input terminals 54 and which are connected by switch core egress output interface 66 to exchange terminals 24 in accordance with the corresponding pairing.
  • each exchange terminal 24 has egress input terminal 68, the egress input terminal 68 being connected to interface 66.
  • Output terminals 70 on the egress side of switch ports 50 are connected to second buffer circuit 72, which in turn is connected to line termination equipment 40 by link 74.
  • Line termination 40 serves to interface link 74 with egress physical link 31.
  • ATM controller 44 is connected both to microprocessor 80 and to database memory 82.
  • Database memory is preferably a random access memory (RAM).
  • Microprocessor 80 is employed, e.g., to construct a database which resides in database memory 82. The utilization of the database in memory 82 is explained subsequently in connection with the operation of ATM controller 44.
  • ATM controller 44 is a device marketed by PMC-Sierra, Inc. as part number PM7322 RCMP-800 for performing ATM layer routing control, monitoring, and policing.
  • each exchange terminal 24 has a microprocessor 80.
  • Switch 20 has one or more unillustrated central processors to which the plurality of microprocessors 80 of the various exchange terminals 24 are connected.
  • An output terminal of controller 44 is connected to first buffer circuit 46.
  • First buffer circuit 46 is connected to store and access ATM cells in cell buffer 90.
  • second buffer circuit 72 on the outgoing side of exchange terminal 24 is connected to store and access ATM cells in cell buffer 92.
  • buffer circuit 46 and cell buffer 90 form an ingress buffering section 100; buffer circuit 72 and cell buffer 92 form an egress buffering section 102.
  • Ingress buffering section 100 can take many forms, such as (for example) the form of section 100A as illustrated in Fig. 3.
  • the particular ingress buffering section 100A shown in Fig. 3 includes both a input queue selector 120 and an output queue selector 122.
  • Cell buffer 92 comprises a plurality of queues 110 for each of a plurality of priority classes. All but one of the queues for each priority class are associated with a corresponding switch port. One queue for each priority class is a point-to-multipoint queue. Accordingly, in Fig.
  • queues 110 are subscripted in accordance with both priority class and destination switch port, i.e., queue 110 ⁇ , 2 being the queue for priority class 1, destination switch port 2, for example.
  • the point-to- multipoint queue for each class has "p-mp" as a designator, thus queue 110 ⁇ /P - mp is the queue for the point- to-multipoint cells for priority class 1.
  • Switch 20 performs a prepending operation upon in which both "buffering data" and routing data are added to incoming ATM cells.
  • Fig. 2 diagrammatically illustrates the transmission of an ATM cell through switch 20 and the content of the ATM cell at differing junctures in the routing through switch 20.
  • the ATM cell Upon arrival at ATM controller 44 of switch 20, the ATM cell comprises both its payload 200 and its header 202.
  • ATM controller 44 uses the VPI/VCI portion of cell header 202, as well as information regarding the physical link of the incoming cell, as an index in a smart search algorithm (based on binary search) for locating an appropriate one of a plurality of records 400 in the database stored in memory 82. As shown in Fig.
  • each record in the database of memory 82 includes e.g., a field for core routing data, a field for threshold values for first buffer circuit 46, a field for queue data for first buffer circuit 46, a field for connection type data for first buffer circuit 46, a field for threshold values for second buffer circuit 92, a field for queue data for second buffer circuit 92, a field for connection type data for second buffer circuit 92, and a new VPI/VCI.
  • first buffering data's means one or more of the following fields for the first buffer circuit 46: the field for threshold values, the field for queue data, and the field for connection type data.
  • second buffering data means one or more of the following fields for second buffer circuit 72: the field for threshold values, the field for queue data, and the field for connection type data.
  • buffering data means either one or both of “first buffering data” and “second buffering data”.
  • Fig. 4 shows (in brackets [ ]) various parameters included in each field of a record in the database stored in memory 82.
  • the acronyms employed for the parameters illustrated in Fig. 4 are explained in Appendix 1.
  • the core routing data field includes the parameters RI (Routing Information) ; IDP (Implicit Delay Priority), ICLP (ICLP Implicit Cell Loss Priority), MCI, and CID (Cell Identity) .
  • the routing information parameter RI holds fourteen bits of information used to route the cells through the switch core. In the direction towards the switch core, the RI parameter is used to address the out port(s) to which the cell is destined. Such addressing can be accomplished in either of two modes -- Cross Point Addressing or Table Addressing. Selection between the two addressing modes is differentiated by the MCI parameter.
  • the format of the routing information parameter RI for the Cross Point Addressing mode is illustrated in Fig. 8A..
  • the routing information parameter RI includes a pointer to an addressing table.
  • the addressing table holds the necessary information to route the cell.
  • the RI parameter can hold pointers up to 2 13 -1 table entries, each table entry corresponding to one combination of one or more out ports of the switch core.
  • the field in a record 400 for threshold values can contain one or more threshold values.
  • Typical threshold type values are those for Selective Cell Discard and EFCI (Explicit Forward Congestion Identifier) [see Fig. 4] .
  • microprocessor 80 constructs records 400 in the database which resides in database memory 82. Each record is constructed in accordance with VPI/VCI and information identifying the physical link incoming to ATM controller 44.
  • ATM controller 44 uses the data obtained from the appropriate one of the records 400 in several ways. First, ATM controller 44 uses such data to modify the standard ATM header 202, resulting in modified standard ATM header 202' . Secondly, ATM controller 44 augments or pre-pends the cell with a switch internal header 20 . Thus, as augmented, the cell includes not only payload 200 and a modified standard ATM header 202', but also switch internal header 204. As shown in Fig.
  • switch internal header 204 includes the first buffering data (depicted by reference numeral 206) which is utilized by first buffer circuit 46); switch core data (depicted by reference numeral 208) which is utilized by switch core 22; and, second buffering data (depicted by reference numeral 210) which is utilized by second buffer circuit 72) .
  • the modified standard ATM header 202' includes the new VPI/VCI obtained from the appropriate record 400 from the database stored in memory 82.
  • An ATM switch typically changes the VPI/VCI value so that the value of VPI/VCI of the arriving cell is not the same as the VPI/VCI value sent out of the switch for the cell.
  • buffer circuit 46 Upon receipt of the cell, buffer circuit 46 performs a number of operations using the pre-pend data which was included in the cell by ATM controller 44. In general, buffer circuit 46 uses the first buffering data 206 for its operations. Particularly, concerning the items included in the first buffering data, buffer circuit 46 uses the connection type data to decide if the connection is to be effected on a cell or packet based level. Buffer circuit 46 uses the threshold values for deciding if the incoming cell shall be buffered or thrown away. The EC bit in the switch internal header 208 is used to determine whether the cell should be EFCI-marked (Explicit Forward Congestion Identifier) or not in the case the EFCI threshold is exceeded.
  • EFCI-marked Explicit Forward Congestion Identifier
  • first buffer circuit 46 ascertains from the first buffering data 206 into which switch port queue the ATM cell should be placed.
  • the ATM cell is stored in one of the switch port queues 110.
  • the ATM cell no longer has the first buffering data 206.
  • the cell is applied to the ingress input terminal 48 of switch port 50.
  • switch port 50 in the particular example illustrated the line code and check sum (indicated by reference numeral 212) are added to the ATM cell.
  • the line code is used for synchronization.
  • the check sum is used to determine if a bit error has occurred during the transport through switch core 22. It should be understood that manner of and position of utilization of information comparable to line code and check sum can differ in other embodiments .
  • Switch core 22 Upon exiting switch port 50 the ATM cell is applied to ingress input terminal 54 of switch core 22.
  • Switch core 22 is controlled so that ingress input terminal 54 at which the ATM cell is received is connected by internal paths in switch core 22 to a desired egress output terminal 64 in accordance with the destination of the ATM cell.
  • Switch core 22 can handle a simple cross- point connection for a point-to-point cell, or (in the case of a point-to-multipoint cell) may require look-up to a table address in order to determine a plurality of egress output terminals 64 to which the input terminal 54 should be connected.
  • the control of switch core 22 in order to establish "internal connections" is understood by the person skilled in the art. It will be remembered that ATM controller 44 added routing information (e.g, the RI parameter) .
  • the RI parameter includes the destination address of the switch port, which is utilized in the switch core to route the cell . Point-to-point connections are not set upon the switch core. On the other hand, point-to-multipoint connections must be set up in the switch core. As understood with reference to Fig. 8B, the RI parameter is used to find an entry in a table for the connections to decide to which destination ports to copy the point-to-multipoint cell.
  • the ATM cell leaves switch core 22 with the same content with which it entered, and is applied to egress input terminal 68 of switch port 50.
  • Switch port 50 removes both line code and check sum 212 and the core routing data 208.
  • Switch port 50 uses the line code and check sum 212 for synchronization and to determine if a bit error has occurred during the transport through switch core 22.
  • the core routing data 208 is removed since it has successfully served its purpose of enabling the ATM cell to navigate switch core 22.
  • the ATM cell Upon leaving egress output terminal 70 of switch port 50, the ATM cell enters second buffer circuit 72. Upon entering second buffer circuit 72, the ATM cell has (in addition to its payload and the modified standard ATM header 202') second buffering data 210. In like manner as first buffering data 206 was utilized by first buffer circuit 46, the second buffer circuit 72 employs the second buffering data 210 to check the thresholds and to store the cell in a queue in accordance with its intended destination and service class.
  • the cell header 202' emerging from second buffer circuit 72 basically is that which was prepared by ATM controller 44, assuming that controller 44 supplied a VPI/VCI value. That is, the new cell header 202' is essentially the ATM header which is sent with the ATM cell out of switch 20. Some exceptions can occur, such as (for example) changing of the EFCI bit if congestion has occurred at egress.
  • a new VPI/VCI value must be determined and inserted into the header 202'. In the embodiment thus far described, ATM controller 44 added to the cell both (1) first buffering data 206 and (2) second buffering data 210.
  • ATM controller 44 need not add both the first buffering data 206 and the second buffering data 210, but can instead add buffering data for only one of circuits 46 and 72 (i.e., either one of first buffering data 206 or second buffering data 210) .
  • ATM controller 44 can add only first buffering data 206, if so desired.
  • the present invention also pertains to a switch with a central buffering device in its switch core 22, for example.
  • the buffering data is included in the switch internal header 204 which is prepended to the ATM cell by ATM controller 44.
  • the internal header has fields allotted for all of the prepended information, e.g., for the information obtained from the database in memory 82.
  • Fig. 5 shows an example switch internal header format for an ATM cell, the internal header having the buffering data included therein.
  • the format of Fig. 5 is applicable for a cell on an ingress side of an ATM switch in which a sixteen bit interface is employed. It is to be noted that from Fig. 5 that the first buffering data 206, the switch core data 208, and the second buffering data 210 need not be segregated within switch internal header 204, but instead can be interspersed among the fields of switch internal header 204.
  • the switch internal header 502 of Fig. 5 is for the embodiment mentioned in the preceding paragraph, i.e., the embodiment in which ATM controller 44 adds only first buffering data 206.
  • the switch internal header 500 of Fig. 5 would be modified in several respects.
  • the fields EDP/NSCD T and SCD/EPD/E T would also be added for the second buffer circuit, making the cell three bytes longer.
  • the fields DP and POL are utilized in the second buffering circuit in order to determine in which buffer the cell is to be stored.
  • Switch internal header 208 travels with the ATM cell throughout the switch. Acronyms employed for the parameters illustrated in Fig. 5 are explained in Appendix
  • Fig. 6 is a flowchart showing steps performed by buffer circuit 46 concerning an ATM cell which has internal header 500 (see Fig. 5) .
  • buffer circuit 46 uses the values of the DP and DSP parameters to determine into which queue in cell buffer 90 the cell should be stored.
  • the DP parameter is the Delay Priority parameter which indicates the delay priority of the cell
  • the DSP parameter is the Destination Switch Port parameter which contains information about which switch port (e.g., one of switch ports 50 ⁇ to 50 n ) the cell is destined to.
  • the DP and DSP parameters are thus some of the parameters which correspond to first buffering data 206.
  • buffer circuit 46 consults parameter PC to determine if the cell belongs to a packet connection. If the cell does not belong to a packet connection, step 604 is executed (and possibly steps 608 - 612) . At step 604, buffer circuit 46 determines whether a counter corresponding to the queue length of the particular queue identified in step 600 exceeds the value of the PPD/NSCD T parameter. From Appendix 1 it is understood that the PPD/NSCD T parameter is the Partial
  • step 606 is performed and the cell is discarded. Otherwise, operation continues with step 608.
  • buffer circuit 46 determines whether internal header 500 indicates that cell discard is enabled by checking the parameter DE .
  • buffer circuit 46 determines at step 610 whether the queue length counter for the subject queue (i.e., the queue determined at step 600) exceeds a congestion threshold.
  • the congestion threshold is ascertained from parameter SCD/EPD/E T of internal header 500.
  • Parameter SCD/EPD/E T is the Selective Cell Discard/Early Packet Discard/EFCI
  • Threshold contains the EFCI and the Early Packet Discard Threshold (if a packet connection) or the EFCI and the Selective Cell Discard Threshold (if not a packet connection) . If the congestion threshold is exceeded as determined at step 610, at step 612 buffer circuit 36 determines whether the cell is low priority, i.e., if the CLP bit in the ATM cell header is "1". This check is important because selective cell discard means discarding of low priority cells if the threshold is exceeded.
  • step 612 is affirmative, at step 614 the cell is discarded.
  • step 616 is executed if any of the checks or determinations at step 608, 610, or 612 are negative.
  • the cell is stored in the particular queue ascertained at step 600. Then, after step 616, at step 618 the queue length counter associated with that particular queue is incremented.
  • step 620 is next executed.
  • a determination is made whether the cell is the last cell in a packet. If the cell is the last cell in a packet, at step 622 the cell is marked as the last cell in internal memory. Otherwise, at step 624, the cell is marked as not being the last cell.
  • EOM end of message
  • a flag is checked to determine whether a partial packet discard (PPD) is in progress. If a partial packet discard is in progress, step 628 is next executed. A step 628, a check is made if an end of message (EOM) flag is set. This check is significant since a last cell should not be discarded in the case of a partial packet discard in progress. If the check at step 628 is affirmative, a further check is made at step 630 whether the counter corresponding to the queue length of the particular queue identified in step 600 exceeds the value of the PPD/NSCD T parameter (see step 604) . If the check at step 628 is negative, or the determination at step 630 is affirmative, the cell is discarded at step 632.
  • PPD partial packet discard
  • step 634 is next executed.
  • the cell is stored in the particular queue ascertained at step 600.
  • the queue length counter associated with that particular queue is incremented.
  • the flag indicative of a partial packet discard is cleared.
  • EOM end of message
  • a flag is checked at step 660 to ascertain whether a discard enable is in effect. If not, at step 662 the cell is stored and at step 664 the queue length counter is incremented. If discard enable is in effect, a check is next made at step 670 whether the queue length counter exceeds the Selective Cell Discard/Early Packet Discard/EFCI Threshold (SCD/EPD/E T) . If not, the cell is stored (step 672) and the queue length counter is incremented (step 674) .
  • SCD/EPD/E T Selective Cell Discard/Early Packet Discard/EFCI Threshold
  • step 670 If step 670 is affirmative, the cell is discarded (step 680); a check is made if the end of message (EOM) flag is set, and a flag is set to indicate that an early packet discard (EPD) is in progress (step 684) .
  • EOM end of message
  • EPD early packet discard
  • buffer circuit 46 includes a scheduler which selects from which queue to obtain a cell to send into switch core 22 via switch port 50. Generally the scheduler selects the queue which has the highest priority and sends the oldest cell stored in the queue. Upon the sending of the cell into switch core 22 the queue length counter for the sending queue is decremented. While the foregoing description has illustrated utilization of certain thresholds pertaining to individuals queues, the present invention also encompasses other types of thresholds. For example, thresholds for the entire cell buffer 90 may be employed (e.g., total cell count in all queues of cell buffer 90) .
  • the buffering data need not necessarily be unique for each buffer circuit.
  • differing buffering data is utilized by each buffer circuit, e.g., differing thresholds.
  • Fig. 3 illustrate a particular exemplarly embodiment of an ingress buffering section usable with the ATM switch of Fig. 1, it should be understood that there are yet further embodiments. That is, many differing buffering/queue architectures can be employed. For example, buffering/queuing can be made e.g. with one queue per connection, one queue per service class and destination, or per service class.
  • Fig. 7 shows another embodiment of an exchange terminal 24' which differs from exchange terminal 24 of Fig. 1 by inclusion of a second database in memory 500.
  • Memory 500 (which has the second database stored therein) is connected to second buffer circuit 72.
  • the second database is utilized for point-to-multipoint connections.
  • the outgoing VPI/VCI value must be added at the egress of switch 20. Adding all outgoing VPI/VCI values to the cell at ingress (e.g., using ATM controller 44) would make the cell too large e.g., for transmission through switch core 22. For this reason, the outgoing VPI/VCI values are added to the cell at second buffer circuit 72.
  • the VPI/VCI values are obtained by a look-up operation in the database stored in memory 500. For this reason, microprocessor 80 is shown as being connected to both second buffer circuit 72 and data base memory 500.
  • the size of the memories utilized for switch 20 depend on the number of connections which must be supported and the degree of advancement of the implementation (e.g., how many thresholds are employed) .
  • switch 20 of the present invention has only one database -- the database stored in memory 82 -- which is consulted on a look-up basis in order to obtain both routing data and buffering data.
  • only two data bases in memories 82 and 92 are required in the switch and outside of the switch core. Accordingly, switch 20 minimizes expensive memory requirements and the time utilized in conducting look-up operations. Moreover, in not requiring numerous look-up memories, switch 20 simplifies circuit design.
  • the bandwidth (e.g., size) of each ATM cell sent to first buffer circuit 46 is the same as that sent into switch core 22. Therefore, assuming that the switch core 22 can accommodate sufficient bandwidth, all data required by the constituent elements of switch 20 can be transmitted with the ATM cell through switch 20.
  • buffer circuits 46 and 72 have been illustrated as connected to switch ports, other allocations for buffer circuits 46 and 72 are possible.
  • buffering circuits 46 and 72 may be included internally in switch core 22.
  • the present invention can be practiced in switch implementations which do not employ a switch core. In such coreless implementations, a central buffer is used in which all cells from all links from all extension terminals are stored.
  • the present invention encompasses, e.g., coreless implementations in which a cell is prepended with buffering data, such as either one or both of first buffering data 206 and second buffering data 210 as above described.
  • Packet Discard threshold (if it is a packet connection) or the Non-Selective Cell Discard threshold (if it is not a packet connection).
  • Length 12 bits.
  • Packet Connection This field is used to specify if the cell belongs to a connection carrying AAL5 packets. This information is used to decide if packet discard should be performed or not. Length: 1 bit.
  • Delay Priority This field is used to transfer information about which delay priority the cell has. This information is used in conjunction with the Destination Switch Port field to decide in which buffer queue the cell should be stored. Length: 6 bits.
  • Physical Output Link This field is used to transfer information about which physical link the cell should be sent to. This information is used for Explicit Rate calculations. Length: 4 bits.
  • Physical Input Link This field is used to transfer information about which physical link the cell has been received from. This information is used for Explicit Rate calculations. Length: 4 bits.
  • EFCI Marking Connection This field is used to specify if the cell should be EFCI marked in case the EFCI threshold is crossed.
  • the EFCI threshold is transferred into the
  • Thresholds field Length: 1 bit.
  • This field is used to specify if the cell is a forward RM cell, a backward RM cell, or not an RM cell.
  • AC ABR Connection This field is used to specify if the cell belongs to an ABR connection. Length: 1 bit.
  • RI Routing Information This field is used to contain information that is used for routing the cell through the switch core. Length: 14 bits.
  • IDP Implicit Delay Priority This field assigns one of two loss priority levels to cells of an established connection one out of two delay priority levels. Length: 1 bit.
  • This field serves as an internal channel identifier to which the standardized VPI field is mapped in the switch. Length: 15 bits.
  • ICLP Implicit Cell Loss Priority This field assigns one of two loss priority levels to cells of an established connection one out of two loss priority levels. Length: 1 bit. MCI
  • Multicast Indication This field is used to indicate if the destination address should be interpreted as a cross point address or a table address. Length: 1 bit. SAV
  • Source Address Valid This field is used to indicate the validity of the SA field. Length: 1 bit.
  • SA Source Address This field is the number of the input port. Length: 7 bits.
  • Cell Identity This field contains identity codes for identifying the cell either as an idle cell, an alarm cell, a traffic cell, or a forward RM cell. Length: 3 bits . VCI
  • Virtual Channel Identifier This field holds no information when switching is done at the virtual channel level, but holds the VCI value from the standardize cell when switching is done at the VP level.
  • the AM field is used to decide how the VCI field should be interpreted. Length: 12 bits.
  • PT Payload Type This field indicates whether the payload is user cell data or OAM data, whether congestion is experienced, and how a ATM-layer-user-to-ATM-layer-user indicator is set. Length: 3bits .
  • Cell Loss Priority This field is defined in CCITT Recommendation 1.361 (B-ISDN ATM layer specification), and is used to assign different cells one of the two priority levels within the same connection. Length: 1 bit.
  • this field is used to specify if early packet discard is to be performed. If not a packet connection, this field is used to specify if the selective cell discard is performed. Length: 1 bit.
  • Destination Switch Port This field is used to transfer information about which switch port the cell is destined to. This information is used in conjunction with the Delay Priority field to decide in which queue in the buffer the cell should be stored. Length: 7 bits. PAYLOAD
  • Transparent payload This field is used to store the user data. Length: 384 bits.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un commutateur de mode de transfert asynchrone (MTA) (20) comprenant un contrôleur (44) qui augmente une cellule MTA par addition de données tampon. Pendant que la cellule entre dans le commutateur, un circuit tampon (46) connecté au contrôleur (44) reçoit une cellule MTA augmentée et stocke cette cellule MTA augmentée dans une mémoire cellulaire tampon (90) conformément aux données tampon. Pendant son extraction de la mémoire cellulaire tampon (90), la cellule MTA transite par un tore de commutation (22). Pendant que la cellule sort du commutateur, elle quitte le tore de commutation (22), transite par un port de commutation (50), et est reçue au niveau d'un second circuit tampon (72). Le second circuit tampon (72) stocke la cellule MTA augmentée dans une mémoire cellulaire tampon (92) conformément aux données tampon.
PCT/SE1998/001288 1997-07-11 1998-06-30 Cellule mta augmentee de donnees tampon WO1999003237A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000502606A JP2001510303A (ja) 1997-07-11 1998-06-30 バッファリング・データによるａｔｍセルの増強
GB0000450A GB2342811B (en) 1997-07-11 1998-06-30 Augmentation of ATM cell with buffering data
AU83626/98A AU8362698A (en) 1997-07-11 1998-06-30 Augmentation of atm cell with buffering data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US89350797A 1997-07-11 1997-07-11
US08/893,507 1997-07-11

Publications (1)

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WO1999003237A1 true WO1999003237A1 (fr) 1999-01-21

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JP (1) JP2001510303A (fr)
CN (1) CN1269936A (fr)
AU (1) AU8362698A (fr)
GB (1) GB2342811B (fr)
WO (1) WO1999003237A1 (fr)

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EP1026856A2 (fr) * 1999-02-04 2000-08-09 Nortel Networks Corporation Commutateur de paquets de haute capacité à plusieurs classes avec contrôle de débit
EP1052811A2 (fr) * 1999-05-13 2000-11-15 Nec Corporation Commutateur et sa porte d'entrée
EP1489795A2 (fr) * 2003-04-25 2004-12-22 Alcatel IP Networks, Inc. Comutateur de réseau configuré pour pondération de trafic
US6882799B1 (en) 2000-09-28 2005-04-19 Nortel Networks Limited Multi-grained network

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CN100428724C (zh) * 2005-07-11 2008-10-22 普天信息技术研究院 动态时分交换装置及方法

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EP0606729A2 (fr) * 1993-01-11 1994-07-20 AT&T Corp. Format interne étendu de cellules à ATM
US5361255A (en) * 1991-04-29 1994-11-01 Dsc Communications Corporation Method and apparatus for a high speed asynchronous transfer mode switch
EP0719065A1 (fr) * 1994-12-20 1996-06-26 International Business Machines Corporation Noeud de communication de paquets polycalent pour un réseau de communication de données
US5535202A (en) * 1994-03-16 1996-07-09 Mitsubishi Denki Kabushiki Kaisha Priority processing of ATM cells using shift register stages
US5537400A (en) * 1994-04-15 1996-07-16 Dsc Communications Corporation Buffered crosspoint matrix for an asynchronous transfer mode switch and method of operation
EP0785697A2 (fr) * 1996-01-16 1997-07-23 AT&T Corp. Réseau multi-étages avec mécanisme de rétroaction pour la congestion concernant le "routage point à multipoint"

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US5361255A (en) * 1991-04-29 1994-11-01 Dsc Communications Corporation Method and apparatus for a high speed asynchronous transfer mode switch
EP0606729A2 (fr) * 1993-01-11 1994-07-20 AT&T Corp. Format interne étendu de cellules à ATM
US5535202A (en) * 1994-03-16 1996-07-09 Mitsubishi Denki Kabushiki Kaisha Priority processing of ATM cells using shift register stages
US5537400A (en) * 1994-04-15 1996-07-16 Dsc Communications Corporation Buffered crosspoint matrix for an asynchronous transfer mode switch and method of operation
EP0719065A1 (fr) * 1994-12-20 1996-06-26 International Business Machines Corporation Noeud de communication de paquets polycalent pour un réseau de communication de données
EP0785697A2 (fr) * 1996-01-16 1997-07-23 AT&T Corp. Réseau multi-étages avec mécanisme de rétroaction pour la congestion concernant le "routage point à multipoint"

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1026856A2 (fr) * 1999-02-04 2000-08-09 Nortel Networks Corporation Commutateur de paquets de haute capacité à plusieurs classes avec contrôle de débit
EP1026856A3 (fr) * 1999-02-04 2001-04-04 Nortel Networks Limited Commutateur de paquets de haute capacité à plusieurs classes avec contrôle de débit
US6721271B1 (en) 1999-02-04 2004-04-13 Nortel Networks Limited Rate-controlled multi-class high-capacity packet switch
EP1052811A2 (fr) * 1999-05-13 2000-11-15 Nec Corporation Commutateur et sa porte d'entrée
EP1052811A3 (fr) * 1999-05-13 2004-05-06 Nec Corporation Commutateur et sa porte d'entrée
US6882655B1 (en) 1999-05-13 2005-04-19 Nec Corporation Switch and input port thereof
US6882799B1 (en) 2000-09-28 2005-04-19 Nortel Networks Limited Multi-grained network
EP1489795A2 (fr) * 2003-04-25 2004-12-22 Alcatel IP Networks, Inc. Comutateur de réseau configuré pour pondération de trafic
EP1489795A3 (fr) * 2003-04-25 2005-07-27 Alcatel IP Networks, Inc. Comutateur de réseau configuré pour pondération de trafic

Also Published As

Publication number Publication date
AU8362698A (en) 1999-02-08
GB2342811A (en) 2000-04-19
CN1269936A (zh) 2000-10-11
JP2001510303A (ja) 2001-07-31
GB0000450D0 (en) 2000-03-01
GB2342811B (en) 2002-08-07
GB2342811A8 (en) 2000-05-17

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