WO1999003202A3 - Level-controlled d-trigger - Google Patents

Level-controlled d-trigger Download PDF

Info

Publication number
WO1999003202A3
WO1999003202A3 PCT/RU1998/000213 RU9800213W WO9903202A3 WO 1999003202 A3 WO1999003202 A3 WO 1999003202A3 RU 9800213 W RU9800213 W RU 9800213W WO 9903202 A3 WO9903202 A3 WO 9903202A3
Authority
WO
WIPO (PCT)
Prior art keywords
trigger
controlled
level
mis
realised
Prior art date
Application number
PCT/RU1998/000213
Other languages
French (fr)
Russian (ru)
Other versions
WO1999003202A2 (en
Inventor
Sergei Kuzmich Luzakov
Original Assignee
Sergei Kuzmich Luzakov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from RU97111592/09A external-priority patent/RU97111592A/en
Application filed by Sergei Kuzmich Luzakov filed Critical Sergei Kuzmich Luzakov
Publication of WO1999003202A2 publication Critical patent/WO1999003202A2/en
Publication of WO1999003202A3 publication Critical patent/WO1999003202A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Landscapes

  • Static Random-Access Memory (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)

Abstract

The present invention pertains to the field of pulse technology and relates to a level-controlled D-trigger which can be used in memory elements or in controlled generators. This trigger can be realised using the complementary-MIS techniques with only six pairs of MIS transistors (1 - 12). The state fixation is achieved directly by using a logic signal which is formed at one of two clocked outputs (14, 16) by the action of clock (19, 20) pulses.
PCT/RU1998/000213 1997-07-07 1998-06-30 Level-controlled d-trigger WO1999003202A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU97111592 1997-07-07
RU97111592/09A RU97111592A (en) 1997-07-07 FRONT CONTROLLED D-TRIGGER (OPTIONS) AND LEVEL CONTROLLED D-TRIGGER FOR USE IN IT

Publications (2)

Publication Number Publication Date
WO1999003202A2 WO1999003202A2 (en) 1999-01-21
WO1999003202A3 true WO1999003202A3 (en) 1999-04-08

Family

ID=20195088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU1998/000213 WO1999003202A2 (en) 1997-07-07 1998-06-30 Level-controlled d-trigger

Country Status (1)

Country Link
WO (1) WO1999003202A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19743347C2 (en) * 1997-09-30 1999-08-12 Siemens Ag RS flip-flop with enable inputs

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4057741A (en) * 1974-01-31 1977-11-08 Lasag S.A. Logic circuit for bistable D-dynamic flip-flops
US4227097A (en) * 1977-07-08 1980-10-07 Centre Electronique Horloger, S.A. Logic D flip-flop structure
US4275316A (en) * 1978-11-06 1981-06-23 Rca Corporation Resettable bistable circuit
GB2174856A (en) * 1985-05-08 1986-11-12 Racal Microelect System Hysteresis latch arrangement

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4057741A (en) * 1974-01-31 1977-11-08 Lasag S.A. Logic circuit for bistable D-dynamic flip-flops
US4227097A (en) * 1977-07-08 1980-10-07 Centre Electronique Horloger, S.A. Logic D flip-flop structure
US4275316A (en) * 1978-11-06 1981-06-23 Rca Corporation Resettable bistable circuit
GB2174856A (en) * 1985-05-08 1986-11-12 Racal Microelect System Hysteresis latch arrangement

Also Published As

Publication number Publication date
WO1999003202A2 (en) 1999-01-21

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