WO1998055965A1 - Appareil et procede permettant d'optimiser la memoire lors du traitement d'images graphiques - Google Patents

Appareil et procede permettant d'optimiser la memoire lors du traitement d'images graphiques Download PDF

Info

Publication number
WO1998055965A1
WO1998055965A1 PCT/US1998/007798 US9807798W WO9855965A1 WO 1998055965 A1 WO1998055965 A1 WO 1998055965A1 US 9807798 W US9807798 W US 9807798W WO 9855965 A1 WO9855965 A1 WO 9855965A1
Authority
WO
WIPO (PCT)
Prior art keywords
color information
value
subpixel
pixel
subpixels
Prior art date
Application number
PCT/US1998/007798
Other languages
English (en)
Inventor
Charles Chungyohl Lee
Original Assignee
Oak Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oak Technology, Inc. filed Critical Oak Technology, Inc.
Publication of WO1998055965A1 publication Critical patent/WO1998055965A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed

Definitions

  • the present invention relates to processing of graphical images, and more particularly to a novel apparatus and method for optimizing memory usage during the processing of graphics images.
  • FIG. 1 depicts a typical computer graphics system 100 for generation and display of 2-D and 3-D graphics images.
  • Computer graphics system 100 includes CPU 102, graphics chip 104, system memory 110 and peripheral and storage devices 112.
  • System bus 114 which is typically a PCI bus, provides the communication interface between CPU 102, graphics chip 104, system memory 110 and peripheral and storage devices 112.
  • Graphics chip 104 is also coupled to local memory 106 which is used for storing image data and to cathode ray tube (CRT) display 108 which is used for displaying the graphics images.
  • Graphics chip 104 accepts commands from CPU 102 over system bus 114 and is responsible for processing the digital images to be displayed on CRT 108. Processing of graphics images, for both 2-D and 3-D images, includes performing anti-aliasing and image rendering.
  • Images processed by graphics chip 104 are drawn into a "frame buffer" which may reside either in local memory 106 or in system memory 1 10. Graphics chip 104 then periodically reads the frame buffer, a scanline at a time, and sends the display data to CRT 108 to be displayed on screen.
  • a typical 3-D graphics image is composed of a collection of planar polygons.
  • FIG. 2 depicts a section of the frame buffer for a typical 3-D graphics image composed of a collection of planar polygons 114a,b.
  • the frame buffer stores information for each pixel 116-1, 116-2, . . . 116-n to be displayed on CRT 108, where "n" represents the total number of pixels to be displayed.
  • the frame buffer stores information for each of the 320x240 pixels.
  • graphics chip 104 determines the correct color information associated with that pixel.
  • the color information includes information corresponding to the red (R), green (G) and blue (B) components of the pixel color.
  • a specified number of bits are allocated to store information for each of the color components for the pixel.
  • the RGB888 format uses 8 bits to store color information for each of the red (R), green (G) and blue (B) components for a given pixel.
  • the frame buffer is thus basically an array of memory elements storing color information for each pixel that is to be displayed on the screen. The amount of memory required for the frame buffer is determined by the resolution of the display device and the format used for storing pixel color information.
  • graphics chip 104 is also responsible for performing anti-aliasing on the digital image.
  • the "supersampling" method is a commonly used technique for performing anti-aliasing.
  • each pixel is further subdivided into "N" subpixels, where "N" is a number greater than one. It is common for each pixel to be subdivided into 16 subpixels (117-1, 117-2, . . ., 117-16) as shown in FIG. 3.
  • FIG. 4 depicts a prior art computer graphics system for generation and display of anti-aliased images in which frame buffer 122 and subpixel color buffer 120 are stored in local memory 106 coupled to graphics chip 104. In alternate embodiments subpixel color buffer 120 and frame buffer 122 may also be stored in system memory 1 10. Graphics chip 104 computes the RGB color information for each subpixel and writes the subpixel color information into subpixel color buffer 120.
  • FIG. 5 depicts a portion of subpixel color buffer 120 with two polygons 114a and 114b drawn into subpixel color buffer 120 where each pixel is subdivided into 16 subpixels. Thus, if the RGB888 format is used, subpixel color buffer 120 stores a 24-bit (3 * 8) color value for each subpixel.
  • the same RGB888 value is written into all of the subpixels storage locations corresponding to a pixel that is contained within a polygon. If only a portion of the pixel is contained within a polygon, for example pixel 124 in FIG. 5, then only those subpixels contained in the polygon are given the RGB 888 value for the polygon pixel color. Thus, in FIG. 5, pixel 124 will have some subpixels storing RGB888 values from polygon 114a, while the other subpixels will store RGB888 values from polygon 114b. After all the polygons of a 3-D image have been drawn into subpixel color buffer
  • graphics chip 104 then averages all of the subpixel color values for a pixel to compute a single pixel color value to be stored in frame buffer 122. This averaged pixel value stored in frame buffer 122 then gets displayed on CRT display device 108.
  • the reason for using subpixel color buffer 120 is that the averaging performed by graphics chip 104 for determining the color for a single pixel results in anti-aliasing, which improves the quality of the displayed image. Since subpixel color buffer 120 stores subpixel information for each subpixel, it requires extensive memory storage resources. For example, for a computer graphics system with screen resolution 320x240 pixels and which subdivides a pixel into 16 subpixels and uses the RGB888 format, the total number of memory bits required for subpixel color buffer 120 is:
  • the present invention achieves the above goals and objectives by providing a novel apparatus and method which reduces the amount of memory required for processing and displaying anti-aliased images. Memory savings are achieved by using a reduced number of bits to store subpixel information related to the anti-aliased image.
  • a graphics chip is coupled to an input sealer apparatus, an approximation computation apparatus, an approximation buffer, pixel color computation apparatus and an output sealer apparatus.
  • the input sealer apparatus scales the input pixel color value to a range represented by the reduced number of bits used to store subpixel information.
  • the approximation computation apparatus computes the approximated subpixel color values and writes them to the subpixel storage locations in the approximation buffer.
  • the subpixel color values are represented using a reduced number of bits than prior art techniques.
  • the pixel color computation apparatus retrieves subpixel values from the approximation buffer and averages them to determine the pixel color value.
  • the output sealer apparatus reverses the scaling effect introduced by the input sealer apparatus.
  • the computed pixel value is stored in the frame buffer by the graphics chip and then displayed on a CRT display device.
  • FIG. 1 is a block diagram depicting a typical computer graphics system for generating and displaying anti-aliased digital images.
  • FIG. 2 illustrates a section of the frame buffer for a 3-D image comprising of planar polygons.
  • FIG. 3 depicts an enlarged view of a pixel subdivided into sixteen subpixels for purposes of anti-aliasing.
  • FIG. 4 is a block diagram depicting a prior art graphics system for processing anti- aliased images.
  • FIG. 5 depicts a section of the subpixel color buffer for a 3-D image comprising of planar polygons in which each pixel is subdivided into sixteen subpixels.
  • FIG. 6 is a block diagram depicting an embodiment of the present invention for processing and displaying anti-aliased graphics images.
  • FIG. 7 depicts a flow chart showing the steps involved in processing of 3-D anti- aliased images in accordance with the teachings of the present invention.
  • FIG. 8 depicts an enlarged view of a pixel, comprising of sixteen subpixels, which is owned by two different polygons.
  • FIG. 9 depicts an enlarged view of a pixel showing the pattern of subpixels whose increment flag bit is set.
  • FIG. 10 depicts an enlarged view of a pixel showing the pattern of subpixels whose increment flag bit is set using subpixel scrambling performed by the scrambling logic.
  • FIG. 11a, lib, and 12 depict an example of pixel-level of scrambling in accordance with the present invention.
  • a novel apparatus and method is taught which reduces the amount of memory required for processing and displaying anti-aliased images.
  • the present invention provides a novel apparatus and method for storage of subpixel color information which requires less memory to store the subpixel color information as compared to prior art graphics system architectures.
  • FIG. 6 depicts an embodiment of a computer graphics system 130 constructed in accordance with the teachings of the present invention.
  • computer graphics system 130 comprises CPU 132, graphics chip 134, CRT display device 136, system memory 133, local memory 140 comprising of approximation buffer 142 (which replaces the subpixel color buffer of prior art systems) for storing subpixel information and frame buffer 144 for storing pixel information, input sealer apparatus 146, approximation computation apparatus 148 comprising of scrambling logic 150, pixel color computation apparatus 152 and output sealer apparatus 154.
  • System bus 138 which is typically a PCI bus, provides the communication interface between CPU 132, graphics chip 134 and system memory 133.
  • Graphics chip 134 takes commands from CPU 102 over system bus 138 and along with input sealer apparatus 146, approximation computation apparatus 148, approximation buffer 142, frame buffer 144, pixel color computation apparatus 152 and output sealer apparatus 154, is responsible for processing and displaying 3-D anti-aliased images on CRT 136.
  • approximation buffer 142 and frame buffer 144 reside in local memory 140, in alternate embodiments they may reside in system memory 133.
  • local memory 140 may be integrated with graphics chip 134.
  • the processed 3-D images are drawn into frame buffer 144.
  • Graphics chip 134 then periodically reads frame buffer 144, a scanline at a time, and sends the display data to CRT 136 to be displayed.
  • the present invention reduces the amount of memory required for 3-D anti-aliased graphics by storing subpixel information using a reduced number of bits than prior art techniques.
  • the present invention uses less than eight bits to store color information for each of the color components of the subpixel.
  • P number of bits required to store subpixel color information
  • M number of bits used to store pixel color information
  • N number of subpixels per pixel.
  • P 8 - (log-base-2(16))
  • Flowchart 160 depicted in FIG. 7 describes the steps involved in accordance with the teachings of the present invention.
  • Graphics chip 134 receives pixel color information in RGB888 format.
  • input sealer apparatus 146 scales the input pixel RGB888 value into a range suitable for storage as RGB444 in approximation buffer 142.
  • approximation computation apparatus 148 approximates the scaled RGB888 pixel color received from input scaling apparatus 146 to a subpixel color for each subpixel in RGB444 format. Additionally, rather than storing the same color component value into each of the subpixel locations, different color component values are stored in the subpixel locations in approximation buffer 142.
  • approximation computation apparatus 148 writes the subpixel information into approximation buffer 142.
  • pixel color computation apparatus 152 retrieves the subpixel information stored in approximation buffer 142. Pixel color computation apparatus 152 averages the subpixel colors in RGB444 format to determine the pixel color in RGB888 format. The pixel color value is then forwarded to output sealer apparatus 154.
  • output sealer apparatus 154 reverses the scaling effect introduced by input sealer apparatus 146.
  • the resultant output RGB888 pixel color value is written to frame buffer 144 and then displayed on CRT 136.
  • Input sealer apparatus 146 receives pixel information in RGB888 format and scales the input information to a value which falls within the range of values represented by the number of bits used to store the subpixel information. Scaling is performed by multiplying the input pixel value with a "input scaling factor.”
  • the numerator of the input scaling factor denotes the maximum value that can be represented by the number of bits used to store subpixel color component information in approximation buffer 142, while the denominator denotes the maximum value that is representable by the number of bits used to store the pixel color component information.
  • input sealer apparatus 146 scales the RGB888 pixel value to range representable by RGB444 format
  • the maximum representable value for an 8-bit number is OxFF (hexadecimal format) or 255 (decimal format).
  • the range of each color component represented in RGB888 format is 0 to 255.
  • the maximum representable value for a 4-bit number is OxF (hexadecimal format) or 15 (decimal format). Since each pixel is subdivided into sixteen subpixels, the maximum value that can be represented by approximation buffer color storage is:
  • the range of each color component represented in RGB444 format is 0 to 240. Since the input color range in RGB888 format is 0 to 255, the input scaling factor is (240/255). Input sealer apparatus 146 thus multiplies each input pixel color component by the input scaling factor (240/255). For example, the scaling down operation for the BLUE (B) color component of the input pixel having a value of 0x56 is as follows:
  • Approximation Computation Apparatus 148 receives a scaled input pixel color component value from input sealer apparatus 146. Approximation computation apparatus 148 uses the scaled input pixel color component value to generate subpixel color component values to be stored in the subpixel color storage locations in approximation buffer 142. In prior art techniques, the color component values for each of the subpixels are the same as the color component value of pixel. For example, if the blue pixel color component had a value of 0x56, that same value would be written into all of the subpixel locations for that particular color component However, in accordance with the teachings of the present invention, approximation computation apparatus 148 computes different color component values for the subpixel color components. Approximation computation apparatus 148 computes these values in a manner such that the average of all the subpixel values approximates the desired final color, while using fewer bits of storage in approximation buffer 142.
  • Approximation computation apparatus 148 computes these values by dividing each pixel color component value into a most significant bits (MSBs) portion and a least significant bits (LSBs) portion.
  • the MSB portion is the “base value” and the MSB portion incremented by one is the “incremented value.”
  • Approximation computation apparatus 148 then computes the "increment flag” bits for each of the subpixels based on the value of the LSB portion.
  • the "increment flag” is either SET or CLEAR. The total number of subpixels having a SET “increment flag” equals the value of the LSB portion.
  • the "increment flag" for a particular subpixel is SET, then the "incremented value” of the color component is assigned to that subpixel and stored in approximation buffer 142. If the "increment flag” for a particular subpixel is CLEAR, then the “base value” is assigned to the subpixel and stored in approximation buffer 148.
  • Base Value 0x1
  • the “increment flag” for the other 9 subpixels will be CLEAR.
  • the base value of 0x1 (4 bit value) will be assigned to that subpixel.
  • the incremented value of 0x2 (4 bit value) will be assigned to that subpixel.
  • the method can thus stores subpixel information in RGB444 format rather than RGB888 format.
  • the pixel color computation apparatus 152 reads the subpixel color values from approximation buffer 148 and averages them to determine the pixel color component value, the actual correct pixel color is obtained. For example, in the above example, the initial value of 0x17 is retrieved by pixel color computation apparatus 152 by performing the following calculation:
  • Pixel component value Sum of all the subpixel values
  • the present invention reduces the amount of memory required for subpixel information storage while processing 3-D anti- aliased images without degradation of image quality.
  • the above method employed by approximation computation apparatus 148 produces no artifacts for pixels displayed on the screen which are wholly owned by a single non-transparent polygon, for example, pixel 126 in FIG. 5 which is entirely owned by polygon 114-a.
  • a pixel is owned by multiple polygons, for example, pixel 124 which is owned by polygon 114a and 114b, or if the polygon is a partially transparent polygon
  • the approximation method performed by approximation computation apparatus 148 may introduce artifacts in the displayed image.
  • Scrambling logic 150 which is part of approximation computation apparatus 148 minimizes the visual discrepancies caused by such artifacts. Scrambling logic 150 performs "subpixel scrambling" to reduce errors introduced due to a pixel being owned by multiple polygons and performs "chain scrambling” to reduce the errors where the pixel is part of a partially transparent polygon.
  • FIG. 8 depicts an enlarged view of pixel 124 of FIG. 5. As shown in FIG. 8, pixel
  • FIG. 9 depicts illustrates the pattern of subpixels generated by approximation computation apparatus 148 using the approximation method for a pixel blue color value of 0x17.
  • the shaded subpixels in FIG. 9 represent the subpixels whose increment flag bit is SET.
  • the increment flag bit is SET for seven subpixels and CLEAR for the other nine subpixels.
  • the base value of 0x1 is written to each subpixel with the increment flag CLEAR and the incremented value of 0x2 is written to each subpixel whose increment flag bit is SET.
  • the pixel color for the six subpixels touched by polygon 114a can be computed as:
  • Pixel color (Sum of subpixel values for subpixels owned by polygon 114a)
  • Scrambling logic 150 minimizes the errors introduced by the above situation by storing as close a value to the actual value as possible within the constraint of six subpixels. Scrambling logic 150 accomplishes this by SETTING the increment flag bits in a "scrambled" pattern such that the SET increment flag bits are evenly distributed among the available subpixels.
  • FIG. 10 illustrates the scrambled subpixel pattern for storing a pixel blue color value of 0x17. From FIG. 10, the pixel color for the six subpixels touched by polygon 114a can be computed as:
  • Pixel color (Sum of subpixel values for subpixels owned by polygon 114a) (Number of subpixels touched by polygon 114a)
  • scrambling logic 150 greatly reduces errors produced when a pixel is owned by multiple polygons.
  • a common technique for drawing transparent polygons is to draw them with subpixel "holes" in the pixels. For example, for a pixel subdivided into sixteen subpixels, the drawing hardware will touch only eight of the sixteen subpixels, thus leaving "holes” in the remaining eight subpixels.
  • Such a polygon when drawn on the screen appears to be 50% transparent, as the objects behind the polygon are seen with 50% color intensity, while the polygon itself is seen with 50% color intensity.
  • scrambling logic 150 performs "pixel-level scrambling” to reduce any perceived color errors for transparent polygons. Scrambling logic 150 performs "pixel-level scrambling” by rotating the subpixel colors stored in a group of N pixels on-screen, such that the errors at any particular pixel are "evened out” among the group of N pixels. Consequently, when looking at the group of "N" pixels, the errors tend to cancel each other out. This technique works for either one transparent polygon, or multiple transparent polygons overlapping each other.
  • pixel-level scrambling spreads out the errors such that among a group of N pixels, the errors tend to cancel each other out: one way of doing pixel-level scrambling rotates the 16 increment flag bits differently for a group of 16 pixels on-screen, in the following manner, as depicted in Fig 12.
  • N 16
  • a simple rotation pattern for the "pixel- level scrambling" is possible using the same methodology.
  • the present invention reduces the amount of memory required for the subpixel information storage while processing 3-D anti-aliased images with minimal degradation of image quality. Furthermore, scrambling logic 150 minimizes the occurrence of artifacts in the displayed 3-D anti-aliased graphics image.
  • Approximation Buffer 142 replaces the subpixel color buffer of prior art graphics systems. Subpixel color information is stored in approximation buffer 142 using less memory bits than prior art techniques. Consequently, approximation buffer requires significantly smaller memory than a traditional subpixel color buffer. Although, the embodiment of the present invention depicted in FIG. 6 shows approximation buffer 142 residing in local memory 140, in alternate embodiments approximation buffer 142 may also reside in system memory 133.
  • Output sealer apparatus 154 reverses the scaling effects introduced by input sealer apparatus 146. In essence, output sealer apparatus 154 scales the pixel value from the range represented by the number of bits used to store subpixel color information to the range represented by the number of bits used to store pixel color information. This is performed by multiplying the pixel value with an "output scaling factor.” The output scaling factor is the inverse of the input scaling factor computed by input sealer apparatus 146.
  • the output scaling factor is (255/240), where the numerator denotes the maximum value that can be represented by the number of bits used to store pixel color component information and the denominator denotes the maximum value that is representable by the number of bits used to store the subpixel color component information.
  • the product of the multiplication represents the pixel value in RGB888 format and is stored in frame buffer 144.
  • Graphics chip 134 then periodically reads frame buffer 144, a scanline at a time, and displays the pixel on CRT display 136.
  • the present invention applies to processing of 2-D and 3-D graphics images.
  • the present invention has been described above with reference to an architecture in which the pixel color is represented in RGB888 format, the subpixel information is stored in RGB444 format and each pixel is subdivided into sixteen subpixels.
  • the scope of the present invention is not limited to the above architecture. It should be obvious to those skilled in the art that the present invention can work with a wide variety of architectures using different color format schemes and having varying number of subpixels per pixel. In general, the higher the number of subpixels per pixel, the higher the relative benefit of the present invention in reducing the required storage.
  • the present invention reduces the amount of memory required for processing 2-D or 3-D anti-aliased images.
  • the present invention achieves this by reducing the number of bits required for the storage of subpixel color information.
  • P number of bits required to store subpixel color information
  • M number of bits used to store pixel color information
  • N number of subpixels per pixel.
  • the present invention provides memory savings of approximately 50% over prior art techniques.
  • the relative benefit of the present invention in reducing memory storage is directly proportional to the number of subpixels per pixel. This in turn translates to significant cost savings for the graphics system.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Nouvel appareil et nouveau procédé permettant d'optimiser et de réduire la quantité de mémoire requise pour traiter des images graphiques anticrénelées, tout en conservant la qualité de l'image affichée. Un tampon d'approximation est utilisé pour stocker les informations de couleur de sous-pixels et la réduction de mémoire est obtenue par réduction du nombre de bits utilisés pour stocker lesdites informations. Un appareil de réduction d'échelle d'entrée met à l'échelle la valeur de couleur de pixel d'entrée dans une plage représentée par le nombre réduit de bits utilisés pour mettre en mémoire des informations de couleur de sous-pixels. Un appareil de calcul d'approximation calcule les valeurs de couleur de sous-pixels approximées et les écrit dans les sites de stockage de sous-pixels dans le tampon d'approximation. Ledit tampon stocke les valeurs de couleur de sous-pixels en utilisant un nombre plus réduit de bits que les techniques classiques. L'appareil de calcul de couleur de sous-pixels extrait les valeurs de sous-pixels du tampon d'approximation et en établit la moyenne pour déterminer la valeur de couleur de pixel. Finalement, un appareil d'agrandissement d'échelle de sortie inverse l'effet de mise à l'échelle introduit par l'appareil de réduction d'échelle d'entrée. La valeur de pixel calculée est mise en mémoire dans la mémoire graphique par la puce graphique et ensuite affichée sur un dispositif d'affichage à tube cathodique.
PCT/US1998/007798 1997-06-04 1998-04-20 Appareil et procede permettant d'optimiser la memoire lors du traitement d'images graphiques WO1998055965A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86898597A 1997-06-04 1997-06-04
US08/868,985 1997-06-04

Publications (1)

Publication Number Publication Date
WO1998055965A1 true WO1998055965A1 (fr) 1998-12-10

Family

ID=25352713

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/007798 WO1998055965A1 (fr) 1997-06-04 1998-04-20 Appareil et procede permettant d'optimiser la memoire lors du traitement d'images graphiques

Country Status (1)

Country Link
WO (1) WO1998055965A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112204619A (zh) * 2019-04-23 2021-01-08 华为技术有限公司 处理图层的方法和装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430501A2 (fr) * 1989-11-17 1991-06-05 Digital Equipment Corporation Système et méthode pour dessiner des polygones non corrompus
WO1996008917A1 (fr) * 1994-09-16 1996-03-21 Apple Computer, Inc. Systeme de correction de couleurs et procede utilisant une juxtaposition
US5561751A (en) * 1994-12-13 1996-10-01 Microsoft Corporation System and method for displaying a color image using vector error diffusion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430501A2 (fr) * 1989-11-17 1991-06-05 Digital Equipment Corporation Système et méthode pour dessiner des polygones non corrompus
WO1996008917A1 (fr) * 1994-09-16 1996-03-21 Apple Computer, Inc. Systeme de correction de couleurs et procede utilisant une juxtaposition
US5561751A (en) * 1994-12-13 1996-10-01 Microsoft Corporation System and method for displaying a color image using vector error diffusion

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"INTEGRATED SCHEME FOR DITHERING 24 BITS OF TRUE COLOR DOWN TO 4/8 12 OR 16 BITS WITH REDUCED ERROR", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 37, no. 6A, 1 June 1994 (1994-06-01), pages 179 - 181, XP000455733 *
BARKANS A C: "COLOR RECOVERY: MILLIONS OF COLORS FROM AN 8-BIT GRAPHICS DEVICE", COMPCON (SPRING), TECHNOLOGIES FOR THE INFORMATION SUPERHIGHWAY SAN FRANCISCO, MAR. 5 - 9, 1995, CONFERENCE 40, IEEE, pages 193 - 198, XP000545430 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112204619A (zh) * 2019-04-23 2021-01-08 华为技术有限公司 处理图层的方法和装置

Similar Documents

Publication Publication Date Title
US7903123B1 (en) System for programmable dithering of video data
US5179641A (en) Rendering shaded areas with boundary-localized pseudo-random noise
US6795080B2 (en) Batch processing of primitives for use with a texture accumulation buffer
US6459428B1 (en) Programmable sample filtering for image rendering
US8199146B2 (en) Processing of computer graphics
US7064771B1 (en) Method and apparatus for compositing colors of images using pixel fragments with Z and Z gradient parameters
US7221381B2 (en) Methods and systems for sub-pixel rendering with gamma adjustment
US7545388B2 (en) Apparatus, method, and product for downscaling an image
US5515484A (en) Method and apparatus for rendering volumetric images
US5493637A (en) Video buffer recycling method and apparatus
US20060197778A1 (en) Multi-sample method and system for rendering antialiased images
US20030227462A1 (en) Graphics texture processing methods, apparatus and computer program products using texture compression, block overlapping and/or texture filtering
US20080001961A1 (en) High Dynamic Range Texture Filtering
WO2009090726A1 (fr) Dispositif et procédé de dessin graphique
US5528738A (en) Method and apparatus for antialiasing raster scanned, polygonal shaped images
US20020171665A1 (en) Efficient antialiased dot rasterization
KR20130095651A (ko) 텍스트 렌더링을 위한 룩업 테이블
US5581680A (en) Method and apparatus for antialiasing raster scanned images
US6661423B2 (en) Splitting grouped writes to different memory blocks
US6914609B2 (en) Multiple scan line sample filtering
US20030160799A1 (en) Reconfigurable hardware filter for texture mapping and image processing
US6795081B2 (en) Sample cache for supersample filtering
WO1998055965A1 (fr) Appareil et procede permettant d'optimiser la memoire lors du traitement d'images graphiques
US20030028568A1 (en) System and method for a single-pass multiple tap filter
US6819320B2 (en) Reading or writing a non-super sampled image into a super sampled buffer

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: CA

NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 1999502391

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase