WO1998039709A1

WO1998039709A1 - Data storage device with redundancy circuit

Info

Publication number: WO1998039709A1
Application number: PCT/DE1998/000643
Authority: WO
Inventors: Thomas Zettler
Original assignee: Siemens Aktiengesellschaft
Priority date: 1997-03-05
Filing date: 1998-03-04
Publication date: 1998-09-11
Also published as: DE19708963C2; DE19708963A1

Abstract

The invention relates to a data storage device, especially a semi-conductor data storage device (1) with the following features: 1) at least one storage cell location field (2) with storage cells (S1); said storage cells (S1) can be selected by contacting at least one selection signal with selection lines (XSEL 1,..., XSEL n) provided in the area of said storage cells (S1) and said selection lines can comprise word lines and/or bit lines; 2) a redundancy circuit (3, 7) with at least one redundancy storage cell (RS1); said storage cells (RS1) can be selected by contacting at least one redundancy selection signal with redundancy selection lines (RXSEL1, ..., RXSEL4) provided in the area of said redundancy storage cells (RS1) and said redundancy selection lines can comprise redundancy word lines (RXSEL1, ..., RXSEL4) and/or redundancy bit lines; and 3) a redundancy selection line selection circuit wherein at least one allocation information unit can be stored, said redundancy selection line selection circuit being configured in such a way that at least one redundancy selection line (RXSEL1) can be allocated to at least one selection line (XSEL1) based on said allocation information. Relatively high voltages in the range of 10V or more are needed for programming the redundancy storage cells for a data storage device of this type, requiring additional circuit complexity. According to the invention, the redundancy selection line selection circuit has at least one ferroelectric and especially static ferroelectric allocation memory (10, 11, 12, 13) for accommodating the allocation information, enabling redundancy storage cells (RS1) to be allocated to defective storage locations (S1) quickly and simply.

Description

description

Data storage with a redundancy circuit

The invention relates to a data memory, and in particular to a semiconductor data memory, which has the following features: at least one memory cell array which has memory cells, the memory cells being selectable by applying at least one selection signal to selection lines provided in the area of the memory cells, the selection lines word lines and / or may include bit lines, a redundancy circuit which has at least one redundancy memory cell, the redundancy memory cells being selectable by applying at least one redundancy selection signal to redundancy selection lines provided in the area of the redundancy memory cells, the redundancy selection lines comprising redundancy word lines and / or redundancy bit lines can. a redundancy selection line selection circuit in which at least one assignment information can be stored, the redundancy selection line selection circuit being designed such that at least one redundancy selection line can be assigned to at least one selection line on the basis of the assignment information.

Data storage, and particularly semiconductor data storage, are often manufactured in the following manner. First, a variety of data memories are created on a substrate section called a wafer. After the wafer has been produced, the individual data memories are tested, in particular to determine whether the memory cells of the memory cell array and the redundancy memory cells of the redundancy circuit are working properly. A different value is repeatedly written in each memory cell or in each redundancy memory cell, whereby by a subsequent read operation, it is checked whether the checked memory cell or redundant memory cell could be described Trim according ^¬. If a defective memory cell is determined, the redundancy selection line selection circuit is programmed in such a way that an unusable memory cell is assigned a properly functioning redundancy memory cell. This is done in such a way that the assigned redundancy memory cell takes over the function of the memory cell identified as defective. Due to the special design of the redundancy selection line selection circuit, an assigned redundancy memory cell can be addressed in such a way that the memory cell array gives the impression from the outside that it only has properly functioning memory cells.

In a subsequent step, the wafer is sawn into individual data memories. The individual data storage devices are then mounted in the housing and subjected to a test again, with the generic data storage devices only then being delivered.

The generic data memories have redundancy selection line selection circuits which have flash or EEPROM memory cells in order to store allocation information on the basis of which a redundancy memory cell is assigned to a defective memory cell during operation. To program these memory cells, relatively high voltages in the range of 10 V or greater are required. These voltages have to be generated in a complex manner by means of separate pump circuits, so that additional circuitry is required in the generic data memories. Furthermore, depending on the programming method used, relatively long programming times are required when assigning redundancy memory cells to memory cells. With the so-called "hot electron" process, a programming time in the range of a few microseconds, while the so-called "Fowler-Nordheim" process even results in programming times in the millisecond range. This is particularly troublesome because when the generic data memories are tested, the redundancy memory cells must also be checked for their proper function, which is done by repeated reprogramming of the redundancy memory cells. In the case of a large number of redundancy memory cells, the programming times add up, so that the check is particularly time-consuming. The "hot electron" process is also associated with high power consumption in the range of two milliamperes per checked byte of the data memory.

It is therefore an object of the invention to provide a data memory which has a simple structure in which the redundancy memory cells can be quickly and easily checked for their function and in which redundancy memory cells can be quickly and easily assigned to defective memory cells.

This object is achieved according to the invention in that the redundancy selection line selection circuit for receiving the association information or the association information has at least one ferroelectric and in particular static ferroelectric association memory.

The use of a ferroelectric allocation memory has the advantage of low power consumption and rapid programming, since ferroelectric memory areas can be permanently programmed by simply polarizing a layer.

Furthermore, at least one address decoder is provided, which is connected between an address bus and the selection lines leading to the memory cells, the address decoder advantageously being designed in such a way that one or more selection lines correspond to an am Address bus pending address are selectable. In addition, a redundancy address decoder is provided which is connected between the address bus and the redundancy selection lines which lead to the redundancy memory cells, the redundancy address decoder being designed such that one or more redundancy selection lines can be selected in accordance with an address present on the address bus. Furthermore, the redundancy selection line selection circuit is preferably arranged in the region of the redundancy address decoder. The data memory configured as above proves to be particularly advantageous because the redundancy selection line selection circuit is easy to operate both in a programming state in which the redundancy memory cells are assigned to defective memory cells and in an operating state in which the corresponding redundancy memory cells replace defective memory cells. In the programming state, the redundancy selection line selection circuit then learns from the connected address bus the addresses of the memory cells to be replaced in each case via the same address lines via which the redundancy memory cells are accessed during operation. This considerably reduces the amount of circuitry.

The data memory according to the invention is particularly advantageously designed with an address decoder which can be deactivated by the redundancy address decoder. This prevents incorrect reading of information, since in the case in which a redundancy memory cell is accessed, no memory cell is accessed. The reliability of the data memory also increases.

In addition, it is particularly advantageous if the data memory has the following features: the address bus is designed as a parallel address bus with a number of address bus lines. the ferroelectric allocation memory has ferroelectric allocation memory cells, the number of ferroelectric allocation memory cells being equal to that

Number of address bus lines is. This results in a particularly simple decoding of the address present on the address bus both in the programming mode and in the working mode of the assignment memory of the

Data storage. Advantageously, a plurality of the ferroelectric allocation memories configured as above are provided, in which case each ferroelectric allocation memory then has at least one ferroelectric validation memory cell with a validation address line. Each redundancy selection line, such as a redundancy word line, is assigned exactly one allocation memory with a whole set of allocation memory cells and with one validation memory cell, with all allocation memories being connected in parallel to the address bus. Thus, each assignment memory receives the address currently on the address bus, with individual assignment memories being assignable to specific addresses on the address bus if the assignment memory cells are suitably programmed. Appropriate programming of the validation memory cell can then ensure that only the desired allocation memory responds to the addresses currently present on the address bus.

The embodiments of the data memory according to the invention explained above prove to be particularly advantageous during normal operation of the data memory, in which the data memory is accessed. In particular for simple programming of the allocation memories of the data memory according to the invention, the memory has the following features: the redundancy selection line selection circuit has not only one, but several ferroelectric and in particular static allocation memories for receiving the allocation information, allocation address lines are provided in the region of the allocation memory cells, wherein at least one ferroelectric allocation memory can be selected by applying at least one allocation address signal to at least one allocation address line.

The above development of the invention makes it easy to select one of the multiple allocation memories during programming.

In this case, at least one allocation memory selection decoder, which is connected between an allocation address bus and the allocation address lines, is advantageously provided, which can be designed such that one or more allocation address lines can be selected in accordance with an address present on the allocation address bus. The allocation memory selection decoder can be designed as a switching mechanism that converts the coded allocation memory addresses arriving on a parallel bus into signals applied to individual allocation memories.

In the subject matter of the invention embodied as above, a single address bus ensures access to the memory cell array and the redundancy memory cells, while an association address bus is used to address those map memory cells which have to be programmed in order to assign the redundancy memory cells to the memory cells.

In a particularly easy-to-use embodiment of the invention, the allocation memories are programmed by storing the address of another memory cell to be replaced in each allocation memory, the allocation memory selection decoder being used to select which allocation memory is to be used for addressing a specific one replacing memory cell takes over. The selection signal applied to the address bus for the memory cell to be replaced is also used as a programming signal for the allocation memory, with suitable interconnection ensuring that only one allocation memory is ever programmed with one address at a time. In this embodiment, there is the advantage essential to the invention that the low-strength signals present on the address bus are sufficient to supply the assignment memory with the assignment information. This was not possible in the prior art; rather, the redundancy

Selection line selection circuit requires high separately generated programming voltages.

The allocation memory cell of the data memory according to the invention has at least one ferroelectric component as the first memory element. The ferroelectric component can be designed, for example, as a ferroelectric capacitor or as a ferroelectric field-effect transistor. However, other ferroelectric components are also possible.

In a further development of the ferroelectric component, at least one flip-flop assembly is provided as the second memory element, the first memory element or the first memory elements being designed to be actuatable by the second memory element. When programming the assignment memories, a data item to be stored in the assignment memory cell is first transferred to the flip-flop and buffered. The information stored in the flip-flop is then transmitted from the flip-flop to the ferroelectric component or to the ferroelectric components by means of a suitable circuit. In this way, it is possible to invert the polarity of ferroelectric films in a particularly reliable manner which usually produce ferroelectric components.

The invention is illustrated in more detail in the drawing using an exemplary embodiment.

Figure 1 shows a block diagram of an inventive

2 shows a block diagram of a redundancy decoder of the data memory from FIG. 1,

3 shows a block diagram of an allocation memory selection decoder from FIG. 2, FIG. 4 shows a block diagram of an allocation memory of the redundancy address decoder from FIG. 2, FIG. 5 shows a circuit diagram of an allocation memory cell of the allocation memory from FIG. 4, FIG. 6 shows a voltage waveform diagram which illustrates the programming operation of the allocation memory cell from FIG FIG. 7 shows a further voltage curve diagram which illustrates the programming operation of the allocation memory cell from FIG. 5, FIG. 8 shows a further voltage curve diagram which illustrates the read operation of the allocation memory cell from FIG. 5.

FIG. 1 shows a data memory 1 according to the invention, which is generated on a semiconductor substrate (not shown in this view).

The data memory 1 has a memory cell array 2, which can be, for example, a DRAM, an SRAM, an EEPROM, a flash or a FRAM. The memory cell array has word lines XSEL1 to XSELn and bit lines YSEL1 to YSELn which run perpendicular to one another. Individual memory cells in the memory cell array 2 can be selected via the word and bit lines by applying suitable signals. In 1 shows only a single memory cell S1, which is selected by selecting the word line XSEL1 and the bit line YSEL1. In this view, control circuits associated with the memory cell array, such as level converters, are not shown.

The data memory 1 also has a redundancy memory cell array 3 which has redundancy word lines RXSEL1 to RXSEL4. Otherwise, the redundancy memory cell array 3 also uses the bit lines YSEL1 to YSELN of the memory cell array 2. Redundancy memory cells of the redundancy memory cell array 3 can be selected via the redundancy word lines RXSEL1 to RXSEL4 and the bit lines YSELl to YSELn. 1 shows only one redundancy memory cell Rsl, which can be selected by applying suitable signals to the word line RXSELl and to the bit line YSELl. The data memory 1 also has an address decoder 4 for the word lines XSEL1 to XSELn of the memory cell array 2. The address decoder 4 receives address data from a parallel address bus 5, which has a plurality of parallel address lines, which is illustrated in the drawing by a slash on the address bus 5. The address decoder 4 converts the address data coming from the address bus 5 into control signals for the word lines XSEL1 to XSELn. For this purpose, the address decoder 4 is constructed in the usual way and is not specifically described here. Furthermore, the address decoder 4 has a deactivation input 6. If a logic "1" signal is applied to the deactivation input 6, all signals XSEL1 to XSELn are set to logic "0".

Finally, the data memory 1 also has a redundancy address decoder 7 which, depending on its internal programming and the address data arriving from the address bus 5, drives the redundancy word lines RXSEL1 to RXSEL4. The redundancy address decoder 7 is connected to the deactivation input 6 of the address decoder 4, in such a way that the Address decoder can be deactivated by the redundancy address decoder 7. For its programming, the redundancy ^address decoder 7 has an assignment address bus 8 and various programming inputs 9, via which programming signals LATCH, PLATE, DISABLE and WEN can be entered into the redundancy ^address decoder 7.

In FIG. 1, the redundancy circuit consisting of redundancy memory cell array 3 and redundancy address decoder 7 is provided as an example for the word lines XSEL1 to XSELn. A redundancy circuit can also be provided for the bit lines YSEL1 to YSELn. Because of the simplified illustration, however, such a redundancy circuit for the bit lines is not shown in this view.

FIG. 2 shows the redundancy address decoder 7 from FIG. 1 in more detail.

Central components of the redundancy address decoder 7 are four allocation memories 10, 11, 12 and 13, each of which is connected on the output side to one of the redundancy word lines RXSEL1 to RXSEL4. The assignment memories 10, 11, 12 and 13 are connected to the address bus 5 on the input side. In addition, each of the allocation memories 10, 11, 12 and 13 is connected to an activation line, which is not shown separately in this view and which supplies a signal ENA.

A deactivation switch 14 is provided to generate a deactivation signal DIS for the deactivation input 6 of the address decoder 4. The deactivation switching mechanism 14 has two NAND gates, each with two inputs, one NAND gate being connected on the input side to the redundancy word lines RXSEL1 and RXSEL2, while the other NAND gate is connected on the input side to the redundancy word lines RXSEL3 and RXSEL4. The Outputs of the NAND gates are fed to two inputs of a NOR gate, which generates the DIS signal.

The address bus 5 together with the assignment of memories 10, 11, 12 and 13 as well as the deactivation derailleur 14 active in normal operation of the data memory 1 operation ^¬ area of Redundanzadreßdecoders 7. It is clear that with increasing number of redundancy word lines RXSEL an increasing number of assignment memories must be provided in the redundancy address decoder 7. In the exemplary embodiment of the invention, however, only four redundancy word lines are provided.

The redundancy address decoder 7 also has a programming area which is only in the programming mode of the

Data memory 1 is active. For this purpose, the data memory 1 has an assignment address decoder 15 which is connected on the input side to the assignment address bus 8. Upon the input of a suitable assignment address signal on the assignment address bus 8, one of the four assignment memories 10, 11, 12 and 13 is activated for the programming mode. The

Redundancy address decoder 15 on four output lines 16, which are denoted by ZSEL1, ZSEL2, ZSEL3 and ZSEL4 and which are fed to four NOR gates 17 together with an external programming signal WEN. The outputs of NOR gates 17 lead to activation inputs SEL1, SEL2, SEL3 and SEL4

Allocation memory 10, 11, 12 and 13.

FIG. 3 shows the assignment address decoder 15 from FIG. 2 in more detail. As can be seen, the allocation address decoder 15 has four NAND gates, each with two inputs, which are connected to an allocation address decoder switching mechanism 18 with two inverters as shown in FIG. As can be seen particularly well in this view, the assignment address bus 8 has only two assignment address lines ZADRI and ZADR2. From the two binary coded assignment address lines of the assignment address bus 8 each Signals for the four output lines 16 generated. As a result, as shown in FIG. 3, an assignment address signal "11" on the assignment address bus 8 is converted such that the logic level "0" is present on the output line ZSEL1, while the logic level "1" is present on the other output lines ZSEL2, ZSEL3 and ZSEL4.

FIG. 4 shows the allocation memory 10 from FIG. 2 in more detail. As can be seen particularly well in this view, the address bus 5, which is fed to the allocation memory 10, here only comprises two address lines ADR0 and ADR1. Corresponding to the number of individual lines of the address bus 5, two allocation memory cells 19 and 20 are provided in the allocation memory 10. In this case, the assignment memory cell 19 is connected on the input side (DATA connection) to the ADR0 line of the address bus 5, while the assignment memory cell 20 is connected on the input side (DATA connection) to the ADR1 line of the address bus 5. With an increasing number of individual lines of the address bus 5, an increasing number of allocation memory cells is necessary in order to ensure correct address decoding.

Furthermore, a validation memory cell 21 is provided in the allocation memory 10, which is connected on the input side (DATA connection) to the programming line ENA already mentioned in FIG. The two outputs Dout of the allocation memory cell 19 and the allocation memory cell 20 are each fed to an XNOR gate with two inputs, the other input of the XNOR gate being connected to the respective input terminal DATA of the allocation memory cell. The outputs of the two XNOR gates and the output Dout of the validation memory cell 21 are fed to an AND gate with three inputs. The output AI of the AND gate leads to the redundancy word line RXSEL1, as can best be seen in FIG. The allocation memory cells 19 and 20 and the validation memory cell 21 are each identical built up. They have programming inputs LATCH PLATE and DISABLE which are input lines to corresponding programming ^¬ connected to the assignment memory 10th It is essential that the allocation memory cells 19 and 20 and the validation memory cell 21 are connected in parallel with respect to the programming inputs PLATE and DISABLE. The programming input LATCH and the programming input SEL1, which is supplied by the assignment address decoder 15, are fed to an AND gate with two inputs, the output of the AND gate being fed to the inputs LATCH of the assignment memory cells 19 and 20 and of the validation memory cell 21.

FIG. 5 shows the allocation memory cell 19 from FIG. 4 in more detail. The allocation memory cell 19 is divided into a flip-flop 22, which is composed of two PMOS transistors P2 and P3 and two NMOS transistors N2 and N3, two ferroelectric capacitors C1 and C2, an input circuit N1, N4 and N5, which is composed of three NMOS transistors, and in a combined output and voltage control circuit, which is composed of a NOR gate with two inputs and a PMOS transistor Pl. The input circuit Nl, N4 and N5 enables the data-dependent control of the "left" and "right" nodes with 0 volts in a simple manner. Due to the good driver capability of the NMOS transistors Nl, N4 and N5 for 0 volts, the circuit can be implemented with a small area. The output circuit with the NOR gate prevents an intermediate level between 0 volts and Vdd at the node "left" from leading to cross current losses when the latch supply is switched off.

FIG. 6 shows the programming of a logic “0” state in the memory cell 19 from FIG. 5. During the entire process, the DISABLE signal is kept at logic “0”. Starting from an undefined, unstable initial state, LATCH = logic "1" and WEN = logic "0" Writing path opened. The logical "0" on DATA is saved with the falling edge of LATCH. Here the node "left" goes to Vdd, which polarizes Cl to logic "1", since PLATE is at 0 volts. In the following cycle, PLATE is raised to Vdd, whereby C2 is polarized to "0" if it has not already had this state.

FIG. 7 shows the programming of the logic state "1" in the memory cell 19. The process of programming a logic state "1" in the memory cell 19 is essentially analogous to the programming of the state "0" in FIG. 6 described in FIG. 8. DISABLE = "0" applies throughout the entire process, with LATCH = "1" and WEN = "0" opening the write path.

FIG. 8 illustrates a read operation from the allocation memory cell 19.

LATCH = "0" applies throughout the process. The reading process typically takes place first after the supply voltage has been switched on. The information stored in the ferroelectric capacitors C1, C2 is then restored in the flip-flop 22 and automatically rewritten in the ferroelectric capacitors C1, C2. The read cycle begins with the signals PLATE = 0 volt and DISABLE = Vdd. A PLATE transition from 0 volts to Vdd pumps a positive charge into the "left" and "right" nodes, which is greatest when Cl is polarized to "1" (represented by the larger capacitance in the model). If C2 is polarized to "1" and Cl is polarized to "0" (in the model: Cl <C2), the node "right" is pumped to a greater positive voltage than the node "left". "N" is then additionally discharged via N2. Switching on the flip-flop 22 with DISABLE = "0" amplifies and stores the level difference. The output Dout accordingly goes to Vdd. In the event that the capacitance C1 is at "1" and that the capacitance C2 is at "0" is read out analogously.

When interpreting the simulation results for programming and reading according to FIGS. 6 to 8, it should be noted that for the simulation the programmed state "1" of the ferroelectric capacitors is simulated by an increase in capacitance compared to the deleted state "0".

The data memory 1 according to the invention behaves in operation as described below with reference to FIGS. 1 to 4. For this purpose, it is assumed that it was found after the production of the data ^¬ memory 1 in a test operation, the memory cell Sl is defective and that the working properly as found-out redundancy memory cell RSl is to take over their function.

When programming the data memory 1 in such a way that the function of the memory cell S1 is taken over by the redundancy memory cell RS1, a word line address "00" is created on the address bus 1, which selects the word line XSEL1. For this purpose, the value logic "00" is generated on the two selection lines ADR0 and ADR1 of the address bus 5 (see FIG. 4).

Since the allocation memory 10 allocates the redundancy memory cell RS1, the allocation memory 10 must be selected for its programming. This takes place in that an association address "00" is selected on the association address bus 8, which selects the association memory 10 via the output line 16 (cf. FIG. 2 and FIG. 3). As shown in FIG. 3, this is done in that the logical address "11" is applied to assignment address lines ZADR1 and ZADR2. Thereupon, a state of logic "0" appears on the output line ZSEL1, while the other output lines ZSEL2, ZSEL3 and ZSEL4 each on the logic level "1". Furthermore, the input line ENA (see FIG. 2 and FIG. 4) is also brought to the logic "1" state. Now the programming is enabled with a signal WEN = logic "0" (cf. NOR gate in FIG. 2), the allocation memory 10 being activated, while the remaining allocation memories 11, 12 and 13 remain deactivated. Programming is carried out with a positive pulse on the programming line LATCH (cf. AND gate in FIG. 4). The remaining programming lines PLATE and DISABLE are kept in states during the programming, as are given in FIG.

In this way, the values are written logically "0" in the allocation memory cell 19 and in the allocation memory cell 20, specifically in accordance with the logic values present on the selection lines ADR0 and ADR1. In the validation memory cell 21, after programming, there is also the value logic "1" corresponding to the logic "1" value present on the input line ENA. As a result, the redundancy memory cell RS1 is assigned to the memory cell S1 after programming.

In operation, the data memory 1 programmed as above behaves as described below. For this purpose, it is assumed that an attempt should be made to access the memory cell S1 during operation of the data memory 1. For this purpose, the address data logically "00" is created on the selection lines ADR0 and ADR1 of the address bus 5 (cf. FIG. 4). The programming lines ENA, SEL1, LATCH, PLATE and DISABLE have no function during the operation of the data memory 1, they are kept deactivated.

At the two inputs of the XNOR gates shown in FIG. 4, the value is then logically "0", specifically because of the value "logical" 0 supplied by the selection lines ADR0 and ADR1 and because of the value of the Assignment memory cell 19 and 20 value supplied and stored logically "0" during programming. The outputs of the XNOR gates in FIG. 4 then generate the value logic "1", which is fed to the AND gate in FIG. 4. In the validation memory cell 21, due to the programming, the value is logic "1", which is also fed to the AND gate with three inputs in FIG. 4. The output of the AND gate with three inputs in FIG. 4 thus changes to logic "1", which selects the redundancy word line RXSEL1 (see FIG. 2). In this way, the word line RXSEL1 belonging to the redundancy memory cell RS1 is selected when the address pointing to the memory cell S1 is present on the address bus 5. Since the outputs A2, A3 and A4 of the allocation memories 11, 12 and 13 (cf. FIG. 2) are in the state 0, while the output AI of the allocation memory 10 has the value logic "1", the output DIS of the deactivation switch 14 takes on in Figure 2 the value logically "1". This deactivates the address decoder 4 (see FIG. 1), so that interactions between the output of the memory cell S1 and the output of the redundancy memory cell RS1 are prevented.

In summary, it can be said that during the normal operation of the data memory 1, the contents of the assignment memory cells 19, 20 are compared with the selection signals applied to the address bus 5 and an activation signal AI = 1 is generated, if necessary. The remaining allocation memories 11, 12 and 13 operate essentially in the same way.

Claims

claims

1. Data memory which has the following features: at least one memory cell array (2) which has memory cells (S1), the

Memory cells (S1) can be selected by applying at least one selection signal to selection lines (XSEL 1, ..., XSEL n) provided in the area of the memory cells (S1), ^• the selection lines being word lines and / or

Can include bit lines. a redundancy circuit (3, 7) which has at least one redundancy memory cell (RSl), the redundancy memory cells (RSl) by applying at least one redundancy selection signal to im

The redundancy selection lines (RXSEL1, ..., RXSEL4) provided in the area of the redundancy memory cells (RS1) can be selected, the redundancy selection lines being able to include redundancy word lines (RXSELl, ..., RXSEL4) and / or redundancy bit lines, a redundancy selection line selection circuit, in the at least one assignment information can be stored, the redundancy selection line selection circuit being designed such that at least one redundancy selection line is based on the assignment information

(RXSELl) to at least one selection line

(XSEL1) can be assigned is characterized by the following feature: the redundancy selection line selection circuit has at least one ferroelectric assignment memory (10, 11, 12, 13) for receiving the assignment information or the assignment information.

2. Data memory according to claim 1, characterized in that it has the following features: at least one address decoder (4) which is connected between an address bus (5) and the selection lines (XSEL 1, ..., XSEL n) and so it is designed that one or more selection lines (XSEL 1,..., XSEL n) can be selected according to an address present on the address bus (5), - at least one redundancy address decoder (7), which is connected between the address bus (5) and the redundancy Selection lines (RXSEL 1, ..., RXSEL 4) is connected and is designed so that one or more redundancy selection lines (RXSEL 1, ..., RXSEL 4) correspond to one on

Address bus (5) present address are selectable, and the redundancy selection line selection circuit is arranged in the area of the redundancy address decoder (7).

3. Data memory according to claim 2, characterized in that the address decoder (4) is designed such that it can be deactivated by the redundancy address decoder (7).

4. Data memory according to claim 2 or claim 3, characterized in that it has the following features: the address bus (5) is designed as a parallel bus with a number of address bus lines (ADRO, ADR1), the ferroelectric allocation memory (10, 11, 12th , 13) has ferroelectric allocation memory cells (19, 20), the number of ferrolelectric allocation memory cells (19, 20) being equal to the number of address bus lines (ADRO, ADR1).

5. Data memory according to claim 4, characterized in that the ferroelectric allocation memory (10, 11, 12, 13) has at least one ferroelectric validation memory cell (21) with a validation address line (ENA).

6. Data memory according to one of the preceding claims, characterized in that it has the following features: - The redundancy selection line selection circuit has a plurality of ferroelectric allocation memories

(10, 11, 12, 13) to accommodate the

Assignment information is provided in the area of the assignment memory cells (19, 20). Assignment address lines (SEL1, ..., SEL4) are provided, whereby at least one assignment address line (SEL1, ..., SEL4) is applied to at least one ferroelectric assignment memory (10 , 11, 12, 13) is selectable.

7. Data memory according to claim 6, characterized in that at least one between a map address bus (8) and the map address lines (SEL1, ..., SEL4) map memory selection decoder (15) is provided, which is designed such that one or more map address lines ( SEL1, ..., SEL4) can be selected according to an address on the assignment address bus (8).

Data memory according to one of Claims 1 to 7, characterized in that an allocation memory cell (19, 20) is provided which has at least one ferrolectrical component (C1, C2) as the first memory element.

9. Data memory according to claim 8, characterized in that the ferroelectric component is designed as a ferroelectric capacitor (Cl, C2).

10. Data memory according to claim 8, characterized in that the ferroelectric component is designed as a ferroelectric field effect transistor.

11. Data memory according to one of claims 8 to 10, characterized in that at least one flip-flop module (22) is provided as a second memory element, the first memory element or the first memory elements (Cl, C2) being actuated by the second memory element is or are trained.

12. allocation memory cell (19) for receiving allocation information, in particular for a redundancy selection line selection circuit, wherein the allocation memory cell (19) has at least one ferroelectric allocation memory element (Cl, C2).

13. allocation memory cell according to claim 12, characterized in that two ferroelectric allocation memory elements (Cl, C2) are provided.

14. allocation memory cell according to claim 12 or claim 13, characterized in that the ferroelectric allocation memory element or the ferroelectric allocation memory elements are designed as ferroelectric capacitances (Cl, C2).

15. allocation memory cell according to one of claims 12 to 14, characterized in that a programming circuit (22) is provided which is designed such that the ferroelectric assignment ^¬ storage ^element or the ferroelectric assignment ^¬ storage ^elements (Cl, C2) are programmable to predetermined states.

16. allocation memory cell according to claim 15, characterized in that the programming circuit is designed as a flip-flop (22) with at least one output (left, right) which is connected to the ferroelectric allocation memory element or which are with the ferroelectric allocation memory elements (Cl, C2) .

17. allocation memory cell according to claim 16, characterized in that the programming circuit is designed as a flip-flop (22) having a first pair of MOS transistors (P2, N2) and a second pair of MOS transistors (P3, N3), the Channel connections are each connected in series, a first ferroelectric assignment memory element (Cl) being provided at the connection point (left) between two channel connections of the first pair of MOS transistors (P2, N2) and a second ferroelectric assignment memory element (C2) at the connection point ( right) between two channel connections of the second pair of MOS transistors (P3, N3) is provided.

18. allocation memory cell according to one of claims 15 to

17, characterized in that an input circuit (Nl, N4, N5) is provided which is designed such that the programming circuit (22) can be operated selectively.

19. allocation memory cell according to one of claims 15 to 18, characterized in that an output circuit (Pl, NOR) is provided which is designed such that the ferroelectric allocation memory element or the ferroelectric allocation memory elements (Cl, C2) can be read out selectively or are .