WO1998033184A1

WO1998033184A1 - Reference cell system for memories based on ferroelectric memory cells

Info

Publication number: WO1998033184A1
Application number: PCT/US1997/024282
Authority: WO
Inventors: Richard Womack
Original assignee: Radiant Technologies, Inc.
Priority date: 1997-01-27
Filing date: 1997-12-31
Publication date: 1998-07-30
Also published as: AU5906098A

Abstract

A memory (500) for storing a plurality of words of data. Each of the words includes N data bits, where N is an integer greater than 1. The memory (500) includes a plurality of storage cells, each of the word storage cells having N + 1 single bit memory cells (512, 513, 514, 517). The single bit memory cells (512, 513, 514, 517) are numbered from 1 to N + 1. Each of the single bit memory cells (512, 513, 514, 517) connects a conductor in a word bus common to all of the memory cells in that word to a bit line that is connected in common to all of the single bit memory cells (512, 513, 514, 517) having the same number. The word bus also includes a conductor for transmitting a signal indicating that this connection is to be made. Each of the single bit memory cells (512, 513, 514) having a number between 1 and N stores one of the N data bits. The memory (500) also includes N sense amplifiers (550, 560, 570), one of the sense amplifiers (550, 560, 570) being connected to each of the bit lines to which the bits numbered 1 to N are connected. Each of the sense amplifiers (550, 560, 570) compares a signal on the bit line (551-553) connected thereto to a signal on the bit line (557) connected to the single bit memory cells (517) numbered (N + 1). When data is written into the data bits of the word, a predetermined value is preferably written into the single bit memory cell (517) number N + 1. Embodiments of the present invention based on ferroelectric FET memory cells (10) or ferroelectric capacitor-based memory cells (100) are preferred.

Description

REFERENCE CELL SYSTEM FOR MEMORIES BASED ON FERROELECTRIC

MEMORY CELLS

Field of the Invention

The present invention relates to static memory cells, and more particularly, to memory systems based on ferroelectric memory cells.

Background of the Invention

Memory cells based on ferroelectric dielectrics have been known for some time. The simplest form of ferroelectric memory cell is based on a capacitor having a ferroelectric dielectric. Information is stored in the capacitor by setting the direction of the remnant polarization of the dielectric. The information stored in the memory cell may be read by observing the transient current generated when a potential is placed across the dielectric. If the applied potential causes the polarization to change directions, a current flows. If the applied potential does not change the direction of polarization, no current flows.

A second type of ferroelectric memory cell is described in U.S. Patent 5,070,385.

This type of memory cell utilizes a ferroelectric FET. The memory cell consists of a semiconductor layer that overlies a ferroelectric layer. The direction of polarization of the underlying ferroelectric layer determines the electric field in which the semiconductor layer functions. Data is stored in the direction of polarization of the ferroelectric layer. The data is sensed by measuring the resistivity of the semiconductor layer between two electrodes that are analogous to the source and drain in a conventional FET. The polarization of the underlying ferroelectric layer is set by applying voltages across the ferroelectric layer. These voltages are applied with the aid of a third electrode which is analogous to the gate of a conventional FET.

While both types of memory cells have been known for some time, commercially successful memories based on these cells have been lacking. Both types of memory cells exhibit characteristics which change with time. In the case of memory cells based on ferroelectric capacitors, the memory cells suffer from two problems, commonly referred to as "imprint" and "fatigue". Imprint is the tendency of a ferroelectric capacitor to exhibit a shift of its hysteresis curve along the voltage axis in either the positive or negative direction depending on the data stored therein. This tendency can lead to a logic state failure for either of two reasons. First, after a sufficient shift, both logic states appear the same to a sense amplifier. Second, the coercive voltage becomes too large to be switched by the available programming voltage. When either case is encountered, a memory cell based on the capacitor becomes useless.

Fatigue is a decrease in the magnitude of the remnant polarization of the dielectric layer with the number of times the direction of polarization is changed. Since the amount of charge displaced when the capacitor is switched is related to the remnant polarization, the capacitor finally reaches a point at which there is insufficient charge displaced to detect. At this point, a memory cell based on the capacitor also becomes useless.

Memory cells based on ferroelectric FETs also suffer from aging problems. Data is represented by two resistance states, a high resistance state and a low resistance state. Once the data is stored, the resistance states slowly shift. If the data corresponds to the high resistance state, the resistance of this state tends to decrease over time until it is no longer distinguishable from the low resistance state. Similarly, if the device is set to the low resistance state, the resistance tends to increase with time. However, unlike memory cells based on ferroelectric capacitors, the shift in state is corrected each time a memory cell is rewritten.

The performance of both types of memory cells is also degraded by non-uniformity in the semiconductor fabrication steps over the area of the memory. For example, variations in the thickness of the ferroelectric layers over the memory can lead to devices that exhibit different characteristics even for the same memory state. Such variations further reduce the operating lifetime of a memory.

One method for improving the useful lifetime of both types of memories relies on placing reference cells within the memory. The sense amplifiers that read the currents generated by the devices compare the current from a memory cell corresponding to a bit in a word of memory with the current generated from a reference cell having known data stored therein. To the extent that the reference cell undergoes the same aging process as the memory cell, a reference cell can measure the degree of aging and partially correct for the aging effect. Similarly, the reference cell can provide a calibration for the parameters that depend on the semiconductor processing steps used in the fabrication of the device.

Prior art memories have utilized two types of reference cell configurations. The most useful type of reference cell configuration utilizes one reference cell for each memory cell, and places the reference cell next to its corresponding memory cell. The reference cell is then read and written in parallel with the data cell. This configuration assures that the reference cell has been generated with the same layer thicknesss and other processing conditions as its corresponding memory cell, and that the reference cell has the same read-write history as the corresponding data cell. While this memory configuration provides the greatest degree of correction for the aging effects and fabrication non-uniformities, it doubles the size of the memory array, and hence, substantially increases the cost of memories utilizing this configuration.

The second configuration taught in the prior art utilizes one reference cell for each column in the memory. In general, a large memory is constructed from a rectangular array of bits organized as a plurality of rows and columns. Each row includes one or more words consisting of a predetermined number of bits. The bits of a word are read and written together. These bits are connected to bit lines that connect all of the bits in a given column to a sense amplifier and write circuitry. The specific word that is read at any time is determined by which row is selected. The output of the reference cell is routed to the sense amplifier for the column in question. The sense amplifier then compares the reference cell to the cell connected to it on the corresponding bit line.

While this second configuration requires significantly fewer reference cells, it cannot correct for processing non-uniformities or aging effects that depend on the read- write history of a particular bit. The reference cells cannot have the same read- write history as the bits to which they are compared, since the read- write history of all of the bits in a column will, in general, be different. Similarly, the reference cells are located at the end of the columns, and hence, experience different process non-uniformities than memory cells located far from the reference cells in the array.

Broadly, it is the object of the present invention to provide an improved ferroelectric- based memory.

It is a further object of the present invention to provide a ferroelectric memory having reference cells that experience substantially the same fabrication environment as the corresponding data cells.

It is yet another object of the present invention to provide a ferroelectric memory having reference cells that experience substantially the same read-write history as the corresponding data cells.

These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.

Summary of the Invention

The present invention is an improved memory for storing a plurality of words of data. Each of the words includes N data bits, where N is an integer greater than 1. The memory includes a plurality of storage cells, each of the word storage cells having N+l single bit memory cells. The single bit memory cells are numbered from 1 to N+l. Each of the single bit memory cells connects a conductor in a word bus common to all of the memory cells in that word to a bit line that is connected in common to all of the single bit memory cells having the same number. The word bus also includes a conductor for transmitting a signal indicating that this connection is to be made. Each of the single bit memory cells having a number between 1 and N stores one of the N data bits. The memory also includes N sense amplifiers, one of the sense amplifiers being connected to each of the bit lines to which the bits numbered 1 to N are connected. Each of the sense amplifiers compares a signal on the bit line connected thereto to a signal on the bit line connected to the single bit memory cells numbered (N+l). When data is written into the data bits of the word, a predetermined value is preferably written into single bit memory cell number N+l . Embodiments of the present invention based on ferroelectric FET memory cells or ferroelectric capacitor-based memory cells are preferred. The single bit memory cells that make up a word are preferably located adjacent to one another in the memory.

Brief Description of the Drawings

Figure 1 is a schematic drawing of a single bit memory cell based on a ferroelectric capacitor.

Figure 2 is a cross-sectional view of a ferroelectric FET.

Figure 3 is a schematic drawing of a single bit memory cell based on a ferroelectric

FET.

Figure 4 is a schematic drawing of a prior art memory employing one reference cell per data bit.

Figure 5 is a schematic drawing of a memory according to the present invention.

Detailed Description of the Invention

A ferroelectric memory cell based on a ferroelectric capacitor consists of a ferroelectric capacitor 102 combined with an n-channel transistor 104 as shown in Figure 1 at 100. The ferroelectric material of the capacitor has an electrically reversible remnant polarization. When reversed, a large compensating electrical charge must flow between the two plates of the capacitor. Transistor 104 acts as a switch that connects capacitor 102 to the bit line 106 in response to a signal on word line 107. A sensing circuit 109 measures the flow of charge into capacitor 102. To execute a write, the word line is activated to turn on transistor 104, bit line 106 is set high or low, and then the plate line 108 is pulsed. The direction of polarization of the capacitor is set by the state bit line 106.

To execute a read, transistor 104 is turned on, and plate line 108 is pulsed. The charge on the capacitor is forced onto bit line 106 where it is measured by sense circuit 109. If the capacitor polarization is switched by the read pulse, a large current will flow on bit line 106. If, on the other hand, the polarization of capacitor 102 is already oriented in the direction provided by the read pulse, only a small current will flow on bit line 106. In either case, the polarization will be pointing in the direction specified by the read pulse after the read operation, independent of the original direction of polarization of capacitor 102. If the data was destroyed by the read operation, sense circuit 109 re-writes the correct data after the read operation.

Refer now to Figure 2 which is a cross-sectional view of a ferroelectric FET 10.

Ferroelectric FET 10 is constructed on a substrate 12 by first depositing the gate electrode 14. The ferroelectric layer 16 is then deposited over the gate electrode and etched to the appropriate size. The semiconductor layer 18 is then deposited on the ferroelectric layer and two electrodes 21 and 22 corresponding to the source and drain are deposited on semiconductor layer 18. The choice of which electrode is labeled as the "source" is arbitrary.

Data is stored in ferroelectric FET 10 by setting the direction of polarization of ferroelectric layer 16. In three terminal operation, the direction of polarization is set by applying a potential difference across ferroelectric layer 16 using a circuit that holds the source and drain at the same potential. For example, the polarization of the ferroelectric layer may set in one direction by applying 5 volts to the source and drain while holding the gate at ground. The opposite state is set by holding the source and drain at ground and applying a potential of 5 volts to the gate. It should be noted that this write scheme results in the direction and magnitude of the polarization of the ferroelectric layer being the same at all points between the source and the drain. Refer now to Figure 3 which is a schematic drawing of a single bit memory cell 300 connected to the various lines needed to read and write the bit in a memory. Single bit memory cell 300 includes pass transistors 302 and 304 and a ferroelectric FET 303. The pass transistors connect ferroelectric FET 303 between a source line 320 and a bit line 310 when the word lines 312 and 313 are high. The cell is read by measuring the current that flows in bit line 310 when a small potential is applied to source line 320. Data is written into ferroelectric FET 303 by applying a signal indicative of the data on bit line 310 and pulsing gate line 322 and source line 320 in the appropriate order. The details of the write cycle are described in U.S. Patent 5,070,385 which is hereby incorporated by reference. Alternatively, data may be written by putting a signal indicative of the data both the bit line and source line simultaneously and then pulsing the gate. Since the present invention does not depend on these details, they will not be described in more detail here.

Single bit memory cells based on ferroelectric FETs in which pass transistor 302 is absent have also been described in a copending U.S. patent applications Serial Numbers

08/592,629 and 08/663,675 which are also incorporated by reference. In this type of memory cell, the source and gate lines are connected together during the read operations. There are two possible modes of writing such a memory cell. The first utilizes a scheme in which the source and gate lines remain shorted during the write. The second utilizes a scheme in which the source and gate lines are independently pulsed during a write. The first scheme requires significantly less circuit area than the design shown in Figure 3; however, the difference in resistance that must be sensed by a sense amplifier connected to the bit line to determine whether a "1" or a "0" is stored is considerably less than that provided by memory cell 300. The second scheme provides a difference in resistances that is comparable to that obtained with memory cell 300 while requiring only slightly more circuit area than that of the first scheme.

As noted above, the present invention does not depend on the specific connection scheme utilized for the single bit memory cell. Hence, a ferroelectric FET memory cell may be represented by a 4 terminal circuit having connections for a word line, source, line, gate line, and bit line. The word line, source line, and gate line run horizontally across the array while the bit line runs vertically. The word line, source line and gate line are common to all single bit memory cells in a word. Hence, these lines will be referred to as the word bus in the following discussion. While the embodiments described below will utilize this arrangement, it should be noted that the only requirement for operation in the modes described below is that the bit line runs perpendicular to the word line. Hence, embodiments in which the bit line is part of the word bus while the word line runs perpendicular to the word bus are also possible.

It should be noted that a word of memory based on ferroelectric capacitor single bit memory cells is similar in organization to a word based on ferroelectric FETs in that the word has a horizontal bus consisting of the plate and word lines which are common to all single bit memory cells in a word. The memory cell also connects to a vertically running bit line which is shared by all bits at a given position in the word. Hence, to simplify the following discussion, a single bit memory cell will be assumed to have terminals for providing connections to a word bus and to a bit line. The details of the connections within the single bit memory cell or its type of ferroelectric storage device will not be discussed further, except in those cases in which ferroelectric capacitor based memory cells differ from ferroelectric FET based memory cells.

Refer now to Figure 4 which is a schematic drawing of a prior art memory 400 based on ferroelectric capacitor single bit memory cells. The memory is organized into words, exemplary words being shown at 410, 420, and 430. Each word is constructed from a plurality of single bit memory cells. The single bit memory cells corresponding to word 410 are shown at 412-414. If the memory is organized into N-bit words, there will be N bit lines, one corresponding to each bit of a word. Single bit memory cells occupying the same bit position in different words are connected to the same bit line. The bit lines corresponding to the first, second, and N^,h bit positions are shown at 451-453, respectively. Each single bit memory cell has a reference cell associated therewith. The reference cells corresponding to single bit memory cells 412-414 are shown at 415-417, respectively. The reference cells are also connected to bit lines, referred to as "reference bit lines". Exemplary reference bit lines are shown at 455-457. Each pair of bit lines, one bit line and one reference bit line, terminate on a sense amplifier which compares the voltage on the bit line with that on the reference line to determine the data stored in the single bit memory cell connected to the bit line. Exemplary sense amplifiers are shown at 450, 460, and 470. The specific word to be read is specified by signals on the word bus running through the bits of that word.

Data is written into a word by placing the data on the bit lines and applying the proper signal sequence on the word bus corresponding to the word to be written. The references cells are also written at the same time. The data to be written into the reference cells is placed on the reference bit lines. In some embodiments, the reference data is fixed independent of the data written into the single bit memory cells. In other embodiments, the reference data is the complement of the data written into the corresponding single bit memory cell.

The arrangement shown in Figure 4 provides a reference system that takes into account the "history" experienced by each single bit memory cell and any non-uniformities resulting from variations in semiconductor processing over the wafer in which the memory was constructed. Unfortunately, the cost of this system as measured in area of silicon needed per bit of data stored is twice that of a system lacking reference cells. The present invention provides the advantage of reference cells taking into account the "history" experienced by each single bit memory cell and any non-uniformities resulting from variations in semiconductor processing over the wafer in which the memory was constructed while imposing only a small increase in cost.

Refer now to Figure 5 which is a schematic drawing of a memory according to the present invention. Memory 500 differs from memory 400 shown above in that a single reference cell is used for each word. If a word has N data bits, then the word has N+l single bit memory cells located adjacent to one another. Exemplary words are shown in Figure 5 at 510, 520, and 530. The first, second, and Nth data bits are stored in single bit memory cells 512-514, respectively, in word 510. The corresponding reference memory cell for word 510 is shown at 517. The memory cells are connected to bit lines in which terminate in sense amplifiers. The bit lines for the first, second, and Nth bits of each word are shown at 551- 553, respectively. The corresponding sense amplifiers are shown at 550, 560, and 570, respectively. The reference cells are connected to a reference bit line 557. The reference bit line is routed to each of the sense amplifiers. The reference cell is compared to each of the data cells to determine the value stored in the data cell. When the word is written, the reference cell is also written. Hence, the reference cell has the same history as the cells storing the data bits. The choice of the value to be written into the reference cell will, in general, depend on the type of memory cell. In ferroelectric FET based systems, it has been found experimentally that a value corresponding to the low resistance state for the source to drain connection is the most reproducible from memory cell to memory cell. Hence, in ferroelectric FET based cells, the reference cell is written with the data value that corresponds to the low resistance state.

The present invention provides the advantages of a reference cell located proximate to the data storage cells while requiring only one reference cell per word. The proximity of the reference cell to the other data storage cells allows the reference cell to compensate for processing non-uniformities in the fabrication of the device. Since the reference cell is read and written each time the data word is written, the reference cell has the same read- write history as the data storage cells.

The above described embodiments of the present invention have assumed that the single bit memory cells were constructed from ferroelectric based memory cells. However, it will be obvious to those skilled in the art from the preceding discussion that the principles of the present invention may be applied to any type of memory cell in which the history of the device and or processing non-uniformities in the construction of the device require the introduction of a reference cell. Examples of other types of single bit memory cells are magneto-resistive memory cells and ferroelectric memory cells in which data is stored in the direction of polarization of the ferroelectric layer, but the ferroelectric layer is placed in a different relationship to the various electrodes and gate transistors from the arrangements described above.

It should also be noted that the present invention requires only N sense amplifiers for an N-bit word, independent of the number of blocks of N-bit words into which the memory is divided. If the memory is divided into a number of blocks that are separately decoded, the bit lines from each block can be multiplexed together such that all of the blocks share the same sense amplifiers. Various modifications to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims.

Claims

WHAT IS CLAIMED IS:

1. A memory [500] for storing a plurality of words of data, each of said word including N data bits, where N is an integer greater than 1, said memory [500] comprising:

a plurality of word storage blocks[510, 520, 530], each of said word storage blocks[510, 520, 530] comprising N+l single bit memory cells[512, 513, 514, 517], numbered from 1 to N+l, each of said single bit memory cells[512, 513, 514, 517] connecting a conductor that is common to all of said memory cells in that word storage block to a bit line[551, 552, 553, 557] that is connected in common to all of said single bit memory cells[512, 513, 514, 517] having the same number, said word storage block[510, 520, 530] also including a conductor[107] for transmitting a signal indicating that said connection is to be made, each single bit memory cell having a number between 1 and N storing one of said N data bits; and

N sense amplifiers[550, 560, 570], one sense amplifier being connected to each of said bit lines[551, 552, 553] to which bits 1 to N are connected, each sense amplifier[550, 560, 570] comparing a signal on said bit line[551-553] connected thereto to a signal on said bit line [557] connected to said single bit memory cells[517] numbered N+l.

2. The memory [500] of claim 1 further comprising means for writing a predetermined value into said single bit memory cell number N+l each time a value is written into the bits numbered 1 to N.

3. The memory [500] of claim 1 wherein said single bit memory cells[512, 513, 514,

517] comprise a ferroelectric FET[10].

4. The memory[500] of claim 1 wherein said single bit memory cells[512, 513, 514, 517] comprise a capacitor[102] having a dielectric comprising a ferroelectric material.

5. The memory [500] of claim 1 wherein said single bit memory cells[512, 513, 514, 517] in each of said word storage blocks[510, 520, 530] are located adjacent to one another in said memory[500].