WO1998031105A1 - Convertisseur analogique-numerique delta sigma - Google Patents

Convertisseur analogique-numerique delta sigma Download PDF

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Publication number
WO1998031105A1
WO1998031105A1 PCT/US1998/000311 US9800311W WO9831105A1 WO 1998031105 A1 WO1998031105 A1 WO 1998031105A1 US 9800311 W US9800311 W US 9800311W WO 9831105 A1 WO9831105 A1 WO 9831105A1
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WIPO (PCT)
Prior art keywords
signal
analog
output signals
produce
digital output
Prior art date
Application number
PCT/US1998/000311
Other languages
English (en)
Inventor
Brian Victor Cake
Thomas Coutts Leslie
Original Assignee
Phoenix Vlsi Consultants
Lecroy Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/IB1998/000011 external-priority patent/WO1998031143A2/fr
Application filed by Phoenix Vlsi Consultants, Lecroy Corporation filed Critical Phoenix Vlsi Consultants
Priority to AU59097/98A priority Critical patent/AU5909798A/en
Priority to EP98902427A priority patent/EP1012983A4/fr
Publication of WO1998031105A1 publication Critical patent/WO1998031105A1/fr
Priority to US09/351,250 priority patent/US6292121B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/74—Projection arrangements for image reproduction, e.g. using eidophor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/466—Multiplexed conversion systems
    • H03M3/468—Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters
    • H03M3/47—Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/402—Arrangements specific to bandpass modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path

Definitions

  • the present invention relates to analog to digital conversion, and, more particularly, is directed to a delta sigma type of analog to digital converter.
  • Delta sigma converters also referred to as sigma delta modulators, convert a signal amplitude into digital data.
  • An input signal at a given frequency f 0 is oversampled, that is, sampled at a rate f s much higher than the Nyquist rate, f s >> 2f 0 .
  • the output signal comprises a one-bit data pulse stream having a time average amplitude proportional to the amplitude of the input signal.
  • Quantization of the input signal introduces errors, that is, noise, into the output signal.
  • a major advantage of delta sigma converters is their ability to shape the quantization noise spectrum, specifically, to move the noise from low frequencies into high frequencies. The output data is then low pass filtered to remove the noise.
  • a single bit first order delta sigma converter is shown in Fig. 1 as including subtractor 20, integrator 30, analog-to-digital converter 40 comprising comparator 43 and latch 46, and digital to analog converter 50.
  • An input signal S IN having a maximum frequency f c is applied to an input terminal 10 which supplies the signal S IK to a subtractor 20.
  • the subtractor 20 subtracts a feedback signal from the present input signal to produce a difference signal, and applies the difference signal to an integrator 30.
  • the integrator 30 functions to add the difference signal to the sum of previous difference signals so as to generate an integrated signal, and to supply the integrated signal to a comparator 43.
  • the comparator 43 is operative to coarsely quantize the integrated signal into one of two levels, and to supply the quantized signal to a latch 46.
  • the latch 46 also receives a control signal at the sampling frequency f s from a clock generator (not shown) via input terminal 45, and is adapted to sample the quantized signal in response to the control signal and to supply the sampled value as an output D ou ⁇ to an output terminal 60 and to a digital to analog converter (DAC) 50.
  • DAC digital to analog converter
  • the comparator 43 finely quantizes the integrated signal to produce an output signal exhibiting more than two levels.
  • the DAC 50 receives the output signal D ou ⁇ and the control signal at the sampling frequency f s , and functions to convert the value D ou ⁇ to one of two output signal levels, and to supply the result as the feedback signal to the subtractor 20.
  • the feedback ensures that the average value of the quantized signal tracks the average input.
  • the architecture of a first order delta sigma converter is fairly simple. Relatively imprecise circuit components can be used due to the presence of the feedback loop .
  • a second order delta sigma converter is shown in Fig. 2 as comprising subtractors 110, 130, integrators 120, 140, comparator 153, latch 156 and DAC 160.
  • the second order delta sigma converter is generally similar to the first order delta sigma converter, except that the feedback signal is supplied to an "outer" subtractor 110 where it is combined with the input signal, and then integrated, before being applied to an "inner” subtractor 130.
  • An inner path comprising subtractor 130, integrator 140, comparator 153, latch 156 and DAC 160 serves to stabilize the system, and to determine the high frequency properties of the system.
  • An outer path including subtractor 110 and integrator 120 dominates in determining the low frequency properties of the system.
  • the rms noise n 0 in the signal band f 0 is given by: n, 2nd order e rms ( ⁇ r 4 /5 ) 1/2 ( 2 f 0 /f s ) 5 2 . . . ( eq . 2 )
  • Doubling the sampling frequency of a second order delta sigma converter decreases the in-band noise by 15 db, corresponding to an increase in resolution of 2.5 bits.
  • the second order delta sigma converter is seen to reduce the quantization noise, permitting improved resolution.
  • the second order delta sigma converter is less stable and less tolerant of component imprecision.
  • Delta sigma converters are generally used only with low frequency input signals, typically voice signals, due to the need for a high sampling frequency, specifically, a sampling rate up to several orders of magnitude higher than the Nyquist rate.
  • a sampling frequency specifically, a sampling rate up to several orders of magnitude higher than the Nyquist rate.
  • components operating at an appropriately high sampling frequency are expensive.
  • components operating at an appropriately high sampling frequency are unavailable.
  • delta sigma converters are described below with reference to the figures, for the purpose of background information enabling the skilled man to put the technology into practice.
  • an analog input signal is converted to at least two digital output signals as follows.
  • An analog feedback signal is subtracted from the analog input signal to produce a difference signal.
  • the difference signal is integrated to produce an integrated signal which is quantized to produce the digital output signals in response to respective control signals each having a predetermined frequency and being offset in phase from each other.
  • the digital output signals are converted into the analog feedback signal.
  • a digital sampling oscilloscope comprising an analog to digital converter for converting an analog input signal to at least two digital output signals .
  • an analog feedback signal is subtracted from the analog input signal to produce a difference signal which is integrated to produce an integrated signal.
  • the integrated signal is quantized to produce the digital output signals in response to respective control signals each having a predetermined frequency and being offset in phase from each other.
  • the digital output signals are then converted into the analog feedback signal.
  • the digital sampling oscilloscope further comprises a memory for storing the digital output signals, a processor for combining the stored digital output signals to produce a display signal, and a display for displaying the display signal .
  • Fig. 1 is a block diagram of a first order delta sigma converter
  • Fig. 2 is a block diagram of a second order delta sigma converter
  • Fig. 3 is a block diagram of an alternative delta sigma converter
  • Figs. 4A-4C are timing charts showing the relationship of the sampling frequencies used in the delta sigma converter of Fig. 3;
  • Fig. 5 is a block diagram of another delta sigma converter
  • Fig. 6 is a diagram of yet another delta sigma converter
  • Fig. 7 is a diagram of a portion of a further delta sigma converter
  • Figs. 8A-8C are timing charts referred to in explaining the operation of the delta sigma converter shown in Fig. 7.
  • Fig. 9 shows a digital sampling oscilloscope incorporating a delta sigma converter
  • Fig. 10 shows a delta sigma converter
  • Fig. 11 shows a delta sigma converter according to one aspect of the present invention
  • Fig. 12 shows a delta sigma converter according to the present invention
  • Fig. 13 shows a further delta sigma converter according to the present invention
  • Fig. 14 shows a delta sigma converter according to the present invention comprising a combination of the arrangements shown in Figs. 10-13.
  • the quantizer of a conventional delta sigma converter such as a comparator followed by a latch, is replaced with N quantizers, each operating at a reduced frequency f s /N and phase offset from each other by 2 ⁇ /N radians.
  • the quantized outputs are assembled in a digital to analog converter (DAC) in accordance with a control signal at a frequency f s to produce the feedback signal applied to the subtractor of the delta sigma converter.
  • DAC digital to analog converter
  • the delta sigma converter is discussed in relation to Figs. 3 to 9 below.
  • a delta sigma converter can use components operating at a lower frequency than the sampling frequency f s without loss of dynamic range relative to a conventional delta sigma converter.
  • an eight bit flash ADC requires 255 comparators to produce 255 levels which are converted into eight bits by an encoder having substantial amounts of logic and latches.
  • FIG. 3 there is illustrated an embodiment of a delta sigma converter.
  • the apparatus illustrated in Fig. 3 comprises subtractor 310, integrator 320, sampling comparators 330, 340, switch 350 and DAC 360.
  • An input signal S IN is applied to an input terminal 300 which supplies the signal S IN to subtractor 310.
  • the subtractor 310 functions to subtract a feedback signal from the current input signal to produce a difference signal, and applies the difference signal to an integrator 320.
  • the integrator 320 functions to add the difference signal to the sum of previous difference signals so as to generate an integrated signal, and to supply the integrated signal to sampling comparators 330, 340.
  • the sampling comparators 330, 340 are each operative to coarsely quantize the integrated signal into one of two levels, to sample the quantized signal in response to the control signal at a sampling frequency of f s /2 and to supply the respective sampled values as outputs D 0UT1 , D 0UT2 to output terminals 370, 380, respectively, and to switch 350.
  • the sampling clock signals supplied to the comparators 330, 340 are interleaved in time. As shown in Figs. 4A-4C, the sampling clock signal supplied to comparator 330 represents the odd pulses of the sampling clock signal f s , while the sampling clock signal supplied to comparator 340 represents the even pulses of the sampling clock signal f s . Alternatively, the sampling clock signal supplied to comparator 330 may be delayed by 180° to produce the sampling clock signal supplied to comparator 340.
  • the switch 350 receives the output signals D o ⁇ ,
  • D o u 2 each sampled at a rate of f s /2 and also receives a control signal at the frequency f s /2 from an input terminal 355, and is adapted to alternately select the quantized values D 0UT1 , D 0UT2 at twice the rate of the control signal.
  • the control signal may be inverted, with one terminal providing a positive pulse of the non-inverted signal and another terminal providing a positive pulse of the inverted signal.
  • the output of switch 350 thus is a signal at the desired sampling frequency f s , although each of the sampling comparators 330, 340 operates at a rate of f s /2.
  • the DAC 360 receives the switched outputs D 0UT1 , D 0UT2 and the control signal at the sampling frequency f s , and functions to convert the values D 0UT1 , D 0UT2 to one of two output signal levels, and to supply the result as the feedback signal to the subtractor 310.
  • Fig. 5 illustrates another embodiment of the delta sigma converter.
  • the apparatus illustrated in Fig. 5 comprises subtractor 510, integrator 520, sampling comparators 530, 540, DACs 550, 560 and switch 570.
  • the delta sigma converter of Fig. 5 operates in generally the same manner as the delta sigma converter of Fig. 3, except that the quantized outputs D 0UT1 , D 0UT2 are supplied to DACs 550, 560, respectively, instead of to a switch.
  • the DACs operate at the same frequency as the comparators, and are phase offset in the same manner.
  • the outputs of the DACs 550, 560 are supplied to inputs 570A, 570B, respectively, of switch 570.
  • a control signal at frequency f g /2 is also supplied to the switch 570 from a clock signal generator (not shown) via input terminal 575.
  • the switch 570 is operative to alternately select the outputs of the DACs 550, 560 to produce the feedback signal applied to subtractor 510.
  • the delta sigma converter comprises N comparators, each operating at a frequency of f s /N, and a switch having N inputs selected in turn at a rate of f s .
  • a delta sigma converter may also comprise N DACs, each operating at a frequency of f s /N.
  • the clock signals applied to the comparators and DACs are offset from each other by 2 ⁇ r/N.
  • the feedback signal is supplied to another "outer" path including 5 another subtractor and another integrator, as generally shown in Fig. 2.
  • the comparators in a delta sigma converter are identical, then the outputs, when assembled, provide a signal having a signal to noise ratio which is indistinguishable from
  • Assembly of the outputs D 0UT1 , D ou ⁇ 2 may be done by, for example, storing these values in alternate locations of a memory, such as addresses n, n+2, n+4 , ... for the outputs D 0UT1 , and addresses n+1, n+3 ,
  • the filtering may comprise averaging pairs of adjacent assembled outputs to produce filtered outputs D iJ OUT2 (n+ 1 ) I ) I /2 • i o r l (n+ 1 ) , -p, ( n+2 ) ⁇ / -y
  • a delta sigma converter may operate to quantize the integrated signal to more than two levels by using, for example, a flash A/D converter, instead of a comparator.
  • 35 conventional delta sigma converter cannot be constructed.
  • a delta sigma converter with two temporally interleaved latches is feasible.
  • a delta sigma converter with four temporally interleaved latches is also feasible, and exhibits an increase in resolution of 2.5 bits for a second order system. If eight temporally interleaved latches are used, then an increase in resolution of 5 bits is obtained for a second order system.
  • a delta sigma converter permits a tradeoff between number of components and resolution, with only a small increase in complexity relative to a conventional delta sigma converter.
  • the conventional tradeoff between sampling frequency and resolution is available in a delta sigma converter .
  • a delta sigma converter is seen to inherently produce demultiplexed digital outputs.
  • Fig. 6 shows another embodiment of a delta sigma converter similar to the delta sigma converter of Fig. 5.
  • the DAC reference current is switched, whereas in the delta sigma converter of Fig. 5, the DAC outputs are switched.
  • the delta sigma converter of Fig. 6 requires a clock operating at only f s /2 to achieve an effective switching rate of f s .
  • the delta sigma converter of Fig. 6 comprises current sources 610, 611, 618, 619, 650, voltage source 620, capacitor 612, resistor 617, transistors 613, 614, 615, 616, 652, 653, 654, 655, 656, 658, and sampling comparators 630, 640.
  • Transistors 613, 614, 615, 616 form a cascade differential amplifier.
  • the emitters of transistors 615, 616 are respectively connected to each of the terminals of resistor 617.
  • the collectors of transistors 613, 614 are respectively connected to each of the terminals of capacitor 612, and the bases of transistors 613, 614 are connected in common to a bias voltage V B .
  • the terminals of capacitor 612 are also connected to the collectors of transistors 652, 654, 656, 658.
  • Transistors 652, 654 form a DAC and transistors 656, 658 form another DAC.
  • the emitters of transistors 652, 654 are connected in common to the collector of transistor 653.
  • the emitters of transistors 656, 658 are connected in common to the collector of transistor 655.
  • Transistors 653, 655 are adapted to switch the reference current of the DACs formed by transistors 652, 654 and 656, 658.
  • Comparator 630 is coupled to the DAC formed by transistors 652, 654, and comparator 640 is coupled to the DAC formed by transistors 656, 658.
  • the circuit consisting of transistors 613, 614, 615, 616, resistor 617 and current sources 610, 611, 618, 619 is a differential transconductance circuit which functions to convert the input signal S IN into a differential current which is output from the collectors of transistors 613 and 614.
  • Capacitor 612 is adapted to sum the negative feedback current signal with the input current signal and a signal already present on the capacitor, and to supply the result as an integrated signal to comparators 630, 640.
  • the comparators 630, 640 function to quantize the integrated signal, that is, to compare the integrated signal with a predetermined threshold, to produce one value if the signal is at least equal to the threshold and another value if the signal is less than the threshold, and to hold the resulting value until the next sampling instant.
  • Transistors 653, 655 act to switch, that is, to enable or disable the DAC transistor pairs 652, 654 and 656, 658.
  • transistor 653 When transistor 653 is enabled by the sampling clock signal 620, current from current source 650 flows to the common emitters of transistors 652, 654. If D 0UT1 is a logic "0”, then all current form source 650 flows through the collector of transistor 654. If D 0UT1 is a logic "1”, then all current from source 650 flows through the collector of transistor 652. Thus, the feedback signal corresponds to the value D 0UT1 from comparator 630.
  • Provision of phasing so that the feedback signal is negative is accomplished as follows: Let it be assumed that the input to the comparators is such that the "+" input is more positive than the "-” input. This is transferred to the latch as a logical “1”, so transistor 652 is “on” and transistor 654 is “off”, and the current in the collector of transistor 652 acts to reduce the potential at the comparator "+” input, thus forming a negative feedback connection.
  • the sampling clock signal 620 may be thought of as having a period including a positive edge and a negative edge. While the rate of the sampling clock signal is determined by the positive going edge in each period, the effective switching rate of the DACs is determined by the positive and negative edges in a period, since the positive edge enables transistor 653 while the negative edge enables transistor 655.
  • a clock signal having a rate of f s /2 provides an effective switching rate of f s in the configuration of Fig. 6.
  • the configuration of Fig. 6 may readily be extended to four comparators each operating at a rate of f s /4, and four DAC transistor pairs respectively connected between the outputs of the comparators and a capacitor in a cascade configuration.
  • Fig. 7 shows the corresponding extension of the circuit portion which switches the reference current for the DAC transistor pairs so that only one of the comparator outputs is fed back to the summing capacitor.
  • Fig. 7 comprises clock signal sources 700, 750, 760, transistors 710, 720, 730, 740, 770, 780, and current source 790.
  • the collectors of transistors 710, 720, 730, 740 are respectively connected to the common emitters of the transistors in the transistor pairs forming the four DACs.
  • Clock signal 760 has a frequency of f s /4.
  • transistor 770 is enabled and so current from current source 790 flows to the common emitters of transistors 710, 720.
  • Clock signal 700 has a frequency of f s /2.
  • transistor 710 is enabled so that a first comparator output is fed back through DAC1.
  • transistor 720 is enabled so that a second comparator output is fed back through DAC2.
  • transistor 780 is enabled and so current form current source 790 flows to the common emitters of transistors 730, 740.
  • Clock signal 750 also has a frequency of f s /2.
  • transistor 730 is enabled so that a third comparator output is fed back through DAC3
  • transistor 740 is enabled so that a fourth comparator output is fed back through DAC4.
  • the clock signal 760 may have a frequency of f s /4 and a phase of 0°
  • the clock signal 700 may have a frequency of f s /4 and a phase of 270°
  • the clock signal 750 may have a frequency of f s /4 and a phase of 90°, as shown in Figs. 8A-8c.
  • a maximum clock signal rate of only f s /4 is required.
  • a maximum clock signal rate of only f s /N is required, where n is the number of comparators and corresponding DAC transistor pairs.
  • delta sigma converters including the type discussed below according to the invention include digital sampling oscilloscopes, modular test and instrumentation systems, applications where portability or battery powered operation are important, and generally any situation where conversion of an analog signal to a digital signal is required.
  • Fig. 9 shows a digital sampling oscilloscope incorporating a delta sigma converter.
  • An input signal is supplied to terminal 800 which applies the input signal to signal conditioner 810 that functions to amplify, offset and otherwise suitably condition the input signal in a conventional manner, and to supply the conditioned signal to delta sigma converter 820 and to trigger processor 870.
  • Controller 880 is adapted to generate clock signals suitable for the timebase of the input and output signals, and to supply these clock signals to delta sigma converter 820 and demultiplexers 830A-D. Controller 880 also generates write and read control signals for memories included in the demultiplexers 830A-D.
  • Delta sigma converter 820 functions to convert the conditioned input signal into digital data pulse streams having a combined time average amplitude proportional to the amplitude of the input signal, and to supply the digital data to demultiplexers 830A-D.
  • Demultiplexers 830A-D respectively include a memory for storing the digital data supplied thereto in accordance with clock pulses and write control signals supplied thereto from controller 880.
  • the demultiplexers are needed only when the data rate from the converter is too fast for the memories to accommodate directly.
  • Trigger processor 870 is adapted to detect a trigger indication in the conditioned input signal, and to supply a halt signal to controller 880 upon detection of the trigger indication.
  • Controller 880 serves to respond to the halt signal from trigger processor 870 by generating a control signal to delta sigma converter 820 to halt signal conversion, and generating a read control signal to demultiplexers 830A-D to transfer their contents to processor 840.
  • the data when data is transferred from demultiplexers 830A-D to processor 840, the data may be pre- processed by, for example, filtering as described above, or by conditioning to a form suitable for display.
  • the filtering may be performed by processor 840 or by a dedicated digital signal processor.
  • Processor 840 is adapted to combine the signals read out from the memories in demultiplexers 830A-D, as filtered or conditioned, to form a display signal and to supply the display signal to display system 850 which stores and suitably formats the display signal for display on display 860.
  • each of the quantizing elements (e.g. 330, 340; 530, 540) rather than comprising a single comparator and latch may be replaced by multiple comparators 335, 345 with associated latches as shown in Fig. 13.
  • the reference inputs to these comparator arrays should be suitably matched in a known manner to the output range of the preceding integration filters (320; 520) .
  • like reference numerals refer to like components.
  • the feedback signals (350A, 350B; 580, 590) to the DAC elements (360; 550, 560) consist of the most significant bit (or equivalently the decision made by the central comparator) of the resulting comparator array. This signal is identical to that which was obtained from the structures containing single comparator quantizing elements and hence the action of the feedback loop is entirely unaffected by the change.
  • the outputs (370, 380; 580, 590) are now however multibit rather than single bit. These multibit words require a small amount of digital signal processing, before the normal decimation filters well known from conventional arrangements. The requisite additional processing can be performed in a number of different ways as will be clear to those skilled in the art .
  • the advantage of using such quantizing elements is that for N comparators in a quantizing element, the quantization noise is reduced by 20*N*log 10 (2) decibels. This reduction in quantization noise improves the signal to noise ratio of the complete converter by the same amount.
  • the converters are illustrated with first order loops, although extensions to higher orders will be evident and are discussed in detail in relation to the known arrangements above. That discussion can be applied in relation to the present invention by those skilled in the art.
  • the multibit quantizers described here may be used in time- interleaved architectures of any order.
  • ADC analog-to-digital converter
  • the analog-to-digital converter (ADC) discussed above in relation to known arrangements is typically of the "low-pass” type: that is, the circuit only responds to input signals containing frequencies below a certain "cut-off" frequency f c . Above this frequency, the amplitude response of the circuit is reduced and the digital representation of the input signal becomes inaccurate.
  • This kind of ADC has applications in systems where the signal of interest has been modulated onto a carrier, such as direct conversion digital radios.
  • a resonator 25 in place of the integrator shown in Fig. 1, as shown in schematic form in Fig. 10 in combination with other inventive aspects of the invention.
  • Fig. 10 shows a simple first order delta sigma converter having a bandpass response. More than one resonator 25 can be used in higher order delta sigma converters with advantages in terms of improvement in the system signal to noise ratio as described hereinabove.
  • the invention thus comprises a time-interleaved architecture for a delta sigma ADC having a bandpass characteristic.
  • a simple first order time-interleaved delta sigma ADC with one resonator 315 and two quantizers 330, 340 is shown in Fig. 11.
  • the resonator 25 is configured in a known manner to set a lower cut-off frequency f and an upper cut-off frequency f 2 , thereby defining the bandpass characteristic of the converter.
  • This structure gives a bandpass characteristic with all the advantages described above for a time-interleaved low pass ADC, namely, low complexity, lower operating frequency for the quantizers with improved signal to noise ratio, and low manufacturing cost.
  • a second order ADC with two quantizers and resonators 26, 27 is shown in Fig. 12.
  • the advantage of a second order structure over a first order structure is explained in the discussion above, but, principally, for a given ratio of sampling frequency F s to maximum signal frequency F o; the second order architecture produces better signal-to-noise ratio than a first order architecture.
  • a final converter architecture according to the invention comprises a combination of the arrangements described in relation to Figs. 10-13.
  • the quantizing elements 330, 340 are single comparators. As shown in Fig. 14, these can be replaced by the comparator arrays 335, 345 as described in relation to Fig. 13, with the same effect as that obtained for the low-pass time-interleaved sigma delta architectures : namely an improvement in overall signal-to-noise ratio equal to 20*N*log 10 (2) decibels.
  • time- interleaved bandpass converters of any order may be used.

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Abstract

Un convertisseur analogique-numérique convertit un signal d'entrée analogique (300) en au moins deux signaux de sortie numériques (370, 380) de la manière suivante. Un signal de rétroaction analogique est soustrait (310) du signal d'entrée analogique pour produire un signal différentiel. Ce dernier est ensuite intégré (320) pour produire un signal intégré qui est quantifié (330, 340) pour produire les signaux de sortie numériques en réponse aux signaux de commande respectifs qui ont chacun une fréquence prédéterminée et sont décalés en phase les uns par rapport aux autres. Les signaux de sortie numériques sont ensuite convertis en signal de rétroaction analogique. Le convertisseur analogique-numérique de cette invention utilise des constituants fonctionnant à une fréquence plus basse que la fréquence d'échantillonnage fs sans perte de gamme dynamique.
PCT/US1998/000311 1997-01-10 1998-01-09 Convertisseur analogique-numerique delta sigma WO1998031105A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU59097/98A AU5909798A (en) 1997-01-10 1998-01-09 Delta sigma analog-to-digital converter
EP98902427A EP1012983A4 (fr) 1997-01-10 1998-01-09 Convertisseur analogique-numerique delta sigma
US09/351,250 US6292121B1 (en) 1998-01-09 1999-07-07 Delta sigma-analog-to-digital converter

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Application Number Priority Date Filing Date Title
GB9700403.0 1997-01-10
GB9700403A GB2321143B (en) 1997-01-10 1997-01-10 Delta sigma analog-to-digital converter
PCT/IB1998/000011 WO1998031143A2 (fr) 1997-01-10 1998-01-07 Systeme eclairant pour un dispositif projecteur d'image

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US09/351,250 Continuation US6292121B1 (en) 1998-01-09 1999-07-07 Delta sigma-analog-to-digital converter

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WO1998031105A1 true WO1998031105A1 (fr) 1998-07-16

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US5208594A (en) * 1991-05-02 1993-05-04 Ricoh Company, Ltd. Signal processor that uses a delta-sigma modulation
US5329282A (en) * 1992-03-02 1994-07-12 Motorola, Inc. Multi-bit sigma-delta analog-to-digital converter with reduced sensitivity to DAC nonlinearities
US5363101A (en) * 1992-09-07 1994-11-08 Sony Corporation Analog to digital converter
US5621408A (en) * 1995-02-24 1997-04-15 Lecroy Corporation Delta sigma analog-to-digital converter with temporally interleaved architecture

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US4888587A (en) * 1987-06-29 1989-12-19 Nec Corporation Oversampling A/D converter with two capicitor arrays
US5030954A (en) * 1990-09-17 1991-07-09 General Electric Company Double rate oversampled interpolative modulators for analog-to-digital conversion
US5208594A (en) * 1991-05-02 1993-05-04 Ricoh Company, Ltd. Signal processor that uses a delta-sigma modulation
US5329282A (en) * 1992-03-02 1994-07-12 Motorola, Inc. Multi-bit sigma-delta analog-to-digital converter with reduced sensitivity to DAC nonlinearities
US5363101A (en) * 1992-09-07 1994-11-08 Sony Corporation Analog to digital converter
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GB2321143A (en) 1998-07-15
GB9700403D0 (en) 1997-02-26
GB2321143B (en) 2001-03-28

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