WO1998026507A1

WO1998026507A1 - Method and circuit for mitigation of array edge effects

Info

Publication number: WO1998026507A1
Application number: PCT/US1997/022475
Authority: WO
Inventors: Russell Croman
Original assignee: Cirrus Logic, Inc.
Priority date: 1996-12-09
Filing date: 1997-12-09
Publication date: 1998-06-18

Abstract

A method and circuit for minimizing the differences between members of an array of electrical circuits formed in an integrated circuit is provided. Edge effects seen at the edges of the array are minimized by providing dummy, redundant, or compensation electrical circuits at the edges of the array. These additional electrical circuits are similar to the electrical circuits within the inner portions of the array in both physical layout and electrical operation. In particular, the additional edge electrical structures are made to be electrically operative so that both the physical and electrical environment surrounding the inner array electrical structures is substantially homogeneous throughout the array. In one particular application, an array of comparator circuits for an analog to digital converter of a read channel circuit is provided with additional comparators at the edge of the array. The additional (or dummy) comparators are electrically operative; however, their outputs need not be utilized. The additional (or dummy) comparators improve mismatch characteristics between the utilized comparators in the inner portion of the array.

Description

METHOD AND CIRCUIT FOR MITIGATION OF ARRAY EDGE EFFECTS

BACKGROUND OF THE INVENTION

This invention relates to the mitigation of errors caused by edge effects in integrated circuits, and more particularly, to the mitigation of mismatches and nonuniformities between analog to digital converter electrical structures contained in an array of electrical structures which are intended to be identical in function.

In many integrated circuits an array of identical electrical structures is provided. Often it is desirable that the electrical characteristics of each of the structures be nearly identical across the entire array of electrical structures. For example, in certain mixed signal (analog-digital) s designs it is particularly desirable that the individual electrical structures within an array of electrical structures operate substantially similarly. For example, an analog circuit may often include an array of comparators or an array of capacitors. The array may be physically arranged in the integrated circuit in any number of generally rectangular layouts. It has been recognized that the electrical structures at the edge or outer portion of the array often display mismatches o and variations when compared to the operation of the electrical structures within the center of the array.

It has been theorized that such mismatches are the result of semiconductor manufacturing techniques which cause slight variations in the sizes and shapes of the electrical structures 5 formed in the integrated circuit. For example, it is known that photolithography printing and plasma etching during the semiconductor manufacturing processes may vary between areas on a die having highly dense circuitry and areas having less dense circuitry. Thus, the circuitry within the middle of a dense array of electrical structures may have slightly different structural characteristics than the circuitry that is formed along the edge of the array where the local o density of circuitry may be less. These fabrication differences then result in electrical performance differences. One method for compensating for such edge effects is to create dummy, sacrificial, redundant, or compensation structures at the edge of an array of electrical structures (as used herein dummy, sacrificial, redundant, or compensation may be used interchangeably). FIG. 1 illustrates one prior art method of compensating for such edge or effects by utilizing edge or outer dummy structures. FIG. 1 demonstrates the layout of an array 10 of a plurality of electrical circuits 12. As shown in FIG. 1, the illustrative size of the array is a 2 x N size array. It has been recognized that the electrical characteristics of the electrical structures 12B which are in the center or inner portion of the array 10 may vary from the electrical structures 12A at the edge or outer portion of the array. In order to accommodate for such variations and mismatches, dummy structures may be formed at the edges of the array. Thus, at the edges of the array 10, there may be formed dummy structures 14. Typically, the dummy structures 14 are formed in the integrated circuit and have similar circuit layers and patterning as the electrical structures 12; however, the dummy structures 14 are generally not electrically powered, clocked, or supplied with inputs. Typically the dummy structures 14 may be very similar to the circuit layers and s patterns of the electrical structure 12 so as to create an approximately same circuit density as in electrical structure 12, especially on certain process layers thought to be more critical to similar operation than others. Thus, the physical environment surrounding each electrical structure 12 is substantially similar, including the physical environment surrounding edge electrical structures 12A and inner electrical structures 12B. Therefore, a physical dummy structure has been formed o as a copy of the operative electrical structures and is placed relative to the electrically operative structures at the edges of the array for the purposes of providing a homogeneous semiconductor fabrication environment for the electrically operative structures with the end purpose of causing the electrical characteristics of the operative electrical structures to behave substantially similar to each other. 5

By placing dummy structures 14 at the edges of the array 10, the edge effects and electrical variations between electrical structures 12 of the array 10 may be lessened. However, it has been noted that in certain applications, the mere use of dummy structures 14 does not provide adequate matching of the electrical characteristics of the electrical structures 12. In o particular, it has been noted that in certain read channel circuits (utilized in magnetic disk storage systems) the systematic DNL levels may not adequately be minimized by the mere use of dummy structures 14. In magnetic disk storage systems for computers, such as hard disk drives, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written on a magnetic medium in concentric tracks. To read this recorded data, the read/write head passes over the magnetic medium and transduces the recorded magnetic transmissions into pulses and an analog signal that alternates in polarity. These pulses are then decoded by read channel circuitry to reproduce the digital data.

Decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interferences (ISI) and, therefore, are less susceptible to noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.

There are several well known discrete time sequence detection methods for use in a sampled amplitude read channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, partial response maximum likelihood (PRML) sequence detection, decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). No matter what type of discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on the disk.

One type of ADC which may be utilized to convert the high frequency data is a flash ADC. Such an ADC may contain multiple comparators for conversion of the analog data to digital data. In order to accurately convert the high frequency analog data, it is desirable that the comparators exhibit very little electrical variation from one comparator to the next. Because such comparators are often physically laid out within an integrated circuit die in an array format, these comparators are sensitive to the edge effects as discussed above. The use of dummy structures such as dummy structures 14 FIG. 1 have not resulted in adequate mitigation of systematic DNL effects within the ADC which may be caused by mismatched comparators. One example array of a set comparators for use in a read channel ADC as known in the prior art is shown in FIG. 2. Though seven comparators are shown in FIG. 2, it will be recognized that many more comparators may be utilized depending on the desired resolution. As shown in FIG. 2, the comparators 20 are electrically active and include various electrical inputs such as the clock signal 22, analog input signals 24, reference voltage inputs 23, and output signals 26. As shown in the figure, at both ends of the array of comparators there are provided dummy structures 28. The dummy structures 28 are provided so that the photolithographic and etching "environment" of the comparators 20 is substantially homogeneous. Thus, each operative comparator 20 has a substantially similar physical structure. However, the electrical characteristics of the comparators have still been found to display mismatches and nonuniformities from edge to inner comparators.

In an ADC, the threshold voltage of any given comparator is defined as the input analog signal voltage below which the comparator output signal is in the first of two states and above which the output is in the second of two states. The difference between the threshold voltages of any two adjacent comparators is generally desired to be equal to the differences of any other two adjacent comparators. If a converter achieves this perfectly, it would be said to have differential linearity. In practical designs, the difference between any two adjacent comparator threshold voltages is generally less than or greater than the optimum value, and is generally different from the difference between the threshold voltages of two other adjacent comparators. The greater the disparity between two said differences of threshold voltages, the greater is the so-called differential non-linearity (DNL). Typically, comparators located at the edge(s) of an array demonstrate a consistent tendency in the fabrication of a number of integrated circuit die to have a non-uniform difference of threshold voltages in a particular direction. Comparators not at or near the edge of the array generally tend to lack a consistency of movement of their threshold voltages, but rather tend to have a generally random displacement over multiple die. Thus, the edge comparators generally exhibit so-called systematic, as opposed to random DNL.

Thus, it would be desirable to decrease the edge effects which result in variations within an array of electrical structures and more particularly providing a more accurate array of comparators for use in a read channel ADC. SUMMARY OF THE INVENTION

A method and circuit for minimizing the differences between members of an array of electrical circuits formed in an integrated circuit is provided. Edge effects seen at the edges of the array are minimized by providing dummy, redundant, or compensation electrical circuits at the edges of the array. These additional electrical circuits are similar to the electrical circuits within the inner portions of the array in both physical layout and electrical operation. In particular, the additional edge electrical structures are made to be electrically operative so that both the physical and electrical environment surrounding the inner-array electrical structures are substantially homogeneous throughout the array. In one particular application, an array of comparator circuits for an analog to digital converter of a read channel circuit is provided with additional comparators at the edge of the array. The additional (or dummy) comparators are electrically operative; however, their outputs need not be utilized. The additional (or dummy) comparators improve mismatch characteristics between the utilized comparators in the inner portion of the array.

In one embodiment, the invention includes an electrical circuit having an array of electrical structures. The circuit may include a plurality of inner electrical structures located within the array where the inner structures have outputs utilized by the electrical circuit. Further, the circuit may include a plurality of edge or outer electrical structures within the array where the edge electrical structures may be located between at least one peripheral edge of the array and the inner electrical structures. The edge electrical structures may have outputs utilized by the electrical circuit. The electrical circuit may further include at least one dummy electrical structure proximate the peripheral edge of the array wherein the dummy electrical structure is electrically coupled to the electrical circuit so as to be electrically operative. The dummy electrical structures may provide an improved uniformity of the electrical characteristics across the array of the electrical structures. The dummy electrical structure may be both physically and electrically substantially similar to the electrical structures of the array.

In another embodiment of the present invention, an electrical circuit is provided which includes an array of electrical structures, the array being composed of both inner electrical structures and outer electrical structures. The circuit may include a plurality of the inner electrical structures which are not adjacent to at least two of the peripheral edges of the array. A plurality of the outer electrical structures is provided and these outer electrical structures may be located between at least one edge of the array and the inner electrical structures. Both the inner and outer electrical structures may be utilized for operation of the electrical circuit. The electrical circuit further includes a plurality of additional electrical structures which have substantially similar physical and electrical characteristics as the outer electrical structures. The additional electrical structures may be adjacent to at least one of the outer electrical structures and the additional electrical structures are electrically connected to the electrical circuit so that the additional electrical structures are electrically operable, however the outputs of the additional electrical structures are not utilized by the electrical circuit. The circuit may be an analog to digital converter circuit and the array of electrical structures may be an array of comparators. The additional electrical structures reduce mismatch between the comparators of the array.

In yet another embodiment of the present invention, an analog to digital converter having a plurality of comparators is provided. The plurality of comparators are formed in an array of comparators and include a plurality of inner comparators and a plurality of outer comparators. The analog to digital converter further includes a plurality of dummy comparators proximate to at least some of the outer comparators and the dummy comparators are electrically operable. The dummy comparators may be both physically and electrically similar to the inner and outer comparators. In a preferred embodiment, the output of at least one of the dummy comparators is not utilized by the analog to digital converter. Electrical operation of the dummy comparators reduces mismatch between the inner and outer comparators. The array of comparators may be partitioned into multiple sub-arrays, each of the sub-arrays utilizing dummy comparators.

The present invention also includes a method for operating an analog to digital converter including the steps of providing an array of comparators which includes both inner and outer comparators, forming at least one dummy comparator proximate to at least one of the outer comparators and electrically operating the dummy comparator. A more uniform electrical operation of the array of comparators may be obtained by performing the electrical operating step. The method may further provide a substantially uniform physical and electrical environment surrounding each of the comparators of the array.

Another method of the invention includes providing uniform electrical characteristics for a plurality of electrical structures. This method may include arranging the electrical structures in an array and providing at least one additional structure located along at least one edge of the array, the additional structure being physically similar to the electrical structures. Further, a substantially similar electrical environment is provided adjacent to the electrical structures located at inner portions and outer portions of the array by electrically operating the additional structure. The additional structures may be located along at least two peripheral edges of the array. Further, a plurality of the additional structures may be provided and some of the additional structures may be electrically inoperable.

In yet another embodiment of the present invention, a method for forming an electrical circuit is provided. The method may include providing an array of electrical structures in which the array has both inner portions and edge portions, the electrical structures being located in both the inner and edge portions. Further, the method includes forming a plurality of dummy electrical structures proximate at least one part of the edge portion of the array and electrically connecting the dummy electrical structures so that the dummy electrical structures may be electrically operated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art array of electrical structures utilizing physical dummies at the edges of the array.

FIG. 2 illustrates a prior art array of comparators using physical dummy structures at the edge of the array of comparators.

FIG. 3 is a block diagram of a read channel circuit which utilizes an analog to digital converter.

FIG. 4 is an example of a flash analog to digital converter circuit.

FIG. 4 A is a block diagram of an example comparator for use in the ADC of FIG. 4.

FIG. 4B is a circuit diagram of a comparator for use in the ADC of FIG. 4. FIG. 5 is an array of comparator circuits for use in an analog to digital converter including electrically operative dummy comparators at the edges of the array.

FIG. 6 illustrates one row of the array of FIG. 5.

FIG. 6 A illustrates an embodiment of the array of FIG. 5 in which the array is split into two sub-arrays.

FIGS. 7 A, 7B, 7C, and 7D illustrate the use of the present invention with a variety of sizes of arrays of electrical structures.

FIG. 8 illustrates the use of the present invention with a mixture of physical/electrical dummies and physical only dummies.

FIG. 8 A illustrates one embodiment of the present invention for use with an array of comparators.

FIG. 9 illustrates the use of the present invention in a flash analog to digital converter circuit.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 3 is a block diagram of a typical prior art read channel circuit 30. An analog to digital converter (ADC) 32 may be utilized within the read channel circuit 30. Any number of types of ADC circuits may be used for ADC 32. In one embodiment, the ADC 32 may be a 6- bit flash ADC. An ADC example of this embodiment is shown in FIG. 4. The ADC 32 of the embodiment of FIG. 4 may include an analog input 410 and a reference voltage input 400. The reference voltage is then divided into separate voltages through a series of resistors 420 which form a resistor voltage divider. Output taps are then provided from the resistor voltage divider to provide reference voltage inputs 425 to a series of comparators 430. In one embodiment, sixty-four separate voltages may be provided through sixty-four resistors 420 (each voltage varying by 1/64 of the reference voltage from the adjacent resistor) to sixty-three comparators 430. The analog input which is to be converted to a digital value is provided through input 410 to each of the comparators 430. The outputs of the comparators 430 are then provided to digital logic 490. By observing the outputs of the comparators 430, the digital logic 490 determines which two reference voltages the analog input lies between and provides a 6-bit digital representation of that voltage. This 6-bit output may then be provided at output 160 through a clocked D flip-flop 450. Though not shown, each comparator 430 may also receive clock, power, ground, etc. inputs. A block diagram of an example of a comparator circuit for use as comparator 430 is shown in FIG. 4A. As shown in FIG. 4A the comparator 430 may be a differential comparator. FIG. 4B is a circuit level diagram of the comparator 430. It will be recognized, though, that the present invention may be utilized with other comparator circuits, and more generally, with many other electrical structures.

In the example ADC discussed above, typically sixty-three comparators 430 may be utilized. The physical layout and arrangement of these comparators within the integrated circuit may be performed in a number of manners. In one embodiment the comparators may be arranged in two rows though other array sizes may be utilized. FIG. 5 illustrates a layout of the comparators 430. At each end of the array of comparators 430, dummy, sacrificial, compensation or redundant comparators 440 are provided. Unlike the dummy structures of the prior art, the dummy comparators 440 according to the present invention are electrically active and operable. Though the compensation or dummy comparators 440 are electrically operable and in fact do operate, their outputs will generally not be utilized and their electrical operation is typically performed for the purpose of compensating for array edge effects so that the entire array of comparators 430 (both center/inner comparators and edge/outer comparators) have more homogeneous electrical characteristics.

FIG. 6 illustrates one row of the array 500 of FIG. 5. FIG. 6 illustrates that electrical inputs such as the clock signals 600, analog input signals 602, reference voltages 604, and power inputs (not shown) are provided to both the comparators 430 and the dummy comparators 440. Furthermore, both the dummy comparators 440 and the utilized comparators 430 may have outputs 450. Thus, all of the comparators 430 and 440 are electrically operative and in fact do process electrical signals. However, the outputs 450 of the dummy comparators 440 are not needed or used in subsequent circuitry.

Because the dummy comparators 440 at the edges of the array of the comparators are electrically operative, improved mitigation of electrical mismatch and variation between the inner/center and outer/edge comparators 430 may be obtained. In particular, ADC systematic DNL may be mitigated more than is mitigated through the use of dummy structures which are not electrically operative. By providing electrically operative dummy structures at the array edges, both the physical environment and electrical environment seen by the utilized comparators 430 are more homogeneous across the entire array. In particular, the comparators 430 see a homogeneous physical environment as each comparator 430 has on its left and right sides substantially the same circuitry. Moreover, the electrical environments seen on either side of each comparator 430 is also substantially similar since the dummy comparators 440 are also electrically operative and process electrical signals.

As shown in FIG. 5, the array 500 of utilized comparators 430 is one continuous array. However, it is often desirable to form an array of electrical structures by use of a plurality of sub-arrays. For example, as shown in FIG. 6A, the array 500 of comparators 430 may actually be formed from two sub-arrays 505 and 510 of the comparators 430. In this case, it may be desirable to place electrically operative dummy comparators 440 on both ends of the sub-arrays 505 and 510 as shown in FIG. 6 A. It may be particularly important to obtain the benefits of utilizing electrically operative dummy electrical structures when sub-arrays are present because the partitioning of a larger array into a multiple sub-arrays increases the number of electrical structures at the edge of the array and thus increases the mismatch. Furthermore, in a case such as shown in FIG. 6 A if the comparators are sequentially arranged across both sub-arrays, then the break between the sub-arrays will occur at a point in the middle of the string of ADC decoding codes, a point at which it is even less desirable to have mismatching. Thus, as seen in FIG. 6A the present invention may be utilized by considering each sub-array an array of its own and providing electrically operative dummy structures at the edges of each of the sub-arrays. As used herein, therefore, any use of the term array may also include a sub-array as any given array of electrical structures may be merely a portion of some larger partitioned array.

The use of electrically operative dummy, sacrificial, redundant or compensation structures at the edge of an array may improve the uniformity of the electrical characteristics of the inner electrical structures of the array for a number of reasons. For example, the electromagnetic coupling to any given inner electrical structure from any other electrical structure in the array may now be more substantially similar from one inner electrical structure to another. Likewise, the capacitive coupling from one electrical structure to its surrounding electrical circuitry may also be more uniform for the electrical structures which have outputs which are actually utilized in the circuit. Numerous other specific electrical characteristics of the electrical structures within the array may also be improved, for example, substrate currents, leakage currents, etc. Thus, a dummy, redundant, or compensation structure may be placed adjacent to the array of utilized electrical structures and the dummy structures operated electrically in a similar manner for the purpose of homogenizing the electrical environment of the utilized electrical structures for the end purpose of mitigating electrical mismatches between the utilized electrical structures.

A wide variety of sizes and types of arrays may benefit from the present invention in addition to that discussed above. For example, FIGS. 7A, 7B, 7C, and 7D illustrate just some of the possible implementations of the present invention. As shown within the FIGS. 7A, 7B, 7C, and 7D, arrays of utilized electrical structures 700 are provided. Surrounding each array of utilized electrical structures 700 are dummy, redundant, or compensation electrical structures 705 which are provided so as to provide a more homogeneous electrical behavior of the electrical structures 700. For example, as seen in FIG. 7A, a square n x n array of electrical structures 700 is surrounded on all sides by dummy structures 705 which are electrically active so as to provide both a physical and electrical homogeneous environment around the array of utilized structures 700. Likewise, FIG. 7B shows an example of a n x m rectangular array of electrical structures 700 which are similarly surrounded by electrically operative dummy structures 705. The specific embodiment of a 7 x 3 array is shown in FIG. 7C. Finally, FIG. 7D illustrates that the array of utilized electrical structures 700 need not be symmetric in shape. As shown in FIG. 7D, a non-symmetric array of utilized electrical structures 700 is provided. Surrounding each electrical structure 700 is a single electrically operative dummy structure 705. In addition, even more dummy structures 705a may be utilized so that the total array of structures 700, 705, and 705a takes on a symmetric layout. Such additional use of structure 705a, however, may not be necessary .

As shown in FIGS. 7A, 7B, 7C, and 7D, dummy, redundant, or compensation structures 705 which are electrically operative surround all sides of the array of utilized electrical structure 700. It will be recognized, however, that the benefits of the present invention may be obtained even if the additional structures 705 are not provided on all sides of the array of electrical structures 700. For example, the additional structures 705 may be provided only on one side of an array and some improvement in mismatching will be obtained. Furthermore, the additional structures 705 may be provided on two sides of the array, such as for example, as shown in FIGS. 5 and 6. Alternatively, the additional structures 705 may be utilized on all sides of an array such as shown in FIGS. 7 A, 7B, 7C, and 7D. Furthermore, a single additional electrical structure 705 need not be all that is placed around the edge of an array. Two, three, or more additional structures 705 may be located at each edge of the array so as to provide more improved performance. For example, as shown in FIGS. 5 and 6 two dummy comparators 440 are provided at the edges of the utilized comparators 430.

As discussed above, the present invention has been described with reference to additional structures placed around the array of utilized electrical structures and all of the additional structures have been electrically operative. However, FIG. 8 illustrates an alternative embodiment where the additional structures may include a mix of physical only and electrical/physical dummy structures. As shown in FIG. 8, a two row slice of an array 800 of utilized electrical structures 805 is provided. As shown in FIG. 8, additional structures 810 and 815 are provided at the edges of the array. The additional structures 810 and 815 may both be dummy structures. However, in one embodiment, additional structure 810 may be both a physical and electrical dummy (i.e., the structure 810 is also electrically operative although its output may not be utilized) and additional structure 815 may only be a physical dummy (i.e., not electrically operative). Further, though only one dummy structure 810 and dummy structure 815 are shown, one, two, three, or more dummies 810 and 815 may be provided. Thus, the present invention may be utilized in a circuit in which both physical-only additional structures are provided and physical/electrically operative additional structures are provided. Though preferably the inner most additional structure such as structure 810 would be both a physical and electrical dummy structure, at least some of the benefits of the present invention may be obtained if the inner additional structure 810 is only a physical dummy while the outer additional structure 815 was both a physical and electrical dummy. In an alternate embodiment, the output of a dummy structure may be utilized, however, the output may not be relied upon for accuracy or used in subsequent computations.

Yet another embodiment of the present invention may be similar to that shown in FIG. 8. In this embodiment the additional structure 810 may be both a physical and electrical dummy, however, the additional structure 815 may be only a portion of a physical dummy. Thus, the cell size of an additional structure 810 would be similar to the cell size of the utilized structure 805 and the additional structure 810 would also be electrically operative, however, the outer most additional structure 815 may instead be just some portion of a cell (and thus would not be electrically operative) such as half of the physical structure it is to resemble. Thus, the placement of additional dummies around the array of utilized structures 805 need not be limited to complete additional structures, but rather, VA, VA , 2^lA, 2^λA, etc. portions of additional structures may be placed around the edge of the array. In such a case, it would be recognized that at least one of the whole additional structures placed around the array would be electrically operative and the partial additional structure would generally not be fully electrically operative and in fact may not be electrically operated at all but may merely be a portion of a physical only dummy structure. Thus, it can be seen that the present invention may be utilized in a wide range of manners with a mixture of both physical only and physical/electrical dummies to be arranged around one or more edges of any number of types of arrays of utilized electrical structures. Furthermore, the utilized electrical structures may be any number of electrical circuits, for example including but not limited to, comparator circuits, capacitors, RAM memory cells, ROM memory cells, current source circuits, etc.

FIG. 8 A illustrates one possible layout utilizing the techniques of the present invention. In particular FIG. 8A provides an array layout for the comparator array described above with reference to FIGS. 5, 6, and 6A. As shown in FIG. 8 A, the array 500 is partitioned into two sub- arrays 505 and 510. Each sub-array 505 and 510 includes a plurality of comparators 430 which have outputs 450 utilized by the ADC for performing the data conversion. Thus, each sub-array of comparators 430 includes a plurality of inner comparators and outer comparators, the outer comparators and inner comparators being subject to semiconductor fabrication edge effects. A plurality of dummy comparators 440 are provided at the ends of each sub-array of comparators 430. In particular, electrically operative dummy comparators 440a are provided immediately adjacent the utilized comparators 430 (also indicated as "electrical dummies" in the figure) and multiple non-electrically operative dummies 440b (i.e., physical only dummies) are provided adjacent the electrically operative dummy comparators 440a. Additionally, in this embodiment, each electrically operative dummy 440a has an output 455, which outputs 455 in this particular embodiment are unused by any subsequent electrical circuit (now shown), such as would process utilized outputs 450 of comparators 430. In order to maximize the benefits of the present invention, the electrical connection of the electrically operative dummy structures would generally be similar to the electrical connections of the utilized electrical structures (except perhaps for the use of the output). To most fully replicate (within the electrical dummy structures) the electrical operation of the utilized electrical structures, some additional circuitry may be required to provide nearly identical inputs to the electrical dummy structures. For example, with reference to the use of an array of comparators 430 such as shown in FIGS. 4, 5, and 6 an electrical input connection circuit such as shown in FIG. 9 may be required. As shown in FIG. 9, the utilized comparators 430 are flanked at the edge of the array by an electrically operative dummy comparator circuit 440. Analog inputs 410 are provided to each of the comparators 430 and 440 as are reference voltages 604 which are generated from the string of resistors 420. To more fully replicate the operation of the comparators 430, the voltage reference input to the dummy comparator 440 may be generated from an additional resistor 420a which is added to the string of resistors which are connected to the reference voltage 400. Though resistor 420a may not be necessary to provide sufficient mitigation of mismatches between the comparators 430, the use of resistor 420a may further improve the mitigation of mismatches and nonuniformities between the comparators by providing similar electrical operation of comparators 440 and comparators 430.

As used herein, an electrical structure may be electrically operative even if all portions of the structure do not fully operate. Thus, an electrically operative circuit may fully operate or partially operate, however, in either case such electrical operation according to the present invention provides more uniform electrical characteristics of the electrical structures in the array. For example, one may connect all of the various signals, such as the analog inputs, clock signals, etc., to the electrical dummy structures to make them operate as identically as possible to the utilized structures. On the other hand, for example, if one had prior knowledge that the mitigation of electrical edge effects depended upon the operation of only a portion of the electrical dummy structure, one may then choose to electrically operate only that specific portion, and have the remainder of the electrical dummy structure electrically inoperable. This particular embodiment of the invention would allow for only some and not all of the various signals, such as analog inputs, clock signals, etc., to be connected, although this particular application would not prohibit the connection of all of the signals to the electrical dummy structures. Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the shape, size, arrangement and types of components or devices. For example, equivalent elements or materials may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.

Claims

WHAT IS CLAIMED IS:

1. An analog to digital converter having a plurality of comparators, said analog to digital converter comprising

an array of said comparators, said array including a plurality of inner comparators and a plurality of outer comparators; and

a plurality of dummy comparators proximate at least some of said outer comparators, said dummy comparators being electrically operable.

2. The analog to digital converter of claim 1, wherein said dummy comparators are physically and electrically similar to said inner and outer comparators.

3. The analog to digital converter of claim 2, an output of at least one of said dummy comparators not being utilized by said analog to digital converter.

4. The analog to digital converter of claim 2, said dummy comparators reducing mismatch between said inner and outer comparators.

5. The analog to digital converter of claim 1 , said array being partitioned into at least two sub-arrays, each of said sub-arrays including inner comparators, outer comparators, and a plurality of said dummy comparators.

6. An electrical circuit including an array of electrical structures, said circuit comprising:

a plurality of inner electrical structures, within said array, said inner structures having outputs utilized by said electrical circuit;

a plurality of edge electrical structures, within said array, said edge electrical structures located between at least one peripheral edge of said array and said inner electrical structures, said edge electrical structures having outputs utilized by said electrical circuit; and at least one dummy electrical structure proximate said peripheral edge of said array, said dummy electrical structure being electrically coupled to said electrical circuit so as to be electrically operative.

7. The electrical circuit of claim 6, said at least one dummy electrical structure improving the uniformity of electrical characteristics of said array of electrical structures.

8. The electrical circuit of claim 6, said at least one dummy electrical structure being physically and electrically substantially similar to said electrical structures.

9. The electrical circuit of claim 6, further comprising a plurality of said dummy electrical structures, said dummy electrical structures being located along at least two peripheral edges of said array.

10. An electrical circuit including an array of substantially similar electrical structures, said array comprising inner electrical structures and outer electrical structures, said circuit comprising:

a plurality of said inner electrical structures, said inner electrical structures not adjacent to at least two peripheral edges of said array;

a plurality of said outer electrical structures, said outer electrical structures located closer to at least one edge of said array than said inner electrical structures, both said inner and outer electrical structures being utilized for operation of said electrical circuit; and

a plurality of additional electrical structures, said additional electrical structures having substantially similar physical and electrical characteristics as said outer electrical structures, said additional electrical structures being adjacent to at least one of said outer electrical structures, said additional electrical structures being electrically connected to said electrical circuit so that said additional electrical structures are electrically operable, however outputs of said additional electrical structures not being utilized by said electrical circuit.

11. The electrical circuit of claim 10, said additional electrical structures being located along at least two edges of said array.

12. The electrical circuit of claim 11 , said electrical circuit being an analog to digital converter.

13. The electrical circuit of claim 12, said array of electrical structures being an array of comparators.

14. The electrical circuit of claim 14, said additional electrical structures reducing mismatch between said comparators of said array.

15. A method of operating an analog to digital converter, comprising:

providing an array of comparators, said array including a plurality of inner comparators and a plurality of outer comparators;

forming at least one dummy comparator proximate at least one of said outer comparators; and

electrically operating said dummy comparator.

16. The method of claim 15, further comprising:

obtaining a more uniform electrical operation of said array of comparators by performing said electrically operating step.

17. The method of claim 16, further comprising:

reducing the differential non-linearities of said array of comparators.

18. The method of claim 15, said forming and said electrically operating steps together providing a substantially uniform physical and electrically environment surrounding each of said comparators of said array.

19. A method of providing uniform electrical characteristics for a plurality of electrical structures, said method comprising:

arranging said electrical structures in an aπay;

providing at least one additional structure located along at least one edge of said array, said additional structure being physically similar to said electrical structures; and

providing a substantially similar electrically environment adjacent to electrical structures located at inner portions and outer portions of said array by electrically operating said additional structure.

20. The method of claim 19, further comprising:

providing a plurality of said additional structures, said additional structures located along at least two peripheral edges of said array.

21. The method of claim 19, further comprising:

providing a plurality of said additional structures, some of said additional structures being electrically operated and some of said additional structures being electrically inoperable.

22. The method of claim 19, said electrical structures being comparators, wherein said providing a substantially similar electrical environment step reduces differential non-linearities between said comparators.

23. A method of forming an electrical circuit, comprising providing an array of electrical structures, said array having inner portions and edge portions, said electrical structures being located in both said inner and edge portions;

forming a plurality of dummy electrical structures proximate at least a part of said edge portion of said array; and

electrically connecting said dummy electrical structures so that said dummy electrical structures may electrically operate.

24. The method of claim 23, wherein said dummy electrical structures are physically similar to said electrical structures.

25. The method of claim 24, wherein said dummy electrical structures reduce non- uniformities of the operating characteristics of said array of electrical structures.

26. The method of claim 23, said dummy electrical structures formed adjacent to at least two parts of said edge portion of said array.