WO1998020713A1 - Materiau de masquage de soudures de dimensions stables et procede d'application - Google Patents

Materiau de masquage de soudures de dimensions stables et procede d'application Download PDF

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Publication number
WO1998020713A1
WO1998020713A1 PCT/US1997/018971 US9718971W WO9820713A1 WO 1998020713 A1 WO1998020713 A1 WO 1998020713A1 US 9718971 W US9718971 W US 9718971W WO 9820713 A1 WO9820713 A1 WO 9820713A1
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WIPO (PCT)
Prior art keywords
solder mask
mask material
solder
particle size
film
Prior art date
Application number
PCT/US1997/018971
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English (en)
Inventor
William George Petefish
Original Assignee
W.L. Gore & Associates, Inc.
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Filing date
Publication date
Application filed by W.L. Gore & Associates, Inc. filed Critical W.L. Gore & Associates, Inc.
Priority to AU50839/98A priority Critical patent/AU5083998A/en
Publication of WO1998020713A1 publication Critical patent/WO1998020713A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/285—Permanent coating compositions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0116—Porous, e.g. foam
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0537—Transfer of pre-fabricated insulating pattern

Definitions

  • the present invention relates to integrated circuit packages or circuit boards which are solder masked.
  • a printed circuit board is a board on which a copper film is patterned as an electric circuit.
  • a soldering process wherein integrated circuit packages are soldered to printed circuit boards, is necessary.
  • solder mask material which is a protective layer having high thermal resistance.
  • the portions to be soldered are not covered with the solder mask.
  • a solder mask is generally formed by coating a negative type photosensitive solder resist on the surface of the circuit board followed by exposing the surface to light through a negative film and developing.
  • the coating process of the negative type photosensitive solder resist is classified into three types, i.e., a printing process, a dry film process and a liquid resist process.
  • Typical solder mask materials include photo definable epoxy/acrylate blends in either dry film or liquid forms. These materials have the following typical properties: (Glass Transition Temperature) Tg: ⁇ 125 degrees C (Coefficient of Thermal Expansion) CTE (below Tg): 50-150 ppm/°C CTE (above Tg) : 100-500 ppm/°C
  • solder masks When using typical solder mask materials, after curing and upon subsequent thermal processing, the materials can shrink significantly. Shrinkage can start to occur at temperatures as low as 100°C.
  • Prior art solder masks are unreinforced, i.e., they are single phase systems having no fillers or carriers. The dimensional stability of such materials is poor. When prior art solder masks are used in conjunction with thin low modulus organic laminate structures, the solder mask dimensional performance dominates the overall substrate performance.
  • a thin, low modulus, organic substrate is a material having: Thickness: ⁇ 2mm
  • the solder mask can shrink and, when it does, because it is attached to the substrate package, it can warp the package substrate. Shrinkages of up to 4000 ppm have been measured. The shrinkage makes the package unfit for assembly and also unreliable.
  • prior solder mask materials have high moisture absorption. This can lead to delamination failures during moisture based reliability tests.
  • the moisture sensitivity of prior art solder masks can make them the weakest link in the package substrate.
  • solder masks When signal lines are routed on the outer layers of a package substrate, the electrical characteristics of the solder mask becomes more important. Typical prior solder masks have relatively high dielectric constant (Er) values and high dielectric losses.
  • solder mask material having dielectric values which do not lead to high dielectric losses. It is yet a further purpose of the present invention to provide a solder mask material having dimensional stability and which is easily applied to a substrate.
  • Fig. 1 A shows a laminate of a dimensional stable sheet and a ePTFE matrix.
  • Fig. 1 B shows an ePTFE/dimensionally stable matrix laminate with holes (vias) through the ePTFE layer.
  • Fig. 1C shows an ePTFE/dimensionally stable matrix laminate with through vias.
  • Fig. 2A shows an assembly of a solder mask material and a circuit board prior to lamination.
  • Fig. 2B shows an assembly with a solder mask material laminated to a circuit board.
  • Fig. 2C shows a laminated assembly in which the dimensionally stable layer has been removed.
  • Fig. 3 illustrates a scanning electromicrograph of a preferred ePTFE substrate prior to imbibing according to the present invention.
  • the present invention relates to a solder masked semiconductor package or circuit board wherein the solder mask material comprises a porous non-woven material in which the voids of the porous non-woven material contain a mixture of at least one particulate filler and at least one thermoset or thermoplastic resin. Additionally, the invention relates to a method of forming a solder masked semiconductor package, or substrate useful in making a semiconductor package, comprising the steps of laminating a solder mask material to a substrate and forming a solder masked substrate, wherein the improvement comprises using a solder mask material which is a non-woven material containing a mixture of at least one particulate filler and at least one thermoset or thermoplastic adhesive resin.
  • the present invention relates to a solder masked substrate comprising an integrated circuit package or circuit board having laminated thereto a solder mask material which has been patterned for alignment onto the package or circuit board.
  • the solder mask material comprises a porous non-woven material in which the voids of the porous non-woven material contain a mixture of at least one particulate filler and at least one thermoset or thermoplastic adhesive resin.
  • the solder mask material comprises the porous non-woven material laminated to a dimensionally stable material such as, for example, a thin metal sheet.
  • a dimensionally stable material such as, for example, a thin metal sheet.
  • Aluminum is a preferred material.
  • the dimensionally stable material should be a material which is easily removed by chemical means, such as etching, without causing damage or contamination of the chip package or circuit board features.
  • the solder masked substrate of the present invention can be made by the steps of: a) patterning the solder mask material to form a patterned solder mask material; and b) aligning the patterned solder mask material onto the chip package or circuit board. It is evident to those skilled in the art that alignment is simply the procedure of placing the mask onto the substrate such that the areas to be soldered are accessible while other portions of the package or circuit board are covered and protected by the solder mask.
  • Patterning can be accomplished by various known procedures wherein portions of the material are selectively removed such that the remaining portions can form a protective area over the chip package or circuit board during soldering. Any one of laser, punch, plasma or mechanical drilling methods can be used to form the patterned solder mask material.
  • solder mask material is aligned onto the chip package or circuit board surface using known alignment techniques. Possible alignment techniques include optical alignment or tooling pins.
  • the aligned patterned solder mask and chip package or circuit board assembly are joined to one another by the use of heat and pressure. Lamination can be achieved at pressures of between about 1 to about 500 psi and at temperatures between about 190°C and 250°C, preferably the lamination is conducted at 300 psi and 230°C.
  • the solder mask material is a porous matrix which is a non-woven substrate that is imbibed with high quantities of filler and a thermoplastic or thermoset adhesive, as a result of the initial void volume of the substrate, heated to partially cure the adhesive and form a B- stage composite.
  • Substrates include fiuoropolymers, such as the porous expanded polytetrafluoroethylene material of U.S. Patent Nos. 3,953,566 and 4,482,516, each of which is incorporated herein by reference.
  • the mean flow pore size (MFPS) of the substrate should be between about 2 to 5 times, or above, that of the largest particulate, with a MFPS of greater than about 2.4 times being particularly preferred.
  • suitable composites can be prepared by selecting a ratio of the mean flow pore size to average particle size of greater than 1.4. Acceptable composites can also be prepared when the ratio of the minimum pore size to average particle size is at least above 0.8, or the ratio of the minimum pore size to the maximum particle size is at least above 0.4. These ratios can be determined by employing a Microtrak® Model FRA Particle Analyzer device.
  • Another mechanism for gauging relative pore and particle sizes may be calculated as the smallest pore size being not less than about 1.4 times the largest particle size.
  • Table 1 shows the effect of the relationship of the substrate mean flow pore size (MFPS) and particulate size.
  • MFPS mean flow pore size
  • a fine dispersion was prepared by mixing 281.6 g Ti0 2 (TI Pure R-900, Du Pont Company) into a 20% (w/w) solution of a flame retarded dicyanamide/2-methylimidazole catalyzed bisphenol-A based polyglycidyl ether (Nelco N-4002-5, Nelco Corp.) in MEK. The dispersion was constantly agitated so as to insure uniformity. A swatch of expanded PTFE was then dipped into the resin mixture. The web was dried at 165°C for 1 min. under tension to afford a flexible composite. The partially-cured adhesive composite thus produced comprised of 57 weight percent TiO 2 , 13 weight percent PTFE and 30 weight percent epoxy adhesive.
  • EXAMPLE 2 A fine dispersion was prepared by mixing 386 g SiO 2 (HW-11-89, Harbison Walker
  • This resulting dielectric thus produced comprised of 53 weight percent SiO 2 , 5 weight percent PTFE and 42 weight percent adhesive, displayed good adhesion to copper, dielectric constant (at 10 GHz) of 3.3 and dissipation factor (at 10 GHz) of 0.005.
  • a fine dispersion was prepared by mixing 483 g SiO 2 (HW-11-89) into a manganese- catalyzed solution of 274.7 g bismaleimide triazine resin (BT2060BJ, Mitsubishi Gas Chemical) and 485 g MEK. The dispersion was constantly agitated so as to insure uniformity. A swatch of 0.0002" thick expanded PTFE was then dipped into the resin mixture, removed, and then dried at 165°C for 1 min. under tension to afford a flexible composite. Several plies of this prepreg were laid up between copper foil and pressed at 250 psi in a vacuum-assisted hydraulic press at temperature of 225°C for 90 minutes then cooled under pressure. The resulting dielectric thus produced comprised of 57 weight percent SiO 2 , 4 weight percent
  • PTFE and 39 weight percent adhesive displayed good adhesion to copper, dielectric constant (at 10 GHz) of 3.2 and dissipation factor (at 10 GHz) of 0.005.
  • EXAMPLE 4 A fine dispersion was prepared by mixing 15.44 kg TiO 2 powder (Tl Pure R-900,
  • This dispersion was subjected to ultrasonic agitation through a Misonics continuous flow cell for about 20 minutes at a rate of about 1-3 gal. /minute.
  • the fine dispersion thus obtained was further diluted to an overall bath concentration of 11.9% solids (w/w).
  • the Frazier number relates to the air permeability of the material being assayed.
  • Air permeability is measured by clamping the web in a gasketed fixture which is provided in circular area of approximately 6 square inches for air flow measurement.
  • the upstream side was connected to a flow meter in line with a source of dry compressed air.
  • the downstream side of the sample fixture was open to the atmosphere. Testing is accomplished by applying a pressure of 0.5 inches of water to the upstream side of the sample and recording the flow rate of the air passing through the in-line flowmeter (a ball-float rotameter that was connected to a flow meter.
  • the Ball Burst Strength is a test that measures the relative strength of samples by determining the maximum at break.
  • the web is challenged with a 1 inch diameter ball while being clamped between two plates.
  • the Chatillon, Force Gauge Ball/Burst Test was used.
  • the media is placed taut in the measuring device and pressure affixed by raising the web into contact with the ball of the burst probe. Pressure at break is recorded.
  • the web described above was passed through a constantly agitated impregnation bath at a speed at or about 3 ft./min, so as to insure uniformity.
  • the impregnated web is immediately passed through a heated oven to remove all or nearly all the solvent, and is collected on a roll.
  • An ePTFE matrix containing an impregnated adhesive filler mixture, based on SiO 2 prepared from the vapor combustion of molten silicon is prepared as follows. Two precursor mixtures were initially prepared. One being in the form of a slurry containing a silane treated silica similar to that of Example 5 and the other an uncatalyzed blend of the resin and other components.
  • the silica slurry is a 50/50 blend of the SO-E2 silica of Example 5 in MEK, where the silica contains a coated of silane which is equal to 1% of the silica weight.
  • a five gallon container 17.5 pounds of MEK and 79 grams of silane were added and the two components mixed to ensure uniform dispersion of the silane in the MEK. Then, 17.5 pounds of the silica of Example 5 were added.
  • Two five gallon containers of the MEK-silica-silane mixture were added to a reaction vessel, and the contents, i.e., the slurry, was recirculated through an ultrasonic disperser for approximately one hour to break up any silica agglomerates that may be present. The sonication was completed and the contents of the reaction vessel were heated to approximately 80°C for approximately one hour, while the contents were continuously mixed. The reacted mixture was then transferred into a ten gallon container.
  • Mixture II
  • the desired resin blend product is an MEK based mixture containing an uncatalyzed resin blend (the adhesive) contains approximately 60% solids, where the solid portion is an exact mixture of 41.2% PT-30 cyanated phenolic resin, 39.5% RSL 1462 epoxy resin, 16.7% BC58 flame retardant, 1.5% Irganox 1010 stabilizer, and 1% bisphenol A co-catalyst, all percentages by weight.
  • the desired product is a mixture of the silica treated with a silane, the uncatalyzed resin blend, and MEK in which 68% by weight of the solids are silica, and the total solids are between 5% and 50% by weight of the mixture.
  • the exact solids concentration varies from run to run, and depends in part on the membrane to be impregnated.
  • the catalyst level is 10 ppm relative to the sum of the PT-30 and RSL1462.
  • mixtures I and II were determined to verify the accuracy of the precursors and compensate for any solvent flash that had occurred. Then mixture I was added to a ten gallon container to provide 12 pounds of solids, e.g., 515 solids content, 23.48 pounds of mixture I. Then mixture II was added to the container to provide 5.64 pounds of solids, e.g., 59.6% solids, 9.46 pounds of mixture II. the manganese catalyst solution (0.6% in mineral spirits), 3.45 grams, was added to the mixture of mixture I and mixture II and blended thoroughly to form a high solids content mixture. The bath mixture for impregnating an ePTFE matrix, 28% solids mixture, was prepared by adding sufficient MEK to the high solids content mixture to a total weight of 63 pounds.
  • a fine dispersion was prepared by mixing 26.8 grams Furnace Black (Special Schwarz 100, Degussa Corp., Ridgefield Park, New Jersey) and 79 grams of coupling agent (Dynaslan GLYMO CAS #2530-83-8; 3-glycidyloxypropyl-trimethoxysilane (Petrach Systems). The dispersion was subjected to ultrasonic agitation for 1 minute, then added to a stirring dispersion of 17.5 pounds SiO 2 (SO-E2) in 17.5 pounds MEK which had previously been ultrasonically agitated. The final dispersion was heated with constant overhead mixing for 1 hour at reflux, then allowed to cool to room temperature.
  • an adhesive varnish was prepared by adding the following: 3413 grams of a 57.5% (w/w) mixture of Primaset PT-30 in MEK, 2456 grams of a 76.8% (w/w/) mixture of RSL 1462 in MEK, 1495 grams of a 53.2% (w/w) solution of BC58 (Great Lakes, Inc.) in MEK, 200 grams of 23.9% (w/w) solution of bisphenol A (Aldrich Company) in MEK, 71.5 grams Irganox 1010, 3.21 grams of a 0.6% (w/w) solution of Mu HEX-CEM (OMG Ltd.) in mineral spirits, and 2.40 kg MEK.
  • An adhesive varnish was prepared by adding the following: 3413 grams of a 57.5% (w/w) solution of Primaset PT-30 (PMN P-88-1591)) in MEK, 2456 grams of a 76.8% (w/w) solution of RSL 1462 in MEK, 1495 grams of a 53.2% (w/w) solution of BC58 (Great Lakes, Inc.) in MEK, 200 grams of 23.9% (w/w) solution of bisphenol A (Aldrich Company) in MEK, 71.5 grams Irganox 1010, 3.21 grams of a 0.6% (w/w) solution of Mn HEX-CEM in mineral spirits, and 2.40 kg MEK.
  • porous expanded polyolefins such as ultra high molecular weight (UHMW) polyethylene, expanded polypropylene, polytetrafluoroethylene prepared by paste extrusion and incorporating sacrificial fillers, porous inorganic or organic foams, or microporous cellulose acetate, can also be used.
  • UHMW ultra high molecular weight
  • expanded polypropylene expanded polypropylene
  • polytetrafluoroethylene prepared by paste extrusion and incorporating sacrificial fillers porous inorganic or organic foams, or microporous cellulose acetate
  • the porous substrate solder mask material has an initial void volume of at least 30%, preferably at least 50%, and most preferably at least 70%, and facilitates the impregnation of thermoset or thermoplastic adhesive resin and particulate filler paste in the voids while providing a flexible reinforcement to prevent brittleness of the overall composite and settling of the particles.
  • the filler comprises a collection of particles when analyzed by a Microtrak® Model FRA Particle Analyzer device, which displays a maximum particle size, a minimum particle size and an average particle size by way of a histogram.
  • Suitable fillers to be incorporated into the adhesive include, but are not limited to, BaTiO 3 , SiO 2 , AI 2 O 3 , ZnO, ZrO 2 , TiO 2 , precipitated and sol-gel ceramics, such as silica, titania and alumina, non-conductive carbon (carbon black) and mixtures thereof.
  • Especially preferred fillers are SiO 2 , ZrO 2 , Ti0 2 alone or in combination with non-conductive carbon.
  • Most preferred fillers include filler made by the vapor metal combustion process taught in U.S.
  • Patent No. 4,705,762 such as, but not limited to silicon, titanium and aluminum to produce silica, titania, and alumina particles that are solid in nature, i.e., not a hollow sphere, with a uniform surface curvature and a high degree of sphericity.
  • the fillers may be treated by well-known techniques that render the filler hydrophobic by silylating agents and/or agents reactive to the adhesive matrix, such as by using coupling agents.
  • Suitable coupling agents include, siianes, titanates, zirconates, and aluminates.
  • Suitable silylating agents may include, but are not limited to, functional silyating agents, silazanes, silanols, siloxanes.
  • Suitable silazanes include, but are not limited to, hexamethyldisilazane (Huls H730) and hexamethylcyclotrisilazane, silylamides such as, bis(trimethylsilyl)acetamide (Huls B2500), silylureas such as trimethyisilylurea, and silylmidazoles such as trimethylsilyiimidazole.
  • Titanate coupling agents are exemplified by the tetra alkyl type, monoalkoxy type, coordinate type, chelate type, quaternary salt type, neoalkoxy type, cycloheteroatom type.
  • Preferred titanates include, tetra alkyl titanates, Tyzor® TOT ⁇ tetrakis(2-ethyl-hexyl) titanate,
  • Tyzor® TPT ⁇ tetraisopropyl titanate ⁇ , chelated titanates, Tyzor® GBA ⁇ titanium acetylacetylacetonate ⁇ , Tyzor® DC ⁇ titanium ethylacetacetonate ⁇ , Tyzor® CLA ⁇ proprietary to DuPont ⁇ , Monoalkoxy (Ken-React® KR TTS), Ken-React®, KR-55 tetra (2,2 diallyloxymethyl)butyl, di(ditridecyl)phosphito titanate, LICA® 38 neopentyl(diallyl)oxy, tri(dioctyl)pyro-phosphato titanate.
  • Suitable zirconates include, any of the zirconates detailed at page 22 in the Kenrich catalog, in particular KZ 55- tetra (2,2 diallyloxymethyl)butyl, di(ditridecyl)phosphito zirconate, NZ-01- neopentyl(diallyl)oxy, trineodecanoyl zirconate,
  • Kenrich® diisobutyl(oleyl)acetoacetylaluminate (KA 301), diisopropyl(oleyl)acetoacetyl aluminate (KA 322) and KA 489.
  • certain polymers such as, cross-linked vinylic polymers, e.g., divinylbenzene, divinyl pyridine or a sizing of any of the disclosed thermosetting matrix adhesives that are first applied at very high dilution (0.1 up to 1.0% solution in MEK) can be used.
  • certain organic peroxides such as, dicumylperoxide can be reacted with the fillers.
  • the adhesive itself may be a thermoset or thermoplastic and can include polyglycidyl ether, polycyanurate, polyisocyanate, bis-triazine resins, poly (bis-maleimide), norbornene- terminated polyimide, polynorbornene, acetylene-terminated polyimide, polybutadiene and functionalized copolymers thereof, cyclic olefinic polycyclobutene, polysiloxanes, poly sisqualoxane, functionalized polyphenylene ether, polyacrylate, novolak polymers and copolymers, fluoropolymers and copolymers, melamine polymers and copolymers, poly(bis phenycyclobutane), and blends or prepolymers thereof. It should be understood that the aforementioned adhesives may themselves be blended together or blended with other polymers or additives, so as to impact flame retardancy or enhance toughness. As used herein, mean flow pore size and minimum pore size were determined using the
  • Coulter® Porometer II (Coulter Electronics Ltd., Luton UK) which reports the value directly. Average particle size and largest particle size were determined using a Microtrak® light scattering particle size analyzer Model No. FRA (Microtrak® Division of Leeds & Northup, North Wales, PA, USA). The average particle size (APS) is defined as the value at which 50% of the particles are larger. The largest particle size (LPS) is defined as the largest detectable particle on a Microtrak® histogram. Alternatively, the largest particle size is defined at the minimum point when the Microtrak® Model FRA determines that 100% of the particulate have passed.
  • APS Average particle size
  • LPS largest particle size
  • the largest particle size is defined at the minimum point when the Microtrak® Model FRA determines that 100% of the particulate have passed.
  • the method for preparing the adhesive-filler dielectric solder mask material involves:(a) expanding a polytetrafluoroethylene sheet by stretching a lubricated extruded preform to a microstructure sufficient to allow small particles and adhesives to free flow into the void or pore volume; (b) forming a paste from a polymeric, e.g., thermoset or thermoplastic material and a filler; and (c) imbibing by dipping, coating, or pressure feeding, the adhesive-filler paste into the highly porous scaffold, such as expanded polytetrafluoroethylene.
  • particulate filler is mixed into a solvent or aqueous solution or molten adhesive to afford a finely dispersed mixture.
  • the filler in small particle form is ordinarily less than 40 microns in size, and preferably has an average particulate size of between 1 and 10 microns.
  • the mean pore size of the node-and-fibril structure of the polytetrafluoroethylene should be large enough to allow for adequate penetration of the particulate. If the substrate is to be expanded polytetrafluoroethylene, then structures similar to those taught in U.S. Patent No. 4,482,516 are desirable.
  • the mean flow pore size should be between about 2 to 5 times, or above, that of the largest particulate, with a MFPS of greater than about 2.4 times that of the filler being particularly preferred.
  • suitable composites can be prepared by selecting a ratio of the mean flow pore size to average particle size of greater than 1.4. Acceptable composites can also be prepared when the ratio of the minimum pore size to average particle size is at least above 0.8, or the ratio of the minimum pore size to the maximum particle size is at least above 0.4.
  • the expanded polytetrafluoroethylene acts as the binder, and consequently, the adhesive must only display good glue qualities.
  • the low modulus and intricate network of nodes and fibrils of the expanded polytetrafluoroethylene structure serves to toughen the overall composite similar to the inverted phase in a phase-separated polymer alloy. This allows for compositional ratios of components that would not ordinarily be practical because one classically relies on the adhesive as both a binder and as a glue.
  • Expanded polytetrafluoroethylene can be made very uniform and, once imbibed with adhesive resin, does not change its final thickness. Thus, overall thickness control is possible. Additionally, the thickness of expanded polytetrafluoroethylene can be accurately controlled and, as a result, the resulting scaffold adhesive material film can be made very thin or very thick. Very thin substrates have the added advantage of permitting good surface bonding and structural integrity while minimizing the profile of the laminate.
  • the solder mask material is a prepreg material formed from a porous non-woven material as described hereinabove and preferably formed from an expanded polytetrafluoroethylene (ePTFE) matrix containing a paste filler material in the B-stage which is tack bonded to a sheet of material that is dimensionally stable and which can be subsequently removed without removing or damaging other components of the material.
  • ePTFE expanded polytetrafluoroethylene
  • the tack bonding does not have to be conducted at elevated temperature, and temperatures that could modify the properties of the dielectric should be avoided. Similarly, the temperature should be below the cure temperature and flow temperature of the thermoset or thermoplastic adhesive resin within the voids of the ePTFE.
  • the dimensionally stable material can be a thin metal film, preferably an aluminum film.
  • the ePTFE matrix containing the thermoset or thermoplastic resin adhesive and filler mixture is placed onto the surface of a dimensionally stable sheet of, for example, aluminum and fed through a nip roller to form a layered or laminated substrate. Thereafter, the ePTFE matrix layer is patterned to form blind holes by a variety of techniques, including by laser processing, which is a preferred technique. Alternatively, laser through holes may be formed, i.e., holes extending through both the ePTFE layer and the aluminum layer. Through holes could also be made by mechanical drilling, or mechanical punching. Another method for forming blind holes is a photodefined process. The dimensions of the holes are design dependent and can be on the order of ⁇ 100 ⁇ m in diameter.
  • the laminate is aligned by tooling pins or optical alignment with an electronic component having conductive pads.
  • the optical techniques typically have an accuracy of less than or equal to 25 ⁇ m, whereas typical tooling techniques have an accuracy of greater than 25 ⁇ m.
  • the two components are aligned, they are brought together whereby they are intermeshed and the pads are received within the holes in the ePTFE composite solder mask material. Contact of the two components is made under pressure and elevated temperature.
  • the carrier layer e.g., aluminum is removed with a NaOH or KOH etch or to form a solder marked product.
  • Figures 1A, 1 B and 1C show the solder mask material of the present invention in its various possible embodiments.
  • the assembly 10 comprises a laminate of a dimensionally stable foil such as aluminum 11 and an ePTFE layer 12.
  • the ePTFE layer 12 is a preferred embodiment, as described above, and comprises a porous PTFE whose void volume is filled with a mixture of at least one particulate filler and at least one thermoset or thermoplastic resin adhesive.
  • the resin adhesive is a thermoset resin.
  • Fig. 1 B shows a solder mask assembly having an aluminum dimensionally stable layer 17 and an ePTFE layer 14 having vias 13 while Fig. 1C shows a solder mask assembly having an ePTFE layer 16 and a dimensionally stable layer 18 with through vias 15 extending through both the ePTFE layer 16 and the dimensionally stable layer 18.
  • Figures 2A, 2B and 2C show the fabrication of a solder masked circuit board or package.
  • Fig. 2A shows the assembly prior to lamination with the solder mask material 20 positioned in alignment with conductive pads 23 on the circuit board 22.
  • the solder mask material comprises a dimensionally stable layer 21 and an ePTFE layer 25 with vias 26 in the ePTFE layer 25.
  • Fig. 2B shows the laminated assembly of the solder mask material 20 and the circuit board or package 22, while Fig. 2C shows the laminated assembly of solder mask material 24 wherein the dimensionally stable layer 21 has been removed from the ePTFE layer 25.
  • a main advantage of the solder mask material of the present invention is that because the adhesive is within the matrix, there is no adhesive flow.
  • prior art “coveriay” systems also suffer from shortcomings which detract from their usefulness. More particularly, typically conventional “coveriay” systems are made from polyimide films which are dimensionally unstable. Additionally, adhesives employed with conventional "coveriay” systems flow during bonding, which thereby causes possible contamination of an integrated circuit package or circuit board. Since there is no flow, or substantially no flow, with the solder mask material of the present invention, tolerances, i.e., distance between conductive pads of electronic component, may be much smaller.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

La présente invention a trait à un boîtier de semi-conducteurs ou à une plaquette de circuit (24) imprimé à soudures masquées, dans lesquels le matériau de masquage (25) de soudures comprend un matériau poreux non tissé dont les pores contiennent un mélange constitué d'au moins une charge de matière particulaire et d'au moins une résine thermodurcie ou thermoplastique. De plus, cette invention a trait à un procédé de formage d'un boîtier de semi-conducteurs à soudures masquées, ou d'un substrat (24) utile dans la fabrication d'un boîtier de semi-conducteurs, comprenant les étapes consistant à laminer un matériau de masquage de soudures sur un substrat (24), et à former un substrat (24) à soudures masquées. L'amélioration que présente ce procédé comprend l'utilisation d'un matériau de masquage (25), lequel est un matériau non tissé contenant un mélange constitué d'au moins une charge de matière particulaire et d'au moins une résine adhésive thermodurcie ou thermoplastique.
PCT/US1997/018971 1996-11-08 1997-10-22 Materiau de masquage de soudures de dimensions stables et procede d'application WO1998020713A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU50839/98A AU5083998A (en) 1996-11-08 1997-10-22 Dimensionally stable solder mask material and method of application

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74597496A 1996-11-08 1996-11-08
US08/745,974 1996-11-08

Publications (1)

Publication Number Publication Date
WO1998020713A1 true WO1998020713A1 (fr) 1998-05-14

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AU (1) AU5083998A (fr)
WO (1) WO1998020713A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7381666B2 (en) 2002-12-20 2008-06-03 Kimberly-Clark Worldwide, Inc. Breathable film and fabric having liquid and viral barrier
WO2018149575A1 (fr) * 2017-02-15 2018-08-23 Endress+Hauser SE+Co. KG Carte de circuit imprimé à composants empilés et procédé de fabrication de celle-ci

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US2885601A (en) * 1954-05-28 1959-05-05 Rca Corp Insulation of printed circuits
US3433888A (en) * 1967-01-24 1969-03-18 Electro Mechanisms Inc Dimensionally stable flexible laminate and printed circuits made therefrom
US4155801A (en) * 1977-10-27 1979-05-22 Rohr Industries, Inc. Process for masking sheet metal for chemical milling
WO1986006925A1 (fr) * 1985-05-10 1986-11-20 Boorman, Paul, Anthony Carte de circuit imprime et agencements de transfert pour celle-ci
US4705762A (en) * 1984-02-09 1987-11-10 Toyota Jidosha Kabushiki Kaisha Process for producing ultra-fine ceramic particles
EP0248617A2 (fr) * 1986-06-02 1987-12-09 Japan Gore-Tex, Inc. Procédé de fabrication de substrats pour circuits imprimés
EP0346522A2 (fr) * 1988-06-16 1989-12-20 Nippon CMK Corp. Panneau à circuit imprimé
JPH06244537A (ja) * 1993-02-19 1994-09-02 Junkosha Co Ltd プリント配線板
EP0639042A1 (fr) * 1993-07-01 1995-02-15 Japan Gore-Tex, Inc. Plaque à circuit imprimé avec film de couverture
US5538756A (en) * 1994-09-23 1996-07-23 W. L. Gore & Associates High capacitance sheet adhesives and process for making the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2885601A (en) * 1954-05-28 1959-05-05 Rca Corp Insulation of printed circuits
US3433888A (en) * 1967-01-24 1969-03-18 Electro Mechanisms Inc Dimensionally stable flexible laminate and printed circuits made therefrom
US4155801A (en) * 1977-10-27 1979-05-22 Rohr Industries, Inc. Process for masking sheet metal for chemical milling
US4705762A (en) * 1984-02-09 1987-11-10 Toyota Jidosha Kabushiki Kaisha Process for producing ultra-fine ceramic particles
WO1986006925A1 (fr) * 1985-05-10 1986-11-20 Boorman, Paul, Anthony Carte de circuit imprime et agencements de transfert pour celle-ci
EP0248617A2 (fr) * 1986-06-02 1987-12-09 Japan Gore-Tex, Inc. Procédé de fabrication de substrats pour circuits imprimés
EP0346522A2 (fr) * 1988-06-16 1989-12-20 Nippon CMK Corp. Panneau à circuit imprimé
JPH06244537A (ja) * 1993-02-19 1994-09-02 Junkosha Co Ltd プリント配線板
EP0639042A1 (fr) * 1993-07-01 1995-02-15 Japan Gore-Tex, Inc. Plaque à circuit imprimé avec film de couverture
US5538756A (en) * 1994-09-23 1996-07-23 W. L. Gore & Associates High capacitance sheet adhesives and process for making the same

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7381666B2 (en) 2002-12-20 2008-06-03 Kimberly-Clark Worldwide, Inc. Breathable film and fabric having liquid and viral barrier
WO2018149575A1 (fr) * 2017-02-15 2018-08-23 Endress+Hauser SE+Co. KG Carte de circuit imprimé à composants empilés et procédé de fabrication de celle-ci

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