WO1998020614A1 - A method and an apparatus for comparing two logic signals - Google Patents

A method and an apparatus for comparing two logic signals Download PDF

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Publication number
WO1998020614A1
WO1998020614A1 PCT/DK1997/000505 DK9700505W WO9820614A1 WO 1998020614 A1 WO1998020614 A1 WO 1998020614A1 DK 9700505 W DK9700505 W DK 9700505W WO 9820614 A1 WO9820614 A1 WO 9820614A1
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Prior art keywords
signal
signals
deviation
difference
attenuation
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PCT/DK1997/000505
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French (fr)
Inventor
Christian Glerskov
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Dsc Communications A/S
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Priority to AU48634/97A priority Critical patent/AU4863497A/en
Publication of WO1998020614A1 publication Critical patent/WO1998020614A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present invention relates to a method and a circuit for comparing two logic signals with a view to generating a difference signal capable of assuming a high level with a positive sign, zero and a high level with a negative sign.
  • a function of this type is incorporated in many control systems, which include logic components in a feedback loop, particularly in electronic circuits in which an output signal is compared with a reference, and an analog deviation signal is to be generated on the basis of logic signals for the adjustment of an output signal until the deviation is zero.
  • binary logic components capable of switching between two predetermined levels are used, it is expedient in many cases to provide two branches in a circuit for measuring the deviation, one branch of which substantially expresses the deviation in one direction by setting a high state for a period of time expressing the magnitude of the deviation, and the other branch performs a corresponding processing in case of deviation in the opposite direction, the resulting deviation signal being formed by subtraction. If the average value of this signal is generated e.g. in an integrator or a low-pass filter, an analog signal characterizing the magnitude and the sign of the deviation can be obtained.
  • the invention moreover relates to a method and a circuit for generating a phase-locked oscillator signal.
  • Phase-locked electronic circuits comprising a local oscillator which generates a periodic oscillating signal to be kept in phase-locked relationship with an external periodic synchronization signal are known from the prior art. If a synchronization signal which is periodic with a cycle time greater than the cycle time of the oscillator signal is utilized, a local reference signal more directly comparable with the external reference signal is generated from the signal of the oscillator. Through comparison of these signals, a signal characterizing direction and magnitude of the deviation is generated electronically, which signal is fed back in a control loop to a control input on the oscillator, typically a voltage-controlled crystal oscillator.
  • Commercially available today are integrated electronic circuits capable of performing a comparison between two input signals, and making an error signal available on output terminals which precisely characterizes direction and magnitude of the temporal deviation, thereby providing a signal which can be used in the control loop.
  • a data sheet from Gigabit Logic on a component identified 16G044 discloses such a circuit having two input terminals to which the reference signal and the oscillator signal are applied, and having two output terminals on which the error signal is made available.
  • the two output terminals carry logic signals which each vary between logic zero and logic one, said deviation being expressed by the period of time during which the outputs are set high.
  • One output is used for signalling that the local oscillator is required to oscillate more rapidly, and the other output when it is required to oscillate more slowly.
  • the control signal for the voltage-controlled oscillator is obtained by forming a difference and then an average value on the basis of the output signals. Circuits of this type perform satisfactorily for many applications. However, their accuracy is limited, because the voltage levels are only maintained with a limited accuracy. The deviations or offset errors that may occur, may vary with time and temperature, and it is therefore difficult to exclude their influence.
  • the invention provides a method as defined in claim 1.
  • the non-linear signal processing based on the numerical value of the difference between the signals ensures attenuation of the difference signal in case of small differences, i.e. in practice differences caused by offset errors.
  • the relation between offset errors and the difference between the logic voltage levels is less critical, and this gives a greater freedom in the design of the apparatus.
  • the characteristic according to the invention may be implemented in a simple manner with purely pas-sive components, and it gives a suppression of errors caused by offset of more than one order of magnitude.
  • the invention moreover provides a method as defined in claim 4.
  • This method ensures suppression of phase errors in a phase-locked oscillator which is better than one order of magnitude. This may be implemented by a relatively simple modification of the phase-locked oscillator circuit according to the prior art.
  • the invention moreover provides a circuit as defined in claim 5.
  • This circuit may be used very expediently in control circuits incorporating logic components, and is capable of suppressing zero point errors in a simple manner.
  • the invention moreover provides a circuit as defined in claim 9.
  • the resulting phase-locked oscillator is unique in that it is capable of locking to the reference signal with a very great accuracy.
  • the figure illustrates a circuit receiving, on the input terminal INPUT, an external reference signal which is to synchronize a voltage-controlled oscillator VCXO providing a high-frequency signal which is available on the output terminal OUTPUT.
  • the output signal from VCXO is also fed to the frame generator FG, which divides the high-frequency signal into a periodic signal having a longer cycle time.
  • This signal is the internal reference signal which is directly comparable with the external reference signal on the terminal INPUT.
  • the two signals are fed to a phase and frequency detector PFD, the external reference signal on the terminal R and the internal one on the terminal V.
  • the circuit PFD may e.g. comprise a component such as the above-mentioned type 16G044 from Gigabit Logic. As mentioned, it has two output terminals carrying logic signals which each vary between logic zero and logic one, the deviation being expressed by the period of time during which the outputs are set high.
  • the output U is set high when the oscilla ⁇ tor is to increase its frequency
  • the output D is set high when the oscillator is to reduce its frequency.
  • the signals from U and D are fed to a special combination circuit which processes them in a manner which will be explained below, so that signals are obtained on the output terminals U' and D' . These signals are fed to the amplifier AMP which forms their difference. The difference signal is fed through the low-pass filter LPF which forms the temporal average value of the signal. The output signal from LPF controls the oscillator VCXO.
  • the special combination circuit essentially comprises a bridge coupling having four resistors, where the signals U and D are fed to diametrically opposite corners, and the signals U' and D' are tapped from the remaining corners .
  • the four resistors, Rl, R2, R3 and R are precision resistors of equal values.
  • a diode Dl is inserted in parallel with the resistor Rl, oriented so that the forward direction is from U to U' .
  • a diode D2 is inserted in parallel with the resistor R4, oriented with a forward direction from terminal D to D' .
  • the diodes are semiconductor components which are assumed to be practically closed to current in the reverse direction, while in the forward direction they carry current of an intensity which varies as an exponential function of the voltage across them. For simple practical calculations, the simplifying assumption is made that the diode is blocked in the forward direction up to the threshold voltage V ⁇ and completely open in case of voltages above the threshold voltage.
  • the threshold voltage is greater than the offset errors that may occur on the PFD circuit. It is moreover assumed that the difference between high and low levels on U and D, respectively, is somewhat greater than the threshold voltage V ⁇ .
  • U and D have essentially the same voltage, i.e. both at high level or both at low level, perhaps with an offset error which gives a small difference. Both diodes are completely blocked in this case.
  • the combination circuit divides the voltage so that U' exactly has the mean value of the voltages on U and D. The same voltage is present on D' .
  • the difference signal on the output of AMP is exactly zero, irrespective of possible offset voltages.
  • U is high and D is low.
  • D2 is biased in the reverse direction and therefore carries no current.
  • the resistors R3 and R4 form the centre between the voltages VH and V D which is fed to the terminal D' , i.e.
  • V,, + V V D . - ⁇ -.
  • Dl is conductive with the voltage drop V ⁇ .
  • U' has the voltage
  • D is high and U is low.
  • Dl is biased in the reverse direction, and U' has the voltage v réelle +v n
  • D2 is biased in the forward direction, and D' has the voltage
  • V D' V D - V ⁇ .
  • the difference signal available on the output of the differential amplifier is
  • the combination circuit reduces the difference signal which is available for the adjustment to a little less than one half, viz. first by a factor of 2 and then by deduction of the threshold voltage.
  • the reduced gain may easily be compensated by adapting the amplification and attenuation coefficients in the other components in the circuit in a routine manner.
  • the loss involved by the reduction in gain is compensated more than fully by the benefit involved by the suppression of offset errors.
  • the invention is not restricted for use in connection with control loops. It may be applied everywhere where a circuit function is controlled by the difference between two signals, and where this difference substantially assumes a numerically great value or assumes a numerically small zero value. The accuracy of the zero value will frequently be destroyed by offset phenomena in the circuit, which reduces the accuracy of the function of the circuit.
  • the invention ensures that the zero value is independent of the offset of the two signals, which is thus without importance for the circuit function.
  • SU and SD both have a low signal level at the zero value.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A digital circuit compares the phase of two input signals and emits two logic signals which each are capable of assuming two levels and of being combined to an analog output signal which characterizes the phase difference. To suppress offset errors, the circuit comprises means for attenuating the logic signals in such a manner that the attenuation is essentially a non-linear function of the numerical value of the difference between the two logic signals, adapted such that the attenuation is stronger for differences of smaller numerical values. This may be implemented in a passive network (KK) having two diodes (D1, D2) arranged symmetrically at a resistance bridge so as to act symmetrically to a positive difference and a negative difference, respectively. The invention comprises a corresponding method, and a method as well as a circuit for generating a phase-locked, oscillating signal.

Description

A METHOD AND AN APPARATUS FOR COMPARING TWO LOGIC SIGNALS
The present invention relates to a method and a circuit for comparing two logic signals with a view to generating a difference signal capable of assuming a high level with a positive sign, zero and a high level with a negative sign.
A function of this type is incorporated in many control systems, which include logic components in a feedback loop, particularly in electronic circuits in which an output signal is compared with a reference, and an analog deviation signal is to be generated on the basis of logic signals for the adjustment of an output signal until the deviation is zero. Where binary logic components capable of switching between two predetermined levels are used, it is expedient in many cases to provide two branches in a circuit for measuring the deviation, one branch of which substantially expresses the deviation in one direction by setting a high state for a period of time expressing the magnitude of the deviation, and the other branch performs a corresponding processing in case of deviation in the opposite direction, the resulting deviation signal being formed by subtraction. If the average value of this signal is generated e.g. in an integrator or a low-pass filter, an analog signal characterizing the magnitude and the sign of the deviation can be obtained.
The invention moreover relates to a method and a circuit for generating a phase-locked oscillator signal. Phase-locked electronic circuits comprising a local oscillator which generates a periodic oscillating signal to be kept in phase-locked relationship with an external periodic synchronization signal are known from the prior art. If a synchronization signal which is periodic with a cycle time greater than the cycle time of the oscillator signal is utilized, a local reference signal more directly comparable with the external reference signal is generated from the signal of the oscillator. Through comparison of these signals, a signal characterizing direction and magnitude of the deviation is generated electronically, which signal is fed back in a control loop to a control input on the oscillator, typically a voltage-controlled crystal oscillator. Commercially available today are integrated electronic circuits capable of performing a comparison between two input signals, and making an error signal available on output terminals which precisely characterizes direction and magnitude of the temporal deviation, thereby providing a signal which can be used in the control loop.
A data sheet from Gigabit Logic on a component identified 16G044 discloses such a circuit having two input terminals to which the reference signal and the oscillator signal are applied, and having two output terminals on which the error signal is made available. The two output terminals carry logic signals which each vary between logic zero and logic one, said deviation being expressed by the period of time during which the outputs are set high. One output is used for signalling that the local oscillator is required to oscillate more rapidly, and the other output when it is required to oscillate more slowly. The control signal for the voltage-controlled oscillator is obtained by forming a difference and then an average value on the basis of the output signals. Circuits of this type perform satisfactorily for many applications. However, their accuracy is limited, because the voltage levels are only maintained with a limited accuracy. The deviations or offset errors that may occur, may vary with time and temperature, and it is therefore difficult to exclude their influence.
As an offset error, if any, in the control loop is incorporated as a constant quantity, its influence is most noticeable with small net error signals. This corresponds to a situation in which the two signals to be kept coincident are very close to each other. The time interval during which a control signal is generated, will then be relatively short, while the control signal has a zero value during the longest part of the time interval. If, however, there is an offset on one phase detector output, this will, after subtraction and formation of the average value in the control circuit, effectively be interpreted as a phase error, and the control circuit will respond by trying to shift the phase until the error signal, i.e. the average value of the difference signal, has a zero value. The offset error hereby results in a phase synchronization error. This phase synchronization error is considerable where there is a great spacing between the generating control signal pulses.
The invention provides a method as defined in claim 1.
The non-linear signal processing based on the numerical value of the difference between the signals ensures attenuation of the difference signal in case of small differences, i.e. in practice differences caused by offset errors. As a result, the relation between offset errors and the difference between the logic voltage levels is less critical, and this gives a greater freedom in the design of the apparatus. The characteristic according to the invention may be implemented in a simple manner with purely pas-sive components, and it gives a suppression of errors caused by offset of more than one order of magnitude.
The invention moreover provides a method as defined in claim 4.
This method ensures suppression of phase errors in a phase-locked oscillator which is better than one order of magnitude. This may be implemented by a relatively simple modification of the phase-locked oscillator circuit according to the prior art.
The invention moreover provides a circuit as defined in claim 5.
This circuit may be used very expediently in control circuits incorporating logic components, and is capable of suppressing zero point errors in a simple manner.
The invention moreover provides a circuit as defined in claim 9.
The resulting phase-locked oscillator is unique in that it is capable of locking to the reference signal with a very great accuracy.
Further embodiments and advantages of the invention will appear more fully from the following description given with reference to the drawing, whose sole figure shows a block diagram of a phase-locked oscillator circuit according to the invention.
The figure is schematic and simplified for clarity, so that it only shows details which are essential to the understanding of the invention, while other details are left out.
The figure illustrates a circuit receiving, on the input terminal INPUT, an external reference signal which is to synchronize a voltage-controlled oscillator VCXO providing a high-frequency signal which is available on the output terminal OUTPUT. The output signal from VCXO is also fed to the frame generator FG, which divides the high-frequency signal into a periodic signal having a longer cycle time. This signal is the internal reference signal which is directly comparable with the external reference signal on the terminal INPUT.
The two signals are fed to a phase and frequency detector PFD, the external reference signal on the terminal R and the internal one on the terminal V. The circuit PFD may e.g. comprise a component such as the above-mentioned type 16G044 from Gigabit Logic. As mentioned, it has two output terminals carrying logic signals which each vary between logic zero and logic one, the deviation being expressed by the period of time during which the outputs are set high. The output U is set high when the oscilla¬ tor is to increase its frequency, and the output D is set high when the oscillator is to reduce its frequency.
The signals from U and D are fed to a special combination circuit which processes them in a manner which will be explained below, so that signals are obtained on the output terminals U' and D' . These signals are fed to the amplifier AMP which forms their difference. The difference signal is fed through the low-pass filter LPF which forms the temporal average value of the signal. The output signal from LPF controls the oscillator VCXO. As will be seen in the figure, the special combination circuit essentially comprises a bridge coupling having four resistors, where the signals U and D are fed to diametrically opposite corners, and the signals U' and D' are tapped from the remaining corners . The four resistors, Rl, R2, R3 and R , respectively, are precision resistors of equal values. A diode Dl is inserted in parallel with the resistor Rl, oriented so that the forward direction is from U to U' . A diode D2 is inserted in parallel with the resistor R4, oriented with a forward direction from terminal D to D' .
The diodes are semiconductor components which are assumed to be practically closed to current in the reverse direction, while in the forward direction they carry current of an intensity which varies as an exponential function of the voltage across them. For simple practical calculations, the simplifying assumption is made that the diode is blocked in the forward direction up to the threshold voltage Vτ and completely open in case of voltages above the threshold voltage.
It may be assumed in practice that the threshold voltage is greater than the offset errors that may occur on the PFD circuit. It is moreover assumed that the difference between high and low levels on U and D, respectively, is somewhat greater than the threshold voltage Vτ .
Three different states will be mentioned briefly to illustrate the function of the combination circuit:
State A
U and D have essentially the same voltage, i.e. both at high level or both at low level, perhaps with an offset error which gives a small difference. Both diodes are completely blocked in this case. The combination circuit divides the voltage so that U' exactly has the mean value of the voltages on U and D. The same voltage is present on D' . The difference signal on the output of AMP is exactly zero, irrespective of possible offset voltages.
State B
U is high and D is low. In this case, D2 is biased in the reverse direction and therefore carries no current. The resistors R3 and R4 form the centre between the voltages VH and VD which is fed to the terminal D' , i.e.
V,, + V VD. = -^^-.
Dl is conductive with the voltage drop Vτ. U' has the voltage
Figure imgf000009_0001
The difference between U' and D' then represents
Figure imgf000009_0002
This value is formed on the output of the differential amplifier AMP. It will be seen that compared to the prior art in which the signals from U and D are fed directly to a differential amplifier, the deviation signal, in the case described, is reduced to a little less than one half, viz. by a factor of 2 and by deduction of the threshold voltage.
State C
D is high and U is low. In this case, Dl is biased in the reverse direction, and U' has the voltage v„ +vn
V,,'
2
D2 is biased in the forward direction, and D' has the voltage
VD' = VD - Vτ. The difference signal available on the output of the differential amplifier is
Vu- - V,y = " D +VT
viz. similar to the one in state B, merely with an opposite sign of the contribution of the diode. As it was assumed that VD was greater than Vπ, the resulting signal is negative, and the contribution of the diode will reduce the numerical value of the signal.
It will be seen that the combination circuit reduces the difference signal which is available for the adjustment to a little less than one half, viz. first by a factor of 2 and then by deduction of the threshold voltage.
The reduced gain may easily be compensated by adapting the amplification and attenuation coefficients in the other components in the circuit in a routine manner. The loss involved by the reduction in gain, is compensated more than fully by the benefit involved by the suppression of offset errors.
The invention is not restricted for use in connection with control loops. It may be applied everywhere where a circuit function is controlled by the difference between two signals, and where this difference substantially assumes a numerically great value or assumes a numerically small zero value. The accuracy of the zero value will frequently be destroyed by offset phenomena in the circuit, which reduces the accuracy of the function of the circuit. The invention ensures that the zero value is independent of the offset of the two signals, which is thus without importance for the circuit function. In the example shown, SU and SD both have a low signal level at the zero value. In another application in which SU and SD both have a high signal value at the zero value, it is expedient to use the diodes, Dl and D2.

Claims

P a t e n t C l a i m s :
1. A method of comparing two logic signals, each of which being capable of assuming two levels with a view to generating a difference signal capable of assuming a high level with a positive sign, zero and a high level with a negative sign, respectively, c h a r a c t e r i z e d by subjecting the logic signals (SU, SD) to a combination processing which results in the emission of two logic output signals (SU', SD' ) which reflect the input signals (SU, SD) , but are discriminated in the form of a non¬ linear attenuation of the numerical value of the difference between the two logic input signals, adapted such that the attenuation is stronger for differences of smaller numerical values.
2. A method according to claim 1, c h a r a c t e r i z e d by implementing the attenuation in a network (KK) comprising two diodes (Dl, D2 ) for providing the non-linear attenuation, said diodes being arranged symmetrically to act respectively in response to the sign of the difference between the logic signals (Su, SD) .
3. A method according to claim 1, c h a r a c t e r i z e d by subjecting the difference signal to signal processing (LPF) which essentially forms a temporal average value of the difference signal.
4. A method of generating a periodic oscillating signal in phase-locked relationship with an external periodic oscillating signal, comprising
generating on the basis of the periodic oscillating signal (OUTPUT) a local reference signal (SV) which is periodic with a cycle time considerably longer than the cycle time of the oscillating signal,
generating first and second deviation signals (SU, SD) on the basis of a comparison of the local reference signal (SV) with the external synchronization signal (SR) , said first deviation signal switching from a low to a high state on reception of the first reference signal if this is received before the external synchronization signal, said first deviation signal (SU) switching back to the low state on reception of the external signal, said second deviation signal (SD) switching from a low to a high state on reception of the external synchronization signal if this is received before the local reference signal and switching back to the low state on reception of the local reference signal, in such a manner that a control signal (DS) is generated on the basis of the two deviation signals, said control signal being capable of switching essentially between three levels, zero, a high state with a positive sign and a high state with a negative sign, respectively,
forming the average value of the control signal (DS) to generate an analog signal whose numerical value is essentially proportional to the temporal deviation between the local reference signal and the external synchronization signal, and whose sign expresses the direction of the deviation, and
feeding back the analog signal in a loop to control the oscillation frequency of an oscillator (VCXO) which generates the periodic oscillating signal (OUTPUT) ,
c h a r a c t e r i z e d by subjecting the deviation signals to a discrimination which is essentially a non-linear attenuation of the numerical value of the difference between the two logic signals (SU, SD) , adapted such that the attenuation is stronger for differences of smaller numerical values.
5. A circuit (KK) for combining two logic signals (SU, SD) which each are capable of assuming two levels and for emitting two logic signals which reflect the input signals, c h a r a c t e r i z e d in that the circuit comprises means (Dl, D2) for attenuating the signals in such a manner that the attenuation is essentially a nonlinear function of the numerical value of the difference between the two logic signals, adapted such that the attenuation is stronger for differences of smaller numerical values .
6. A circuit according to claim 5, c h a r a c t e r i z e d in that it comprises a network having two diodes (Dl, D2) arranged symmetrically in the network so as to act symmetrically to a positive difference and a negative difference, respectively.
7. A circuit according to claim 5, c h a r a c t e r - i z e d in that it comprises means (AMP) for forming the difference (PS) between the two logic output signals (SU' , SD' ) .
8. A circuit according to claim 5, c h a r a c t e r - i z e d in that it comprises means (LPF) for forming a temporal average value of the difference signal (DS) .
9. A circuit for generating a periodic oscillating signal in phase-locked relationship with an external periodic synchronization signal, comprising a controllable oscillator (VCXO) to generate a periodic oscillating signal (OUTPUT),
means (FG) for generating a local reference signal (SV) on the basis of a periodic oscillating signal, said local reference signal being periodic with a cycle time considerably longer than the cycle time of the oscillating signal,
means for comparing the local reference signal (SV) with the external synchronization signal (SR) and for generating first (SU) and second (SD) deviation signals, said first deviation signal switching from a low to a high state on reception of the local reference signal if this is received before the external synchronization signal, said first deviation signal switching back to the low state on reception of the external signal, said second deviation signal switching from a low to a high state on reception of the external synchronization signal if this is received before the local reference signal and switching back to the low state on reception of the local reference signal,
means (KK) for combining the two deviation signals to a control signal (DS) capable of switching between three levels, zero, a high level with a positive sign and a high level with a negative sign, respectively,
means (LPF) for forming the average value of the control signal for generating an analog signal whose numerical value is essentially proportional to the temporal deviation between the local reference signal and the external synchronization signal, and whose sign expresses the direction of the deviation, means for feeding back the analog signal in a loop for controlling the oscillator (VCXO) ,
c h a r a c t e r i z e d in that
the means (KK) for combining the deviation signals (SV, SR) comprise means for attenuating the deviation signals in such a manner that the attenuation is essentially a non-linear function of the numerical value of the difference between the two logic deviation signals, adapted such that the attenuation is stronger for differences of smaller numerical values.
PCT/DK1997/000505 1996-11-06 1997-11-05 A method and an apparatus for comparing two logic signals WO1998020614A1 (en)

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WO2001008312A1 (en) * 1999-07-22 2001-02-01 Sun Microsystems, Inc. Compensation circuit for low phase offset for phase-locked loops

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DK124696A (en) 1998-05-07

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