WO1998007238A1 - Codeur ecc a entree parallele et methode associee de calcul du residu - Google Patents

Codeur ecc a entree parallele et methode associee de calcul du residu Download PDF

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Publication number
WO1998007238A1
WO1998007238A1 PCT/US1997/014235 US9714235W WO9807238A1 WO 1998007238 A1 WO1998007238 A1 WO 1998007238A1 US 9714235 W US9714235 W US 9714235W WO 9807238 A1 WO9807238 A1 WO 9807238A1
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WIPO (PCT)
Prior art keywords
encoder
circuit
symbols
sub
encoders
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Application number
PCT/US1997/014235
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English (en)
Inventor
Lih-Jyh Weng
Original Assignee
Quantum Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Quantum Corporation filed Critical Quantum Corporation
Priority to AU40646/97A priority Critical patent/AU4064697A/en
Publication of WO1998007238A1 publication Critical patent/WO1998007238A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • This invention relates generally to an encoder for encoding data in accordance with an error-correcting code. More particularly, it relates to an encoder and associated method for speeding up the encoding and remainder computation processes when employing cyclic codes for error detection and correction.
  • an encoder 10 for a cyclic code is typically designed so that the data symbols are fed to the encoder one symbol per clock cycle to simplify the encoder design.
  • ECC error-correcting code
  • Switch 17 should be at position 1 when the data symbols are serially fed to the encoder; after the last data symbol is fed, switch 17 is set to position 2 and the contents of the r registers are the r redundant symbols for the set of the data.
  • the data symbols can be fed serially to any of the GF adders because the storage device (or the register) is a delay element.
  • a delay will be introduced if the data symbols are fed to GF adders 13, except GF adder 13', as shown in Fig. 1.
  • Fig. 2 for example, a delay of one clock cycle will be introduced in encoder 20 to get the redundant symbols.
  • Encoder 20 is an example of a prior art serial encoder with unit cycle delay.
  • Switch 17 is in position 1 for all of the data symbols but one additional clock cycle after the last data symbol is fed in it is switched to position 2 for the redundant symbols in the registers to be outputted.
  • serial input constraint substantially limits the data throughput at the encoder input.
  • both the input encoding and remainder computation processes suffer from the same serial input limitation. For example, let the data symbols be c[N-l], c[N-2], ..., c[r] and let the encoder generate the redundant symbols c[r-l], c[r-2], ..., c[l ], c[0] for the given data symbols; then
  • c(x) c[N-l]*x (N - ,) + c[N-2]*x (N"2) + ... + c[r]*x r + c[r-l]*x (r -" + ... + c[3]*x 3 + c[2]*x 2 + c[l]*x + c[0]
  • c'[i] may or may not be equal to c[i] due to errors.
  • c'[i] c[i] implies that the retrieved symbol c'[i] is correct, whereas if c'[i] differs from c[i] then the retrieved symbol includes an error.
  • c'fN-1], c'[N-2], ..., c'[r] are fed to the encoder to generate c'*[r-l], c"[r-2], ..., c"[2], c"[l], c"[0].
  • the remainder for c'(x) is then given by:
  • the invention to be described enables ECC encoder designers to increase the data encoding speed by an arbitrary factor while limiting increases in circuit complexity to a rate much smaller rate than the rate of increased encoding speed.
  • the invention also provides commensurate speed increases in the remainder computation process.
  • An ECC encoder in accordance with the invention includes a plurality of inputs each coupled to a distinct sub-encoder to facilitate parallel data input to speed up data encoding and remainder computation.
  • a general object of the present invention is to provide an apparatus and method for speeding up the encoding and remainder computation processes when employing cyclic codes for error-correction and/or error-detection.
  • Fig. 1 is a high-level linear circuit diagram of a prior art serial one-data-symbol-per- clock-cycle ECC encoder.
  • Fig. 2 is a high-level linear circuit diagram of a prior art serial ECC encoder with unit cycle delay.
  • Fig. 3 is a high-level diagram of an ECC encoder capable of receiving rwo-data-symbols- per-clock-cycle input.
  • Fig. 4 is a timing diagram illustrating the operation of a pair of T k encoders requiring k units of time to process k or fewer parallel inut symbols.
  • Fig. 5 is a timing diagram illustrating the operation of dual parallel sub-encoders.
  • Fig. 6 is a timing diagram illustrating the operation of triple parallel sub-encoders.
  • Fig. 7 illustrates a sub-encoder circuit encoder, connected according to T 8 .
  • Figs. 8A-8B illustrate a notation for compactly representing a set of circuit elements in a circuit diagram.
  • Fig. 9 illustrates a sub-encoder circuit encoder 2 connected according to T 8 and T 6 .
  • Fig. 10 illustrates a sub-encoder circuit encoder-, connected according to T 8 and T 3 .
  • Fig. 1 1 is a timing diagram illustrating the operation of L+l parallel sub-encoders.
  • FIG. 1 An improved ECC encoder in accordance with a preferred embodiment of the invention may be more clearly understood when described in the context of and in contrast with the prior art serial encoders illustrated in Figs. 1 and 2.
  • the prior art encoders of both Fig. 1 and Fig. 2 can be characterized mathematically by the same companion matrix. That companion matrix is:
  • Eq. (2) or equivalently Eqs. (2a), describes both Fig. 1 and Fig. 2 without taking the input into consideration.
  • c[i] is the ith data symbol.
  • the order of data fed to the encoder is c[n-l], c[n-2], .. c[r+l], c[r] for a cyclic code of length n, and c[r-l], c[r-2], ..., c[2], c[l], c[0] are the redundant symbols taken for the registers after the last input symbol was fed in.
  • s ⁇ ] transpose of row vector (s ⁇ [0], s ⁇ [l], ..., s ⁇ [r-l])
  • s] transpose of row vector (s[0], s[l], ..., s[r-l]) and
  • T The rows and columns of T are numbered from 0 to r-1 as indicated in Eq. (1).
  • Column j of T indicates how s[j] is fed to different s'[i]:
  • s'[i] s[0]*t[i][0] + s[l]*t[i][l] + ... + s[r-l]*t[i][r-l]. Therefore, given the appropriate companion matrix, it is possible to specify a circuit for the encoder. To obtain a companion matrix which will take two input symbols in parallel, define the two input symbols to be fed as c[i] and c[i-l]. The column s'] can be obtained from s] by:
  • the data symbols c[i] and c[i-l] are fed in pairs to encoder 25. If there are an odd number of data symbols, a zero is assumed to be inserted as the first symbol prior to the data symbols; the zero and the data symbols thus form an even number of symbols. In the case that the initial values for shift registers 14 are not zeros, the same set of initial values can be assigned to the registers 14 as if the number of data symbols is even. In the case that the number of data symbols is odd, i.e. there is one zero symbol inserted prior to the actual data, the initial values assigned to encoder 25 will be different. Let the desired initial value for the single-input-data- symbol-per-cycle encoder of Fig.
  • T l denotes the inverse of T. Because the matrix T is of special form, it can be easily shown that T (' ° is given by:
  • the set of k, symbols is fed to encoder, and the set of k 2 symbols is fed to encoder k 2 . All the input symbols to both sub-encoders are fed in order to the GF adders at the output of s[r-l], s[r- 2], etc.
  • Both sub-encoders are connected according to T k for all the inputs except encoder 2 should switch to connection T for the last set of k 2 input symbols.
  • the redundant symbols are the GF sum of the the corresponding shift registers of both sub- encoders after the last set of k data symbols are fed.
  • the initial values can be set on the shift registers of encoder, and the initial values for encoder 2 are all set to zeros. If there are n zeros filled in for the data with n ⁇ k navig and let the desired initial values for the single- input-data-symbol-per-cycle-encoder be p], then the initial values for encoder, is
  • encoder can be considered as the first encoder followed by encoder,.
  • a timing diagram 30, as shown in Fig. 4, may help clarify some of the concepts discussed above.
  • T s time units
  • both encoder, and encoder 2 are connected according to T k . Therefore, encoder, needs k units of time to process k, symbols and encoder 2 also needs k units of time to process k 2 symbols.
  • encoder starts at k, units of time ahead of encoder 2 . as shown in Fig. 4.
  • the encoder is still connected according to T k ; however, the very last k 2 symbols for encoder 2 the encoder is connected according to T as shown in Fig. 4. Therefore, both encoders will produce, respectively, the redundant symbols RED, from encoder, and RED 2 from encoder 2 at the exactly the same time as shown in Fig. 4.
  • the final encoded redundant symbols are obtained from symbol by symbol exclusive-oring of RED, and RED 2 .
  • the time for an encoder T k to process k, input symbols or k 2 symbols is the same as T k 2 ) to process k 2 input symbols are exactly the same.
  • the value oft can be an arbitrary value; however, t can be made equal to or slightly less than the time for k input symbols to be fed to the encoders.
  • both encoder, and encoder 2 are starting at the same time. Therefore, a realistic timing diagram 40 for dual encoders is illustrated in Fig. 5. It is evident from the timing diagram 40 of Fig. 5 that it is possible to design an encoder which can take up to 2r parallel inputs with two sub-encoders encoder, and encoder 2 . If the initial condition is not zero, only one of the sub-encoders have non-zero initial condition set according to Eq. (15) or Eq. (16) and the initial condition for the other initial condition are set to all zero.
  • Timing diagram 50 (of the same type developed in Section i), illustrated in Fig. 6, may be used to represent the timing for case ii). Timing diagram 50 illustrates a realistic timing model for triple parallel sub-encoders.
  • Fig. 7 illustrates sub-encoder 55, designated encoder, connected according to T 8 (as an example).
  • GF multipliers 57-65 multiply their respective inputs by the indicated power of ⁇ in Fig.
  • GF multiplier 96 is an ⁇ p multiplier for all of the input data symbols except the last k symbols and GF multiplier 97 is an ⁇ q multiplier for the last k input data symbols.
  • s[2] s3[2] + s2[2] + sl [2]
  • s[l] s3[l] + s2[l] + sl [l]
  • s[0] s3[0] + s2[0] + sl [0].
  • the initial conditions for the sub-encoders they depends on the number of data symbols, which, in turn, determines the number of zero fills for the each of the encoders. Let us assume that the total number of data symbols is 100. Since 100 is not divisible by 8, we need to fill in 4 symbols. This means that encoder, will have both inputs being zero and encoder 2 will have two zeros at the very beginning. Therefore, the initial conditions for encoder, and encoder 3 are all zeros and the initial condition for encoder 2 is
  • the initial condition for encoder 2 be the transpose of ( ⁇ 127 , 102 , ⁇ 24 )
  • FIG. 1 1 illustrates a realistic timing diagram 150 for the case of L parallel sub-encoders.
  • the L sub-encoders can be designed from the timing diagram, in the manner previously set forth. In the illustrated example:
  • k i . k - (k, + k 2 + ... + k i ); . . . .
  • the instant invention provides an apparatus and method for speeding up the encoding process and the remainder computation by an arbitrary factor.
  • the time saved in the encoding process and the remainder computation can be used to perform other more complex decoding algorithms.
  • the present invention facilitates the design and fabrication of, for example, more reliable and higher performance disk drives.

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  • Physics & Mathematics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention a trait à un codeur ECC (25) pourvu de plusieurs codeurs auxiliaires (55, 100, 125) configurés de manière à ce que celui-ci accepte un nombre arbitraire de symboles d'entrée dans un seul cycle d'horloge. La configuration du codeur selon l'invention permet d'accélérer le processus de codage et de calcul du résidu par l'utilisation d'un facteur arbitraire, encore que cela se traduise par un renforcement de la complexité. Dans la mesure où l'amélioration du processus de codage est plus rapide que la cadence à laquelle la complexité augmente, la technique selon l'invention est à même d'améliorer de façon significative la vitesse globale d'exécution du système ECC puisque les opérations de codage et de calcul du résidu figurent parmi celles qui prennent le plus de temps dans ledit système ECC.
PCT/US1997/014235 1996-08-15 1997-08-13 Codeur ecc a entree parallele et methode associee de calcul du residu WO1998007238A1 (fr)

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AU40646/97A AU4064697A (en) 1996-08-15 1997-08-13 Parallel input ecc encoder and associated method of remainder computation

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US08/698,075 1996-08-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0913949A2 (fr) * 1997-10-29 1999-05-06 Nec Corporation Dispositif et méthode de réalisation d'un codage Reed-Solomon
EP1353446A2 (fr) * 2002-04-09 2003-10-15 Broadcom Corporation Système et méthode pour générer des codes cycliques pour le contrôle d'erreurs pour des communications digitales

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US5226043A (en) * 1990-12-27 1993-07-06 Raytheon Company Apparatus and method for data error detection and correction and address error detection in a memory system
US5377207A (en) * 1992-09-03 1994-12-27 The United States Of America As Represented By The United States National Aeronautics And Space Administration Mappings between codewords of two distinct (N,K) Reed-Solomon codes over GF (2J)
US5396239A (en) * 1989-07-17 1995-03-07 Digital Equipment Corporation Data and forward error control coding techniques for digital signals
US5416801A (en) * 1992-07-08 1995-05-16 U.S. Philips Corporation Digital signal transmission system based on partitioning of a coded modulation with concatenated codings
US5446745A (en) * 1992-10-05 1995-08-29 Mitsubishi Semiconductor America, Inc. Apparatus for correcting errors in optical disks

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396239A (en) * 1989-07-17 1995-03-07 Digital Equipment Corporation Data and forward error control coding techniques for digital signals
US5226043A (en) * 1990-12-27 1993-07-06 Raytheon Company Apparatus and method for data error detection and correction and address error detection in a memory system
US5416801A (en) * 1992-07-08 1995-05-16 U.S. Philips Corporation Digital signal transmission system based on partitioning of a coded modulation with concatenated codings
US5377207A (en) * 1992-09-03 1994-12-27 The United States Of America As Represented By The United States National Aeronautics And Space Administration Mappings between codewords of two distinct (N,K) Reed-Solomon codes over GF (2J)
US5446745A (en) * 1992-10-05 1995-08-29 Mitsubishi Semiconductor America, Inc. Apparatus for correcting errors in optical disks

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0913949A2 (fr) * 1997-10-29 1999-05-06 Nec Corporation Dispositif et méthode de réalisation d'un codage Reed-Solomon
EP0913949A3 (fr) * 1997-10-29 2004-10-06 Nec Corporation Dispositif et méthode de réalisation d'un codage Reed-Solomon
US6895545B2 (en) 2002-01-28 2005-05-17 Broadcom Corporation System and method for generating cyclic codes for error control in digital communications
US7539918B2 (en) 2002-01-28 2009-05-26 Broadcom Corporation System and method for generating cyclic codes for error control in digital communications
EP1353446A2 (fr) * 2002-04-09 2003-10-15 Broadcom Corporation Système et méthode pour générer des codes cycliques pour le contrôle d'erreurs pour des communications digitales
EP1353446A3 (fr) * 2002-04-09 2004-03-17 Broadcom Corporation Système et méthode pour générer des codes cycliques pour le contrôle d'erreurs pour des communications digitales

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