WO1998007189A1 - Structure d'isolement par tranchees de semi-conducteurs presentant une planeite de surface superieure amelioree - Google Patents

Structure d'isolement par tranchees de semi-conducteurs presentant une planeite de surface superieure amelioree Download PDF

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Publication number
WO1998007189A1
WO1998007189A1 PCT/US1997/009426 US9709426W WO9807189A1 WO 1998007189 A1 WO1998007189 A1 WO 1998007189A1 US 9709426 W US9709426 W US 9709426W WO 9807189 A1 WO9807189 A1 WO 9807189A1
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WIPO (PCT)
Prior art keywords
fill dielectric
recited
dielectric
fill
trench
Prior art date
Application number
PCT/US1997/009426
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English (en)
Inventor
Fred N. Hause
Charles E. May
Sabhash Gupta
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1998007189A1 publication Critical patent/WO1998007189A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Definitions

  • This invention relates to semiconductor fabrication and more particularly to an improved method of planarizing fill dielectric used in a shallow trench process.
  • the improved method entails removing fill dielectric above active regions while retaining fill dielectric above field regions prior to chemical-mechanical polish (CMP).
  • CMP applied to the selectively removed fill dielectric provides for a more globally planarized fill dielectric regardless of the underlying topography.
  • isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
  • a popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS process involves oxidizing field regions between devices.
  • field oxide The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas.
  • LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
  • LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS.
  • a growing field oxide extends entirely across the field region and laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area.
  • the pre-implanted channel-stop dopant oftentimes redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects.
  • the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink.
  • the trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e g , between 0.2 to 0 5 microns, ana then filling the shallow trench with a deposited dielectric (referred to henceforth as "fill dielectric " )
  • Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled After the trench is filled, it is then plana ⁇ zed to complete the isolation structure
  • the trench process eliminates bird ' s-beak and channel-stop dopant redistribution problems
  • the isolation structure is fully recessed, offering at least a potential for a planar surface
  • field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width
  • the upper surface of fill dielectric in large isolation areas are generally at lower elevationai levels than the upper surface fill dielectric in small isolation areas
  • the fill dielectric readilv deposits in small area trenches such that the elevation of the fill dielectric in a small area trench is greater than the elevation within a large area trench Accordingly, subsequent processing is needed to bring the small trench fill topography to the same elevationai level as the large trench area fill topography
  • a popular rework technique involves depositing a sacrificial layer across the fill dielectric topography and then removing the sacrificial layer at the same etch rate as the underlying dielectric Generally, the sacrificial laver is deposited as a low-viscosity liquid
  • sacrificial materials include photoresist, polyimide or spin-on glass (SOG)
  • SOG spin-on glass
  • I he sacrificial layers generally etch back in a plasma until the topmost regions of the fill dielectric are exposed The etch chemistry is then modified so that the sacrificial layer material and the underlying fill dielectric are etched at approximately the same rate The etch is continued until all of the sacrificial layer has been etched away, leaving a somewhat planar fill dielectric upper surface
  • the sacrificial etchback technique is generally valid only tor plana ⁇ zation of topographies having features spaced less than 10 ⁇ m (microns) apart
  • the step height will not be reduced, since the sacrificial layer thickness on top of such features will be the same as the thickness over the adjacent trench
  • CMP chemical-mechanical polishing
  • Topography 10 includes a substrate 12 which has been fashioned with a small area trench 14 and a large area trench 16 according to the trench isolation process. Trenches 14 and 16 define field areas between active regions, wherein active regions are defined as silicon mesas 18 which extend upward from an elevation equivalent to the trench base. Deposited across trenches 14/16 and silicon mesas 18 is a fill dielectric 20.
  • Fig. 2 illustrates a processing step subsequent to that shown in Fig. I Specifically, the upper surface of fill dielectric material 20 receives CMP
  • the polishing pad inherently flexes or conforms under pressure to the upper surface of dielectric 20, causing the polishing pad to attack and remove dielectric 20 upper surface in large area trench 16, albeit to a lesser degree than the removal of dielectric 20 in small area trench 14 If dielectric in large area trench 16 is not sufficiently thick to withstand the attack, the dielectric upper surface will be removed below the desired planar elevation. Thus, a slight recess of dielectric 20 upper surface occurs at the conclusion of CMP That recess is shown as reference numeral 22. If not properly protected with sufficient overlying material, mesa upper surfaces, corner or sidewalls may also show erosion due to CMP
  • a process must be formulated which can achieve complete global planarization of the fill dielectric surface above both large area trenches and small area trenches.
  • the desired process must also be one which can plana ⁇ ze fill dielectric regardless of the underlying silicon mesa area (i.e., achieve planarization in regions above mesas of either large of small area).
  • Global planarization is hereby defined as the degree by which planarization is achieved across an entire semiconductor wafer topography. That degree is quantifiable and is derived from a process which can planarize the fill dielectric upper surfaces across the entire wafer topography with relatively small elevationai disparity in the resulting fill dielectric upper surface.
  • Fabrication of high density integrated circuits require elevationai uniformity of the fill dielectric surface regardless of the elevationai disparity of underlying features. If some degree of global uniformity is not achieved, then step coverage and depth of focus problems may result. Further, uneven planarization may affect the electrical parameters within and below the fill area. For example, local thinning of the fill region may result in an inappropriate amount of dopant beneath the fill dielectric possibly resulting in field inversion. Thus, planarization is desired even if significant elevationai disparity occurs between raised mesas or recessed trenches.
  • Plana ⁇ ty is also needed if the underlying topological area entails large area trenches/mesas (e g , greater than 2 0 microns per side) or small area trenches/mesas (e g , less than 1 0 microns per side)
  • the desired process must be one which does not over etch the fill dielectric surface to an elevation lower than an adjacent mesa upper surface If overetching occurs, then the mesa upper surface, comer and a portion of the silicon mesa sidewall will be partially exposed Any exposure of the silicon mesa surface, corner or sidewall causes inappropriate fringing field effects and or parasitic sidewall conduction It is therefore important when choosing a planarization method, that the method not expose portions of the silicon mesa in the process
  • the problems outlined above are in large part solved by an improved shallow trench process of the present invention
  • the shallow trench process hereof demonstrates substantially global planarization of fill dielectric above relatively large and small trench regions as well as large and small silicon mesas
  • a silicon mesa upper surface corner and sidewall areas are protected during planarization of the fill dielectric while ensuring sufficient fill dielectric in regions above those critical areas
  • the improved shallow trench process hereof achieves substantially global planarization by using a masking step More specifically, fill dielectric in large and small area trenches are protected by a photoresist, leaving fill dielectric above active areas (silicon mesas) exposed Lxposure of fill material above the silicon mesas affords select removal of material only in elcvationallv raised regions Bv masking the recessed regions and exposing the raised regions target areas of fill dielectric are advantaeeousiv removed prior to chemical- mechanical polish (CMP)
  • CMP chemical- mechanical polish
  • the plana ⁇ zing (i e , generated) mask protects the trenches and more particularly the fill dielectric in those trenches Generation of the mask is therefore readily achieved as a reverse of the mask used in producing the shallow trench
  • the plana ⁇ zing mask can be formed above large trench areas thereby avoiding use of a plana ⁇ zing mask above small trenches
  • Etching the non-masked fill dielectric is performed using an isotropic etch
  • the isotropic etch is a dry (or plasma) isotropic etch The dry isotropic etch proves beneficial in removing a larger quantity of fill dielectric in elevationally raised areas
  • dry isotropic etch is chosen over a wet isotropic etch using, e g , HF, for several reasons
  • dry isotropic etch is less likely to jeopardize the photoresist/fill dielectric juncture
  • dry isotropic etch is less likely to attack the fill dielectric "seam at the midline above spaced silicon mesas
  • wet etch causes separation of the photoresist from the fill dielectric upper surface This phenomenon is generally referred to as photoresist "lifting" and is most prevalent at the etch sidewall just beneath the photoresist Lifting of photoresist provides a conduit of etch along the fill dielectric surface, resulting in topological disparities once the photoresist is stripped
  • etch along the fill dielectric surface can, in the extreme, progress toward the seam area If the etchant reaches the seam it can delete ⁇ ously etch at a faster rate along the seam and toward the underlying topography The faster etch
  • the present invention contemplates a method for forming a plana ⁇ zed fill dielectric upper topography
  • the method comprises removing portions of a semiconductor substrate to form a pair of isolation trenches within the semiconductor substrate A pair of isolation trenches are laterally spaced from each other by an active region A fill dielectric is then deposited within and between the pair of isolation trenches Thereafter, the fill dielectric is isotropically etched from a plasma source in areas above the active region A chemical-mechanical removal step is then applied to the fill dielectric remaining in the areas above the active region such that the fill dielectric upper surface is removed to an elevation level commensurate with the fill dielectric within the pair of isolation trenches
  • the present invention further contemplates a method for forming a field dielectric The method comprises providing a silicon substrate having an active region bounded by a pair of field regions A trench is formed within the field region, and a fill dielectric is deposited within the trench and upon the active region At least a portion of the fill dielectric above the active region is isotropically
  • portions of the semiconductor substrate are removed to form the isolation trench or trenches using a photolithography spin-expose-develop-etch sequence.
  • the trenches are preferably formed within the field regions to a depth between, e.g., 0.2 to 0.5 ⁇ m.
  • the fill dielectric is deposited within the trench to a thickness exceeding the depth of the trench.
  • Isotropic etching is defined as an etch step which can proceed in several directions at the same rate. Isotropic etching can thereby occur along three dimensions defined as being perpendicular and non-perpendicular to the fill dielectric upper surface. Thus, isotropic etching is one which can occur along a vertical and horizontal axes, and proceeds along vectors formed by these axes at substantially the same etch rate. According to one embodiment, isotropic etching can be designed to occur at a faster rate in a lateral direction than the rate in a direction perpendicular to the etch surface. Conversely, anisotropic etching is any etching that is not isotropic.
  • Anisotropic etching proceeds primarily in one direction, e.g., along a vertical axis and essentially does not proceed along a horizontal axis.
  • the etch rate of an anisotropic etch along, for example, a vertical axis is substantially greater than the etch rate along a horizontal axis.
  • Fig. 1 is a partial cross-sectional view of a semiconductor topography having fill dielectric deposited upon and between silicon mesas formed according to a conventional shallow trench process;
  • Fig. 2 is a process subsequent to that of Fig. 1 , wherein the upper topography of fill dielectric is removed to uneven planarization levels according to a conventional planarization process;
  • Fig. 3 is a partial cross-sectional view of a semiconductor topography with photoresist applied across a topography according to an exemplary embodiment of the present invention
  • Fig. 4 is a processing step subsequent to Fig. 3, wherein the photoresist is patterned and isolation trenches are formed into the semiconductor substrate leaving silicon mesas between the trenches;
  • Fig. 5 is a processing step subsequent to Fig. 4, wherein a fill dielectric is formed entirely across the isolation trenches and silicon mesas;
  • Fig. 6 is a processing step subsequent to Fig. 5, wherein the photoresist layer and underlying fill dielectric are selectively removed using a dry isotropic etch according to the present invention
  • Fig 7 is a processing step subsequent to Fig 6, wherein the fill dielectric topography is shown after the photoresist is removed
  • Fig 8 is a processing step subsequent to Fig 7, wherein a CMP is applied to the fill dielectric topography
  • Fig 9 is a processing step subsequent to Fig 5, wherein a photoresist layer and underlying fill dielectric are selectively removed using a dry anisotropic etch, and
  • Fig 10 is a processing step subsequent to Fig 9, wherein a CMP is applied to the fill dielectric topography resulting in less than preferred planarization of the fill dielectric upper surface
  • Topography 30 includes a substrate 32, upon which a protective layer 34 is formed Deposited across the entire protective layer is a photoresist layer 36
  • Substrate 32 is preferably made from a single crystal silicon
  • Protective layer 34 comprises any layer which protects the silicon surface from etch materials and/or oxidation
  • protective layer 34 includes a nitrogen species, such as silicon nitride, or silicon nitride deposited upon an oxide
  • Photoresist 36 includes any material which can selectively polymerize when exposed to ultraviolet light
  • Topography 30 can include any topography from which an integrated circuit such as metal oxide semiconductor (MOS) is fashioned
  • Fig 4 illustrates a processing step subsequent to Fig 3 Specifically, a pattern is printed upon photoresist 36, and select regions are exposed and developed
  • the polymerized regions of photoresist 36 are represented as reference numerals 38
  • Polymerized photoresist 38 protects the underlying material from etchant Some of the areas protected by photoresist 38 include active regions 40 Active regions 40 represent areas where transistors will be formed, and are generally designated in areas exclusive of field regions 46
  • Field regions are defined as regions of a semiconductor substrate which receive isolation trenches Field regions do not contain active devices All active devices (e g , transistors, etc ) are formed withm active regions 40, i e , withm silicon silicon mesas 44
  • the patterned photoresist allow etchant to remove between, e g , 0 2 to I 0 microns of substrate material 32
  • the removed reg'ons are designated as trenches 45 formed exclusively in field regions 46 What remains of substrate 32 after trenches 45 are formed is a
  • Seam 52 is the result of deposited fill dielectric 50 meeting near the midline between small area trenches 45a
  • seam 52 forms when fill dielectric 50 sidewalls meet as a result of a geometric tunction of the trench depth, trench width, fill thickness amount, and the fill conformality characteristic Careful attention must be paid to the location of seam 52 when performing subsequent etch operations
  • Fig 6 illustrates an isotropic etch according to a preferred embodiment of the present invention Isotropic etch is performed upon fill dielectric 50 in regions exposed to the etchant
  • a photoresist 54 is used Photoresist 54 is selectively removed to expose fill dielectric 50 onlv in regions directly above silicon mesas 44
  • the mask used in patterning photoresist 54 is of opposite poia ⁇ ty to the mask used in forming trenches 45
  • photoresist 54 can be of opposite polarity to photoresist 36, whereby the same photomask used in forming trench 45 can be used to form openings 56
  • the etch used in Fig 6 is an isotropic etch and, more specifically, an isotropic etch performed from a plasma source, often referred to as "glow discharge"
  • the etch process is carried forth preferably in a fluorocarbon-containing plasma, using an etch gas comprising, e g , nitrogen-trifluo ⁇ de (NF 3 )
  • etch gases such as SF 6 may also be used, for example If desired, oxygen or hydrogen may be added to the fluorocarbon material to change the etch rate or the selectivity to underlying films, such as silicon
  • the etch chamber used in producing a dry etch plasma, resulting in an isotropic etch is one which is purpose
  • dry isotropic etch can be carried out in a LAM Corporation model 4520 ⁇ downstream plasma etcher with a 13 56 MHz RF source (downstream plasma systems with RF sources dissimilar from 13 56 MHz are likely to perform as well)
  • the etchant gas is preferably NF 3 introduced at 100 to 900 seem, wherein NF, is mixed with He introduced at 100 to 500 seem
  • the wall of the isotropic chamber is maintained at a temperature between 30-60°C during the etch process
  • the paddle temperature (l e the temperature of the receptacle upon which the wafer resides) is maintained between 60-100°C
  • the etchant RF power is held approximately at 500 to 950 watts during times in which the process pressure was maintained between 1300 to 2100 mtorr Good etch uniformity (within 5% having a 3 delta variance) is achieved at an etch rate of approximately 4500 angstroms/minute as a result of the following parameters NF, flow of 500 seem.
  • Fig 7 illustrates the resulting upper surface 60a of fill dielectric 50 after removal of photoresist 54
  • the dry etch species prevents photoresist separation from the fill dielectric and over etch along seam 52
  • the integrity of upper surface 60a directly above seam 52 is thereby retained so as not to exacerbate its preexisting topological disparity
  • Fig 8 illustrates a processing step subsequent to Fig 7, wherein chemical-mechanical polish (CMP) is applied to upper surface 60 by selectively removing fill dielectric 50 in raised regions using a pre-conditioning etch step
  • CMP shown in Fig 8 is more effective in producing a more globally plana ⁇ zed fill dielectric surface
  • Flexure of a CMP pad from raised regions of upper surface 60a is minimized by breaking up the raised surface area with the isotropic etch hereof Removing as much of the raised surface is possible without attacking seam 52 is thereby a primary objective of the present invention
  • removal along spaced intervals so as to separate the raised surface into a plurality of smaller area surfaces proves beneficial in optimizing CMP
  • CMP is more attuned to removing small area, spaced surfaces rather than large area surfaces
  • CMP proves useful in removing intermittently raised surfaces (I e raised surface above density-spaced silicon mesas 44 and the raised surface above small area trenches 45a)
  • Fig 8 illustrates substantially global planarization achieved by CMP CMP is continued for a pre- determined time duration
  • time duration is deemed the end point etch determinant
  • protective layer 34 can be removed to leave the upper surface of silicon mesas 44 intact
  • CMP does not expose the upper surface, corner or sidewall, of any silicon mesa 44 Problems involved in exposing those regions is thereby eliminated by the present process
  • Fig 9 illustrates a non-preferred anisotropic etch used in lieu of the isotropic etch shown in Fig 6 More specifically, Fig 9 illustrates a step subsequent to Fig 5, whereby exposed regions 56 of fill dielectric 50 are removed using a dry anisotropic etch as opposed to a dry isotropic etch
  • the dry anisotropic etch results in leaving a greater portion of fill dielectric in raised regions Since anisotropic etch does not afford lateral spreading at an etch rate substantially equivalent to the vertical etch rate, fill dielectric 50 in regions above small area, closely spaced silicon mesas 44 remain The remaining fill dielectric in the raised regions make CMP more difficult
  • CMP applied after the processing step of Fig 9 results in less than complete global planarization
  • the added fill material between closely spaced silicon mesas causes undue flexure of the CMP pad
  • the pad flexes, or when CMP is terminated after a set time period sufficient amounts of fill dielectric remain above and between closely spaced silicon mesas 44 That fill dielectric cannot be removed using CMP since fill dielectric between sparsely spaced silicon mesas will be unduly removed
  • anisotropic etch is preferred over conventional planarization processes, which do not use a pre-existing etch prior to CMP
  • anisotropic etch is not as preferred as dry isotropic etch
  • dry isotropic etch is preferred over wet isotropic etch and the photoresist lifting and seem etch problems associated therewith

Abstract

L'invention concerne une technique d'isolement pour améliorer la planéité globale d'une surface supérieure d'un diélectrique de remplissage. Ce diélectrique de remplissage est utilisé dans un procédé par tranchées de faible profondeur. Selon ce procédé, ce diélectrique est déposé dans des tranchées de faible profondeur à l'aide de dispositifs actifs isolants formés en mésas de silicium. Pour rendre ce diélectrique plan, il est retiré sélectivement avant d'effectuer un polissage chimique-mécanique. Ce diélectrique est retiré des zones surélevées décrites comme les zones se situant sensiblement au-dessus des mésas de silicium. Un matériau formant masque est utilisé en regard de celui qui constitue les tranchées de faible profondeur. Le diélectrique de remplissage est retiré à l'aide d'un processus d'attaque chimique isotropique sec. Cela permet de retirer la plus grande partie possible de diélectrique de remplissage surélevé. Une fois ce diélectrique retiré de manière sélective, le polissage chimique-mécanique peut être réalisé sur la surface supérieure restante pour obtenir une surface sensiblement plane sur la totalité de la plaquette de semi-conducteurs.
PCT/US1997/009426 1996-08-13 1997-05-29 Structure d'isolement par tranchees de semi-conducteurs presentant une planeite de surface superieure amelioree WO1998007189A1 (fr)

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US69677596A 1996-08-13 1996-08-13
US08/696,775 1996-08-13

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2237037A1 (fr) 2005-12-12 2010-10-06 Gyros Patent Ab Dispositif microfluidique et son utilisation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0407047A2 (fr) * 1989-07-03 1991-01-09 Advanced Micro Devices, Inc. MÀ©thode pour la planarisation de topologies pour des circuits intégrés
EP0545263A2 (fr) * 1991-11-29 1993-06-09 Sony Corporation Procédé pour former une rainure d'isolation comportant une étape de plissage et procédé pour fabriquer un dispositif semi-conducteur
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
EP0718874A2 (fr) * 1994-12-22 1996-06-26 Siemens Aktiengesellschaft Procédé de planarisation globale utilisant une technique auto-alignée d'espaceurs ou de polissage et procédé de gravure isotrope

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0407047A2 (fr) * 1989-07-03 1991-01-09 Advanced Micro Devices, Inc. MÀ©thode pour la planarisation de topologies pour des circuits intégrés
EP0545263A2 (fr) * 1991-11-29 1993-06-09 Sony Corporation Procédé pour former une rainure d'isolation comportant une étape de plissage et procédé pour fabriquer un dispositif semi-conducteur
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
EP0718874A2 (fr) * 1994-12-22 1996-06-26 Siemens Aktiengesellschaft Procédé de planarisation globale utilisant une technique auto-alignée d'espaceurs ou de polissage et procédé de gravure isotrope

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2237037A1 (fr) 2005-12-12 2010-10-06 Gyros Patent Ab Dispositif microfluidique et son utilisation

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