WO1997045909A1

WO1997045909A1 - Photovoltaic to grid interconnection

Info

Publication number: WO1997045909A1
Application number: PCT/AU1997/000319
Authority: WO
Inventors: Limin Zhong; Muhammed Fazlur Rahman
Original assignee: Unisearch Ltd.
Priority date: 1996-05-24
Filing date: 1997-05-23
Publication date: 1997-12-04
Also published as: AUPO009496A0

Abstract

This invention describes a new interface between a photovoltaic (PV) array and a single-phase mains utility that eliminates the bulky input (50 or 60 Hz) transformer on the ac side. The interface employs a PWM boost converter/rectifier on the dc side followed by a PWM current-forced single-phase reversible rectifier for injecting the power from the PV array into the mains. The current waveform at the ac side remains sinusoidal and exactly out of phase at all times. The circuit also has the advantage of requiring fewer switching devices than the circuits described in the prior art. The controller for the boost rectifier includes a maximum power tracker (MPT) while the current-forced reversible rectifier autonomously feeds the maximum available PV energy into the mains. This invention describes a full dynamic model of the interconnection using which various control and power circuit parameters can be determined or optimized and the performance of the interconnection studied.

Description

Photovoltaic to Grid Interconnection

INTRODUCTION

Solar photovoltaic (PV) energy has been drawing increasing interest in recent years as an alternative but important source of energy for the future. This has led to the rush for the development of suitable interconnections for solar PV arrays to the utility grid so that PV energy can be pumped into the mains efficiently and effectively. The desirable attributes of such interconnections are yet to be specified by the utilities. However it is expected that the interconnection will pump the solar power in to the mains without injecting additional harmonics into the system. Also, in order to minimise the sizing of the component parts, the interconnection is expected to insure that the current fed in to the mains will be in phase opposition to the sinusoidal voltage of the mains supply. These two requirements should guarantee near unity power factor operation and also compliance to the new IEC555 standard. A current-forced circuit

is also desirable so that short-circuit protection is available at all times. Isolation between the solar array and the utility grid, though desirable also from the point of no dc injection from the array to the mains, may not be essential from isolation considerations where fixed installations are considered. The nominal voltage of PV arrays is expected be within the range of 78-135 volts dc. so that some means of voltage amplification by a transformer or otherwise would be necessary, especially for the 230 or 240 volts single-phase ac mains.

In recent years a number of circuits have been proposed for the PV-grid interconnection. Most of the circuits proposed to-date utilise either a four transistor full-bridge inverter [1-4] or a half- bridge inverter [5], followed by a mains frequency transformer to connect the inverter to the mains. The transformer, in addition to providing the isolation, raises the output voltage of the inverter to the level of the mains voltage Since this transformer operates at the mains frequenc> for sizeable power transfer, it is rather bulky and costlv Reference [6] has described a circuit which utilises one high frequency switch in a forward converter in order to reduce the size of the transformer, followed by a four-transistor full-bridge inverter connected directly to the mains

The component count for this circuit is high. Reference [7] has described a transformerless single-phase four-transistor connection but the circuit operates from a PV array voltage of 750 V which is rather high from economic and other considerations. This reference does not address how maximum power tracking is to be incorporated within the inverter controller

Even though an ac side input transformer provides for isolation of the PV array, there is no overriding reason for including it [7]. This paper describes the topology of a current-forced reversible rectifier circuit, originally proposed in ref 8. that connects a PV array at a low voltage, typically 100V dc, to a single-phase 240 V ac mains which avoids the ac side transformer A full dynamic model of the whole circuit and its controllers which includes a maximum power tracker has been developed This model can be used for designing the interconnection and for studying its performance for various conditions of operation as occur with solar cells and for various power and controller circuit system parameters. Important modelling results relating to the steady-state and dynamic performance of the interface is presented in subsequent sections. A set of experimental results are also included showing the important waveforms at various parts of the interconnection Finally, a full appraisal of the interconnection in terms of its performance, both steady-state and dynamic is presented

THE PROPOSED INTERCONNECTION AND ITS OPERATION

The structure of the proposed PV array-to-grid interconnection is shown figure 1 The step-up (boost i rectifier raises the voltage of the PV array, typicallv about 100 V to a voltage above 680 V which is the potential maintained at the dc-link by the current-forced reversible rectifier

(CFRR). This step-up rectifier (SR). which also forces a current into the dc-link. in fact also serves the function of the maximum power tracker (MPT), the output of which is the pwm duty cycle for the step-up rectifier. The control structure for the step-up rectifier/MPT is given in

figure 2. The array voltage v_J0 and current /_raare multiplied to produce a power variable. This

power is then used in a search algorithm to hunt for the maximum power point. The output of the MPT is the reference for the current to be drawn from the PV array. The error between this reference current and the actual array current is amplified and used to modulate the pulse width of the switching signal of the IGBT T₃ in order to boost the array voltage to a level higher than 680 V. The diode D, and the inductor L_aare essential parts of the step-up circuit.

Initially, before the step-up rectifier is brought into operation, the two series connected capacitors charge up. via diodes D, and D₂, each to the peak of the supply voltage. For a 240 V ac mains this is 340 volts (=V 2*240), so that the dc-link voltage becomes 680 volts.

The current-forced reversible rectifier (CFRR) consists of the two transistors T, and T₂ with their parallel diodes D, and D_:. the series connected centre-tap capacitors C and the inductor L_ς. The control circuit for this stage is depicted in figure 3. The dc-link voltage is compared with a reference (>680V) and the error is amplified and multiplied with a unit inverted sine reference derived from the mains to form the current reference, i_sr, for an inner current loop for the supply

source current i_s. When the dc-link voltage is maintained above 2-/2K. through this control

loop, where V_s is the rms value of the mains, this current reference i,_r tends to become an undistorted sinewave which is in phase opposition to the mains voltage. The current forced through the mains is then regulated by the inner current loop. The outer voltage loop tries to

SUBSTπTJTE SHEET (Rule 26) maintain the dc link voltage slightly above 680 V. the level required for current-forced operation for the 240 V_nns mains

For balanced capacitor values, the two capacitors should share the dc-link \ oltage equall> , leading to a symmetric current waveform ;_y without a dc bias In the absence of identical capacitor values, voltages in the two current loops are different and it may lead to distortions in the current waveform Furthermore, unequal shaπng of the dc-link voltage may lead to overvoltage across the capacitors. To prevent these a dc bias may be introduced into the current controller to compensate for such a difference in capacitor voltage shaπng, as indicated in figure 3 The error between the two capacitor voltages is used to produce a dc bias signal which is added to the current reference.

SYSTEM MODELLING

A model of the whole system depicted by figures 2 and 3 has been developed with a view to studying both the steady-state and dynamic responses of the proposed interconnection as indicated in figure 1 For this purpose, a simulation package called Simnon. has been used for the simulation of the discrete and continuous parts of the circuit. The discrete parts are the voltage and current controllers for the current-forced reversible rectifier and the maximum power tracker and the current controller for the step-up rectifier Discrete models were chosen for these functions since its was felt that the control and switching functions included in these would be best implemented in a digital signal processor. The solutions for currents ι_as and ι_s in the CFRR and the SR according to the states of the three switches which are determined in the discrete sections of the model, are obtained in the continuous time-domain A. Modelling of the reversible rectifier. CFRR

The power circuits has two stages, namely the current-forced reversible rectifier and the step-up rectifier. The purpose of the reversible rectifier is to maintain the dc link voltage to a set value above 680VDC and to keep the source current waveform in phase-opposition to the mains voltage. The later arrangement, in addition to allowing unity power factor operation, is desirable for the sizing of the dc link capacitors. The capacitor value is the smallest when the phase angle between the input voltage and current is 180°. The reversible rectifier is fully capable of transferring real power in either direction and its operation is adequately described in reference 8. In this paper, power flow only to the mains only is of interest.

In each half cycle, current through the inductor L_s is built up by using a capacitor and the mains voltages in the same sense by turning either T, or T₂ on. When a transistor is off. current transfers to the diode across its complementary transistor. The switching of the two transistors are complementary except for the dead time delay, during which both transistors are off. The dynamic equations of the current through the inductor L_scan be written as:

L_S ^- = V_S - F_X * E_DC+ for T, or D, on (1) at

L_S ^ = V_S - F₂* E_DC_ for T₄ or D₄ on (2) at where F\ = 1 for T, or D, on and Fi = 1 for T_A or D₄ ON; else these are zero.

Assuming identical capacitor values, the dynamic equations of the capacitor currents can be written as:

dE

C M÷ = _F]* i_s - i_L+ ; Fj 1 for T, on (3) at and c ^£_ι = f> /_s - /, ; /^■■-> = 1 for T, on (4) dt ^"

where ι_L _ and /, _. are the positive and the negative dc-link currents respectively .

The dc-link currents i_{t +} and i_L_ are determined by the switching of transistor T, or diode D, in

the step-up rectifier stage.

B. Modelling of the Step-up Rectifier and the Maximum Power Tracker

The equations of current in the PV array circuit are :

l_a ^f- = h? * Esa + F_W (E„ - E_DC) (5) at

where Ef)C is ^me total dc-link voltage, E_sa and i_sa are the PV array voltages and currents respectively. For Fjp = 1 , transistor T, is on and for F$N = 1 , diode D, is on. Obviously, F$p

and Fj^r are complementary time functions. For F$p = 1 , i_L+ = i_L_ = 0 and for F^\ = 1 , i_L+ = -

i_L_ - i_sa. The switching signal for T3 is produced in the control circuit for the MPT which will be

described in section IV. (B)

MODELLING OF THE CONTROLLER CIRCUITS

As mentioned earlier, all controllers for the interconnection have been modelled as discrete time

systems as they were expected to be implemented in this way. The algorithms for these are

described below.

A. The CFRR Controller The CFRR operates with a voltage reference for the dc-link set above 680VDC and below two times the capacitor rated voltage, taking into account the fact the there must be some room for the link voltage to go up when current is forced into the capacitors by the joint operation of the SR and the MPT. The controller for the CFRR is of proportional plus integral (PI) type. At any sampling instant k. the error E_rr(k) in the dc-link voltage controller is

A_Err(k) = E_dcref(k) - E_dc(k) (6)

where Ecj_cref and Efc are the reference and actual values of the dc-link voltage. The PI controller output is

V_rr(k) = K_vrr * A_E (k) + I_rr(k) (7)

K * Δ and I_rr{k) = I_rr{k - \) + -≡ Err &* T„

(8)

T I,rr

where K_vrr, T_srr and T_trr are the proportional gain, sampling interval and the integral time- constant, respectively, of the PI controller for the CFRR. The controller output V(k) is multiplied by a unit sinewave derived from the source voltage v_s to produce the current reference Isreffk) for the CFRR. Thus

I_sref(k) (9)

where V_s(k) is the kth sample and Vs is peak value of the source voltage.

An inner current loop regulates the source current to the above reference according to the following proportional controller where Kp_rr is the gain of the controller and l_s(k) is the source current at the kth sampling instant. The amplified error signal lEsrr(V is then compared with a triangular carrier waveform at a frequency of 5 kHz to produce the pwm switching signals for T, and T₄, subject to the dead time limitation of these switches.

Capacitor voltage balancing is obtained by simply obtaining the difference between the two capacitor voltages, multiplying the difference by a gain Kfy_rr and adding it to l_esrr(k) before

comparing with the carrier waveform.

B. The SR Controller and the MPT

The step-up converter which boosts the PV array voltage to above 680V operates under the control of the maximum power tracker. The power output from the array at the kth sampling instant. P_a(k), is

P_a(k) = V_sa(k)* I_sa(k) (11)

where V_sa(k) and I_sa(k) are the array voltage and current respectively. The error in power between two consecutive samples is

U^> _a(k) = P_a(k) - P_a(k - \) (12) A PI algorithm is chosen for forcing the ΔP to zero which implies operation at the maximum

power point of the v-t characteristic of the The describing equations tor this are

V_p(k) = K_pp * ΔP_a(k) + I_p(k)

K_p * AP{k)* T and I_p(k) = I_p(k - \) + ^— 2L _{( 13)} h_P

where I p(k) is the controller output and Kpp, Tψ and Tjp are the parameters of the PI controller The output Vp(k) forms the current reference for an inner current loop which forces an equivalent current from the array to flow into the dc-link capacitor Again a PI algorithm is chosen for it as given below

M_a(k) = V_p(k) - I_sa(k) (14)

V_sa(k) = K_sap* Al_a(k) + l_a(k) (15)

I_a(k) (16)

where V_sa(k) is the output of the controller and K_sap, T_sa and T_ιa are parameters of the controller V_sa(k) modulates a carrier with 5 kHz switching frequency to determine the switching signals for T3 in the SR

MODELLING RESULTS

The above equations ( 1-16) describing the complete interconnection were solved numerically using Simnon for the following parameters Power circuit: L. = l O mH . L_r = 1 mH. C = 4700μF. V, = 240V.

CFRR: switching frequency = 5 kHz. K_vrr = 2. K_prr = 30. T_srr = 0.00001.

Tι_rr = 0.01. MPT: switching frequency = 5 kHz. K_pp = 1.005, T_sp = 0.00001. Tj_p = 0.0001.

SR: switching frequency = 5 kHz, K_pa = 10. T_sa = 0.00001. Tj_a = 0.01.

The v-i characteristics of the PV array used in the modelling is indicated in figure 4 for four different temperatures. The nominal no-load voltage for the array is 120V.

Figures 5 and 6 show the simulated dc link voltage and the mains voltage and current waveforms

of the interconnection for the innermost array characteristic of figure 4. The corresponding PV array voltage and current are indicated in figures 7 and 8 respectively. These simulations are

started when the dc link capacitors have charged fully through diodes D, and D₂. to twice the

peak of the ac supply voltage. During steady-state, input current waveform of i_s is clearly

sinusoidal and out of phase with the source voltage v_s.

The region around the tip of the innermost triangle of figure 9 indicates the operation of the

interconnection with maximum power tracking. The output power from the array and the current

i_sa drawn from it by the step-up rectifier are indicated. The faint part of the graph indicates the trajectory not traversed by the MPT. During steady-state, when maximum power point is tracked, the operation of the rectifier is confined to a small region around tip of the triangles.

Varying outputs of the array for different operating conditions are simulated by abrupt switching of the array v-i curves as indicated in this figure 9. The maximum power tracking of the array

10

SUBSTΓTUTE SHEET (Rule 26) shifts as the characteristics are switched for higher output power levels The dvnamic response of the MPT tor the four power levels indicated in figure 8 and 9 are shown in figure 10 Changes in the \ -ι characteristics of the PV arrav are simulated b\ abrupt changes to these as

indicated in figure 4 1 he MPT adjusts to these by pumping the appropπate maximum power for each characteristic, as indicated in figure 10. by the output power drawn from the array Vs time These dynamic responses clearly indicate the stable operation of the interconnection for varying conditions of operation of the array

EXPERIMENTAL RESULTS

The proposed circuit of figure 1 has been built and its control has been implemented in a dsp controller For the PV array a dc source of 120V with appropπate series resistance and switches have been used The steady-state and dynamic responses of the CFRR are shown in figures 1 1

and 12 respectively These are experimental results from the ac side and dc link of the CFRR From figure 1 1. it is seen that ac supply current is in phase opposition to the mains voltage waveforms implying energy return Figure 12 clearly shows that ac side current is in phase with the mains voltage when the dc link capacitor is charging and they are in opposition when the PV energy is forced into the mains The experimental results are in good agreement with modelling results

CONCLUSION

This paper has described the modelling and some experimental results pertaining to the development of a new interconnection between a photovoltaic solar arra\ and a 240\ utility grid This interconnection dispenses with the bulky 50 Hz transformer normally used at the output stage of a 50 Hz inverter for pumping the solar energy into the mains. The model is approached from the ac side of the interconnection and simulates the dynamic and steady-state operation of the interconnection. This model provides a means for a detail evaluation of the interconnection

and its design.

REFERENCES

[ 1 ] Schonholzer E. T. and Schmidhauser. "A modular Utility Interface for Photovoltaic Power

Plants", Proc. of European Power Electronics Conference, Vol 3, pp. 81-85. Sevilla.

Spain. 1995.

[2] Steigerwald R. L. et al, "Investigation of a Family of Power Conditioners Integrated into the Utility Grid'^". Sandia National Laboratories Report. Sand 81-7031. 1981.

[3] Steigerwald R. L.. Bose, B. K., and Szczesny, "Design and Construction of an Advanced

Power Conditioning System for Small Photovoltaic Applications^". Sandia Report.

SAND83-7037. 1985. [4] Nonaka S.. Kesamaru K. and Yamasaki Y., "Utility Interactive Photovoltaic System With

PWM Current Source Inverter", Trans. IEE of Japan, Vol. 1 12-B, No. 5, pp. 439-447,

1992.

[5] Makino M. et al. "Digital Control Method for a Photovoltaic Power System". Proc. of

IPEC. Vol. 1 , pp. 197-202. Yokohama. Japan. 1995.

[6] Matsui K. Hu Y. and Ueda F., "Utility-Interactive 3kW Photovoltaic Power Conditioning

System by Using Forward Converter", Proc. of International Power Electronic Conference.

IPEC, Vol. 1 , pp. 189-196, Yokohama, Japan, 1995.

[7] Meinhardt M. and Mutschler P., "Inverters Without Transformer in Grid Connected

Photovoltaic Applications", Proc of European Power Electronics Conference. Vol. 3. pp.

86-91. Sevilla. Spain 1995.

[8] Boys J. T.. ^•iCurrent-forced Single-Phase Reversible Rectifier^". Proc of IEE. Pt. B. Vol.

136. No. 5. 1989, pp. 205-21 1.

Claims

1 A power converter for controlling electrical power flow between a photovoltaic array and an

AC supply mains: said converter comprising a boost converter in combination with a

reversible rectifier.

2 The converter of claim 1 wherein said boost converter comprises a pulse width modulated boost converter adapted to receive power from said photovoltaic array

3 The converter of claims 1 or 2 wherein said reversible rectifier is a puise width modulated current forced reversible rectifier and which is interposed between said AC supply mains and said boost converter.

4 A single phase power converter of the type claimed in claim 1 and as hereinbefore particularly described with reference to what is shown in fig 1

5. The power converter of claim 1 including a control system as hereinbefore particularly described with reference to what is shown in fig 2. 6 The power converter of claim 1 as hereinbefore particularly described and including a control system for said reversible rectifier as hereinbefore particularly described with reference to

what is shown in fig 3.