WO1997031314A1 - Circuits logiques autofiables, tolerants aux fautes et a autodiagnostic, et procedes de conception de tels circuits - Google Patents

Circuits logiques autofiables, tolerants aux fautes et a autodiagnostic, et procedes de conception de tels circuits Download PDF

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Publication number
WO1997031314A1
WO1997031314A1 PCT/NL1997/000080 NL9700080W WO9731314A1 WO 1997031314 A1 WO1997031314 A1 WO 1997031314A1 NL 9700080 W NL9700080 W NL 9700080W WO 9731314 A1 WO9731314 A1 WO 9731314A1
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Prior art keywords
state
vector
vectors
transition
state vector
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PCT/NL1997/000080
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English (en)
Inventor
Meine Jochum Peter Van Der Meulen
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Simtech Beheer B.V.
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Priority to AU18139/97A priority Critical patent/AU1813997A/en
Publication of WO1997031314A1 publication Critical patent/WO1997031314A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/085—Error detection or correction by redundancy in data representation, e.g. by using checking codes using codes with inherent redundancy, e.g. n-out-of-m codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Definitions

  • the present invention relates to a logic circuit and a method for designing such a logic circuit which includes at least one combinational logic circuit provided with at least one input for receiving at least one input vector, at least a first output for outputting at least one output vector, at least a second output for outputting at least one state vector, and at least one feedback input for receiving the at least one state vector, the combinational logic circuit being arranged for transitions from at least one starting state vector to at least one end state vector through transition vectors in dependence on the input vector.
  • the objective of the present invention is to provide logic circuits and a method to design logic circuits which remain operational or change their outputs to a predefined safe output vector, despite failing of a number of components causing a predetermined maximum of bit errors in the state vectors.
  • the object of the invention is to provide logic circuits and a method to design logic circuits which remain operational or switch to a predefined safe output vector, even when a predetermined maximum number of allowed bit errors occur in any of the state vectors of the states as well as of the transitions, and to avoid the necessity of applying the logic circuit two or even more times in parallel.
  • a bit error is a failure of a combinational logic circuit causing one bit xj of a state vector X to have another value than expected.
  • State vector X changes thereby into an adjacent state vector.
  • the Hamming distance d HAM (X1, X2) between two state vectors X1 and X2 being defined as the number of positions in the state vectors where the bits are different.
  • bit errors Two types may occur: static bit errors and dynamic bit errors.
  • a static bit error occurs when a bit does not change from a certain moment in time despite being instructed to do so.
  • static bit errors There are two possible static bit errors: a bit remains 1 or a bit remains 0.
  • Dynamic bit errors occur when a bit changes its value without being instructed to do so.
  • dynamic errors There are two possible dynamic errors: a bit becomes 1 or a bit becomes 0.
  • a dynamic bit error once occurred can either become a static bit error or disappear.
  • the starting cloud including any of the state vectors of the starting state and any of the state vectors which may be obtained after any allowed combination of dynamic bit errors in any of the state vectors of the starting state;
  • an end cloud of state vectors associated with the end state vector including any of the state vectors of the end state, any of the transition state vectors where transitions to the end state might stop due to any allowed static bit error, any of the state vectors which may be obtained after any allowed combination of dynamic bit errors in any of the state vectors of the end state, and any of the transition state vectors which may be obtained after any allowed dynamic bit error in any of the transition state vectors where transitions to the end state might stop due to any allowed static bit error;
  • combinational logic circuits are designed such that any time they have to change a state vector (i.e. a starting state vector) into a next state vector (i.e. an end state vector associated with the actual input) the internal logic components are designed to try to change not only one bit after the other but several predetermined bits (the number being 1 higher than the number of allowed static bit errors, as long as the state vector is still outside the cloud of state vectors of the end state), until one of these bits actually changes. The attempt to change these bits can be done substantially simultaneously.
  • the combinational logic circuit is designed such that the output will be equal for any state vector of a cloud.
  • designing a combinational logic circuit in accordance with the present invention produces logic circuits of which the output does not change even when a predetermined number of bit errors occur through component failure.
  • the present invention also claims a method for designing a logic circuit as defined above, characterized by the addi- tional step of:
  • step of defining object state vectors is carried out by the following rules:
  • Fail-safe behaviour of a state vector occurs when the system designed, due to an error, stops in such a state vector without having reached the end state vector but the output vector related to that state vector defines a safe condition. Then the system stagnates but does not produce dangerous situations.
  • the invention provides a method as defined above, wherein at least one change deviating from the order changes a state vector to a predetermined transition state vector of a fail-safe state having a predefined safe output vector and results in a stagnation of the transition e.g. by assigning the predetermined transition state vector as object state vector to itself.
  • the fail-safe state can comprise several state vectors which e.g. have one another as object vector.
  • the invention provides a method, wherein a predetermined number of dynamic bit errors in the predetermined transition state with safe output vector is allowed by assigning the predetermined transition state vector as object vector to any of the state vectors that may be reached after occurrence of any allowed combination of dynamic bit errors.
  • the invention also relates to a method for designing a logic circuit including at least one combinational logic circuit, being provided with at least a first input for receiving at least one input vector, at least a first output for outputting at least one output vector, at least a second output for outputting at least one state vector, and at least one feedback input for receiving the at least one state vector, the combinational logic circuit being arranged for a transition from a starting state vector to an end state vector through transition vectors in dependence on the input vector, including the following steps:
  • al. define all possible states of the combinational logic circuit; a2. assign a predetermined value to the at least one output for any of the possible states,
  • b transfer the state diagram into Boolean equations in accordance with the following steps- b1. assign a unique binary number, i.e. a state vector, to any of the possible states and assign unique binary numbers, i.e. transition state vectors, to any of the possible transitions;
  • bit errors either static bit errors or dynamic bit errors or both, for the starting state vector, the end state vector and any possible transition vector
  • step b1 e. in step b1 :
  • a starting cloud of state vectors associated with the starting state vector including any of the state vectors of the starting state and any of the state vectors which may be obtained after any allowed combination of dynamic bit errors in any of the state vectors of the starting state;
  • step b3 define output vectors for any of the state vectors and transition state vectors such that the output vector is equal for the state vectors within the starting cloud and the end cloud, respectively, at least including those state vectors obtainable by a static bit error;
  • step b5 defining object state vectors in the transition for any of the state vectors of the starting state and of the end state and for any transition state vector in accordance with the following rules: g1. assign a state vector of the end state as object state vector to any of the state vectors within the end cloud;
  • each of the state vectors has to change a predetermined number of predetermined individual bits, the number being at least 1 higher than the number of allowed bit errors in the state vectors, but such that one of the at least one state vector of the end state will be the object state vector after multiple successive state vector transitions.
  • a logic circuit includes at least one combinational logic circuit provided with at least one input for receiving at least one input vector, at least a first output for outputting at least one output vector, at least a second output for outputting at least one state vector, and at least one feedback input for receiving the at least one state vector, the combinational logic circuit being arranged for controlling at least one transition from at least one starting state vector to at least one end state vector via transition vectors m dependence on the input vector, characterized in that said combinational logic circuit is arranged such that when changing bits of said state vectors during said at least one transition the combinational logic circuit tries to change a predetermined number of predetermined individual bits for any current state vector, the number being at least 1 higher than the number of allowed static bit errors in the state vector, as long as the Hamming distance between the current state vector an the end state vector so allows and if not, the combinational logic circuit tries to change the current state vector into said end state vector.
  • the logic circuit may be provided with delay elements to control the at least one transition via transition vectors on a trajectory of normal operation consisting of predetermined adjacent state vectors between the starting vector and the end state by providing predetermined amounts of delay to any of the bits instructed to change such that changing bits is controlled in a predefined order.
  • the latter logic circuit may be designed such that it stagnates when a predetermined transition state outside the trajectory of normal operation is obtained and the predetermined transition state is related to a safe output vector. Moreover, the logic circuit may be designed to tolerate a predetermined number of dynamic bit errors in the predetermined transition state with safe output vector. It is observed that the end state might become a starting state for a further transition if the input changes.
  • Logic circuits according to the invention may be based on any known type of technology, e.g., digital logic components, transistor based logic components, relays based logic components. Examples of applications are:
  • safety systems e.g., in nuclear power plants or railway networks in which safety is a key requirement
  • Figure 1 shows a combinational logic circuit diagram as known from the prior art
  • Figure 2a shows a diagram to illustrate the concept transition and to show the consequences of a static bit error
  • Figure 2b shows a diagram to illustrate the consequences of a dynamic bit error during a transition in accordance with the transition shown in figure 2a;
  • Figure 2c shows a diagram to illustrate the principle of failsafe behaviour of a combinational logic circuit in accordance with the invention
  • Figure 3 shows an example of a logic circuit diagram for traffic light control, the logic of which is to be designed in accordance with the present invention
  • Figure 4 shows a state diagram, the subsequent states of which being associated with the logic circuit diagram of figure 3.
  • Bits x1, x2, ... xn are output bits of the combinational logic circuit 1.
  • the output bits x1, x2, ... xn are fed back to a further input of the combinational logic circuit.
  • the possible delay in the combinational logic circuit, or in the feedback is modelled by the delay boxes d1 , ..., dn in the feedback lines.
  • Output bits u1 , u2, ... urn are related to the input bits i 1 , i2 . . . , ik and the state vectors x 1 , x2 ,
  • Stable state vectors X are state vectors which do not change when input bits (i1, i2, ... ik) do not change.
  • a usual way of designing level-mode sequential circuits includes the next steps:
  • 1a define any possible state of the logic circuit to be designed
  • 1b define output vectors of the logic circuit in dependence of any possible state and on any possible input
  • any of the output vector bits has either a logic value "0", "1” or "X", where "X" is a "don't care” value
  • 1c define possible transitions between any combination of subsequent states, the transitions being dependent on the values of the input vector bits to the combinational logic circuit; the input vector bit values may be either "0", "1" or "X".
  • the combinational logic circuit will have to be designed such that after a failure of hardware components causing a predetermined number of allowed bit errors in the state vector, the operation of the combinational logic circuit is either maintained, i.e. , the output vector U is, then, not changed or the operation of the combinational circuit is stopped while changing the output vector U to a predetermined safe state.
  • the combinational logic circuit 1 either still produces the desired output vector U (fault tolerant condition) or a predefined safe output vector Ufs (fail-safe condition)
  • object state vectors may be assigned by the following rules:
  • Such a combinational logic circuit can be modelled in the same way as in figure 1, be it that the delay elements d1, ..., dn are now physical delay elements (and not just models of unavoidable delays introduced by hardware as in the prior art) introducing an intended delay by a predetermined amount differing from bit to bit. Now, these delay elements d1, ..., dn delay the change of the bits of the state vector to the object state vector in a predetermined order, the amount of delay being dependent on the bit concerned of the state vector Xj, the state vector X and the input I.
  • the logic circuit is allowed to have a predetermined number of bit errors in the state vectors, including a set of combinations of n t static bit errors and n. dynamic bit errors.
  • the output U and the sequential behaviour of the output will remain unchanged.
  • the output is a predefined safe output vector
  • the combination of allowed static and dynamic bit errors may be different for different state vectors and for different transition state vectors.
  • every state is distinguishable even when a predetermined combination of static and/or dynamic bit errors occurs.
  • To be distinguishable state vectors X1 and X2 of two different states must fulfil a predetermined condition .
  • n stat 1
  • n dy n 0
  • X1 11011, see figure 2a.
  • transition state vectors 11001, 10001, 00001, 00000.
  • the combinational logic circuit 1 must be designed such that its output U has the same value irrespective whether the state vector is 00000 (i.e. X2) or 00001.
  • the combinational logic circuit has to be designed such that output vector U will have the same value for state vector X2 and for any transition state vector where possible transitions to state vector X2 possibly stops due to static bit errors, for a given input vector I.
  • a stable state T is a state that does not change for a given input I.
  • a stable state may correspond to one state vector, e.g. X2, only.
  • a stable state T may include a predetermined set of state vectors meeting the condition that, for a given input vector I, any state vector of this set has an object state vector which is also part of this set.
  • a stable state T2 may include state vector X2 and one or more other state vectors (not shown in figure 2a). Only one output vector U may be associated with any of the state vectors of this stable state T2.
  • the same output vector U must be associated both to any state vector obtained by any allowed combination of bit errors in any of the state vectors of this stable state T2 and to any transition state vector where possible transitions to this stable state T2 possibly stop due to static bit errors, for a given input vector I.
  • Figure 2a shows an example where a transition has to be made from a starting state T1, including only state vector X1, to stable state T2, including only state vector X2.
  • FIG 2a shows state T1 to be a starting state and T2 to be an end state it is observed that state T2 might become a starting state in a further transition when input I changes (see also figure 4).
  • Any of these transition state vectors where a transition from X1 to X2 possibly stops will have to be recognized by the combinational logic circuit 1 as belonging to X2 This is indicated by a "cloud" C2 around state vector X2 in figure 2a. Note that for the given input I initiating this transition from X1 to X2, state T1 is unstable. State T1 might be stable for another input 11. Which state vectors belong to cloud C1 associated with state T1 is only clear by evaluating any transition (not shown) ending in T1.
  • bits are changed one after another, where a bit is only allowed to change if the preceding bit is actually changed.
  • the combinational logic circuit is designed to change at least two bits substantially simultaneously, as long as the Hamming distance between an actual transition state vector and stable state T2 is 2 or more. Moreover, in the combinational logic circuit in accordance with the present invention it doesn't matter which of these at least two bits is changing first. In other words, the occurrence of critical races does neither affect the value of the output vector U, nor the behaviour of sequential output vectors U. As shown in figure 2a, when changing from state vector X1 to stable state vector X2, the combinational logic circuit 1 follows a route along at least three transition state vectors between X1 and X2.
  • the combinational logic circuit associated with the transition diagram of figure 2a is designed in accordance with the following rules:
  • X2 is the object state vector for any of the transition state vectors XT6-XT9
  • the instruction is to change only one bit since the Hamming distance from these transition vectors to state vector X2 is only 1.
  • the transition from X1 to XT6 can only be obtained by designing the combinational logic circuit such that it changes, normally, at least two bits substantially simultaneously, as long as the actual transition state vector is outside cloud C2. If not, the transition would stagnate whenever the last bit would have to change its value. In the combinational logic circuit in accordance with the present invention, such a stagnation can never occur (of course, assuming no more bit errors occur than are allowed when designing the logic circuit).
  • transition state vector XT9 will be reached which is part of cloud C2 and is associated with the same output as X2.
  • the transition includes each of the transition state vectors XTj between X1 and X2 which may be reached by normal state vector transitions with the bits changing in any order combined with any allowed combination of static bit errors and sequence thereof; moreover object state vectors must be assigned to these possible transition state vectors;
  • the object state vectors when assigning object state vectors to transition state vectors the object state vectors must be such that X2 will be reached by successive state vector transitions, irrespective of the order of the bit changes and the occurrence of allowed static bit errors and sequence thereof.
  • a trajectory of normal operation is defined consisting of predetermined adjacent state vectors between the starting vector X1 and the end state T2.
  • the logic circuit tries to change an actual state vector to the adjacent state vector on the trajectory of normal operation before a deviation of that trajectory is allowed.
  • one allows, e.g., two bits of any state vector to change one prescribes the order of change of these two bits. The order is such that if no error occurs the trajectory of normal operation will be followed.
  • object states may also be defined in other ways.
  • the algorithm for the first option comprises the following steps.
  • trajectory of normal operation between starting state vector X1 and the end state vector X2, the trajectory of normal operation comprising a selected set of adjacent (transition) state vectors X1, XT1, XT4, XT8, X2 between the starting point X1 and the end state vector X2, 2. assign as object state vector to starting state vector X1 that transition state vector on the trajectory of normal operation, which has a distance to starting state vector X1 equal to the number of allowed static bit errors plus 1 (in the example of figure 2a, XT4 is object state vector of X1);
  • step 5 determine all transition vectors that can be obtained between the transition state vectors of step 3 and their object state vector as defined in step 4 (in the example of figure 2a, these are XT3, XT4, XT5);
  • step 6 repeat steps 4 and 5, wherein in steps 4 and 5 "step 3" is amended into “step 5", until the transition state vectors determined in step 5 are within the "cloud” C2 of state vectors associated with the end state vector X2; if so go to step 7;
  • end state vector X2 as object state vector to end state vector X2 itself and to any of the transition state vectors within the cloud C2 of state vectors associated with the end state vector X2.
  • the algorithm for the second option comprises the following steps:
  • trajectory of normal operation between starting state vector X1 and the end state vector X2, the trajectory of normal operation comprising a selected set of adjacent (transition) state vectors X1, XT1, XT4, XT8, X2 between the starting point X1 and the end state vector X2;
  • step 4 repeat step 4 until any of the transition state vectors have been assigned an object state vector; if so, assign an object state vector to the starting state vector X1 in accordance with the ruling of step 4.
  • the starting state T1 and the end state T2 are assumed to include one state vector only. However, the same principles hold when it is assumed that they comprise more than one state vector.
  • XT4 which is located on the trajectory of normal operation, is assigned as object state vector to XT11.
  • X2 which is located on the trajectory of normal operation, is assigned as object state vector to XT13.
  • XT14 is withm cloud C2 and has X2 as an object state vector.
  • transition state vectors can be obtained between starting state vector X1 and end state vector X2 by any allowed dynamic bit error and which have not already been assigned an object state vector; assign an object state vector to these transition state vectors, that is closest to the trajectory of normal operation or on the trajectory of normal operation itself, and closest to the end state vector X2, the Hamming distance between this object state vector and these transition state vectors being equal to or larger than the number of allowed static bit errors plus 1.
  • the number of bits of either the starting state vector X1 or any of the transition state vectors XT located outside the cloud C2 and to be changed by the combinational logic circuit is always one more than the possible number of static bit errors.
  • state vector X is a transition state vector not belonging to a cloud.
  • transition state vectors not belonging to a cloud are XT1 - XT5.
  • the value of output U of the combinational logic circuit may be dependent on the value of input I.
  • a combinational logic circuit shows the following possible reactions when during a fault tolerating state transition from T1 to T2 at a certain transition state vector XT the input value I changes to I':
  • transition state vector XT continues with a fault tolerating transition to another state T3 for input I'; this is possible when the logic circuit is designed such that state vector X1 has a transition to state T3 for input I', then, the transition transfers into another transition which would have been normally initiated by input I' from state vector X1 ;
  • transition state vector XT continues with a fault tolerating transition towards T2 for input I'; the transition will continue unaffected;
  • transition state vector XT continues with a fault tolerating transition towards T1 for input I'; then, the desired transition does not occur or is cancelled;
  • transition state vector XT continues with a fault tolerating transition to another state T3 for input I'; this is possible when the logic circuit is designed such that state vector X2 has a transition to state T3 for input I'; then, the transition transfers into another transition which would have normally followed the transition from X1 to X2 Note, that the transfer of the transition might influence the possible present bit errors.
  • fail-safe properties can be assigned to predefined state vectors. There are several options to assign an object state vector to such predefined state vectors:
  • the object state vector remains the object state vector already assigned in accordance with the fault tolerant principle explained above; moreover, the output signal related to any of such predefined state vectors is changed to a safe output signal, or;
  • the object state vector is changed such that it becomes the state vector itself; moreover, the output signal related to such any of such predefined state vectors is changed to a safe output signal, or;
  • the object state vector is changed to another state vector, which is also assigned an object state vector, and so forth, such that only state vectors are reached, possibly after successive state vector changes, having a safe output signal.
  • circuitry may continue normal operation after disappearance of the faults in the state vector.
  • FIG 2c an example is given of the assignment of fail-safe properties.
  • Figure 2c starts from figure 2a and shows the situation that transition state vectors XT2 and XT5 have been given fail-safe pro- pertie ⁇ .
  • the object state vector of XT5 no longer is XT2 but XT5 itself and a safe output vector is associated with XT5.
  • a safe output vector is associated with XT5.
  • the situation of XT5 in figure 2c refers to one in which one static bit error is allowed, which results in a fail-safe stagnation.
  • XT2 refers to a situation in which one wishes that a fail-safe condition also tolerates one dynamic bit error.
  • the output related to XT15 is a safe output vector.
  • XT15 assigns XT15 as object state vector to any of the state vectors XT16, XT17, XT18, and XT19.
  • output vectors related to XT2, XT16, XT17, XT18, and XT19 need be safe depends on how long these states can exist and how dangerous the effects of these output vectors are.
  • the logic circuit controls a traffic light it does not matter that the green light unintentionally lights up during 1 millisecond; nobody will notice that.
  • a logic circuit able to control the subsequent burning of the red, green and yellow lamps within a traffic light is shown in figure 3.
  • the logic circuit 1 shown in figure 3 is similar to the one of figure 1.
  • output vector U comprises only three bits u1, u2, u3 and input vector I comprises only one input bit i1.
  • Input bit i1 may either have the value "0" or "1".
  • the value of input bit i1 may be controlled by a push button (not shown).
  • the logic circuit to be designed comprises six states with six transitions in between.
  • the graph representing these states and transitions is shown in figure 4.
  • the output vector U may have any arbitrary value since the outputs u1, u2, u3 are connected to the lamps and the transitions are so fast that a human eye is not able to see any change of the output U during the transition.
  • the input i1 may change but, then, the state transition must be completed.
  • trajectory of normal operation listed m the table meets the criteria of the definition of a trajectory of normal operation m accordance with the present invention.
  • the Hamming distance of the state vectors X1, X2, ..., X6 of the states is at least 3, which meets the condition given above.
  • the combinational logic circuit can be implemented in standard technology, by further using standard methods. Definitions:
  • Level-mode sequential circuit A circuit as drawn in figure 1.
  • a Level-Mode Sequential Circuit has inputs (I and X) and outputs (U and X'). The outputs X' are fed back as inputs X, and determine the sequential behaviour of the circuit.
  • the delay elements are not specific elements inserted in the feedback path, but represent the distributed delays in the combinational logic.
  • State diagram A model describing the sequential behaviour of a Level-Mode Sequential Circuit.
  • a state diagram comprises of states and transitions. It defines the input initiating the transitions between states and the outputs as function of the state and/or the input.
  • Stable State A state not having a transition to another state for a specific input I.
  • State Vector A specific binary combination X representing a state or transition.
  • Object State Vector A specific binary combination X' representing object states and object transitions.
  • the object state vector depends on the state vector X and the input I.
  • Bit Error A bit error is the deviation of a bit of the actual object state vector from the defined object state vector, caused by a (hardware) failure in the combinational logic.
  • Static Bit Error A bit error, characterized by a bit not changing its value despite being instructed to do so.
  • Dynamic Bit Error A bit error, characterized by a bit madver- tently changing its value. A dynamic bit error once occurred can become a static bit error, or it can disappear.
  • Starting cloud includes any of the state vectors of a starting state and any of the transition state vectors which may be obtained af ter any al lowed dynamic bi t error in any of the state vectors of the starting state.
  • End cloud includes any of the state vectors of an end state, any of the transition state vectors where transitions to the end state might stop due to any allowed static bit error, any of the state vectors which may be obtained after any allowed combination of dynamic bit errors in any of the state vectors of the end state, and any of the transition state vectors wnich may be obtained after any allowed dynamic bit error in any of the transition state vectors where transitions to the end state might stop due to any allowed static bit error.

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Abstract

On décrit un circuit logique combinatoire ainsi qu'un procédé de réalisation d'un tel circuit conçu pour que chaque fois qu'il doit changer un vecteur d'état de début (X1) en un vecteur d'état de fin (X2), via des vecteurs d'état de transition (XTi), ce circuit logique combinatoire essaie de changer un nombre défini de binaires individuels déterminés pour chaque vecteur d'état courant sur le trajet vers le vecteur d'état de fin (ce nombre étant au moins supérieur de 1 au nombre d'erreurs de binaires statiques permis dans le vecteur d'état), pour autant que le permette la distance de Hamming entre le vecteur d'état courant et le vecteur d'état de fin; dans le cas contraire, le circuit combinatoire essaie de changer le vecteur d'état courant en un vecteur d'état de fin.
PCT/NL1997/000080 1996-02-23 1997-02-21 Circuits logiques autofiables, tolerants aux fautes et a autodiagnostic, et procedes de conception de tels circuits WO1997031314A1 (fr)

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EP96200472.7 1996-02-23
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