WO1997030480A1 - Low resistivity thin film conductor for high temperature integrated circuit electronics - Google Patents
Low resistivity thin film conductor for high temperature integrated circuit electronics Download PDFInfo
- Publication number
- WO1997030480A1 WO1997030480A1 PCT/US1997/002280 US9702280W WO9730480A1 WO 1997030480 A1 WO1997030480 A1 WO 1997030480A1 US 9702280 W US9702280 W US 9702280W WO 9730480 A1 WO9730480 A1 WO 9730480A1
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- thin film
- conduαor
- integrated circuit
- gold
- high temperature
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53247—Noble-metal alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to high temperature electronics and more particularly to metal alloy conductors for use in high temperature semi ⁇ conductor integrated circuit electronics.
- MTTF due to electromigration (EM) in metal conductors used in integrated circuits varies as J N where N is normally equal to or greater than two.
- the electromigration rate also increases exponentially with temperature.
- Aluminum is clearly the present metal of choice for IC conductors. It provides low resistivity, resistance to corrosion, and with proper processing an excellent step coverage over non-smooth surface mo ⁇ hology. However, the same basic property which permits good step coverage, intra-atom bonds that are relatively easily broken, makes a material more susceptible to electromigration. While aluminum films are sufficiently stable to yield acceptable life in most power ICs at 125 ⁇ C, there are serious life problems well below 200°C. Considerable effort has been expended to increase the high current density life of aluminum films through the addition of small percentages of other elements. Increases in life by over an order of magnitude have been reported with several different additions. However, the addition of other elements are also associated with increases in resistivity of the conductor.
- the second metalization scheme used titanium tungsten (TiW) which was also passivated with a conformal Si 3 N 4 coating after patterning and which was even more stable than the WN-W-WN conductor.
- TiW titanium tungsten
- This alloy with 30 atomic percent Titanium, yields a much larger mobility for sputter deposited atoms. This eliminates the fibrous grain structure and produces much more conformal step coverage.
- the resistivity of TiW is greater than that for W films by four times at 300°C and three times at 400°C. While various conductors have been developed for high temperature operation, no clear choice has emerged. The need still remains for reliable interconnection line conductors and contacts with good step coverage, acceptable resistivities, and low susceptibility to corrosion and electromigration for use in high temperature semiconductor integrated circuits.
- An alloy film of Au with a small percentage of a reactive element, such as Cr, is utilized in high temperature integrated circuit electronics to obtain thin Au conductor films with a near perfect conformal passivating coating that greatly suppresses void injection and surface atom transport. This redu ⁇ ion of void inje ⁇ ion and surface transport reduces the Au ele ⁇ romigration (EM) by orders of magnitude.
- the integrated circuit wafer is heated in an appropriate atmosphere, such as air, causing the rea ⁇ ive element to diffuse to the surface of the Au film and rea ⁇ with the atmosphere.
- the rea ⁇ ive element is Cr this creates a conformal passivating coating of Cr : O, on all exposed surfaces of the Au alloy conductor with virtually no flaws.
- FIG. 1 is a se ⁇ ion view of an Au alloy thin film layer on an integrated circuit surface prior to etching to form the patterned interconne ⁇ ion lines;
- FIG. 2 is a se ⁇ ion view of an Au alloy thin film layer on an integrated circuit surface after etching to form the patterned interconne ⁇ ion lines but prior to passivation;
- FIG. 3 is a se ⁇ ion view, taken in FIG. 4 along the line H -III, of an Au alloy thin film condu ⁇ or according to the present invention.
- FIG. 4 is a perspe ⁇ ive view of a portion of an integrated circuit showing some exemplary interconne ⁇ ion line condu ⁇ ors.
- an improved thin film metalization condu ⁇ or 14 according to the teaching of the present invention, particularly suitable for high temperature semicondu ⁇ or integrated circuit ele ⁇ ronic condu ⁇ ors and conta ⁇ s.
- This improved thin film metalization construction incorporates gold (Au) to obtain a lower resistivity, such as 4.9 ⁇ cm at 300 C C, than is available in the prior art.
- Au gold
- This invention utilizing an Au rea ⁇ ive element alloy, presents a superior approach for obtaining conductor films 14 with a near perfe ⁇ sealing conformal passivating coating that greatly suppresses void inje ⁇ ion and surface atom transport.
- an alloy layer 8 of Au with a small percentage of a reactive element, preferably Cr, is utilized. After the Au alloy layer 8 is patterned into the desired conductor network, the wafer is heated in air causing the Cr to diffuse to the surface and rea ⁇ with the atmosphere. This creates a conformal passivating Cr.O. coating 16 on all exposed surfaces of the condu ⁇ or 14 with virtually no flaws.
- the thin file condu ⁇ or 14 is formed by producing an Au alloy layer 8, as shown in FIG. 1, on an insulating layer 12 which will form part of an integrated circuit.
- the thin film Au alloy conducting layer 8 can be formed on layer 12 by means well known in the art such as sputtering, vacuum evaporation, electroplating or the like.
- the Au alloy layer 8 is then etched to form the condu ⁇ or 10, as shown in Fig. 2, with the desired pattern of interconnection lines, as shown in FIG. 4.
- the layer 12 on which condu ⁇ or 14 is formed can be for example SiO. or SijN «.
- FIG. 2 shows the Au thin film condu ⁇ or 10 deposited on layer 12 after etching but before passivation and formation of the conformal C ⁇ t Oi coating 16.
- the Au thin film condu ⁇ or 10 does not need passivation to avoid corrosion.
- uncoated Au films cond ⁇ ing large current densities yield disappointingly short operational life due to EM.
- This is greatly accelerated by the void inje ⁇ ion and atomic transport that occurs at free polycrystalline Au surfaces.
- Encapsulating all free Au surfaces within a passivating layer 16 nearly eliminates both of these processes and greatly reduces EM induced damage.
- the lack of detectable EM damage in Cr 2 O_ coated Au films with our normal accelerated life test makes extrapolation to a MTTF at 300 ⁇ C questionable, but it is likely to be many years even for high temperature power ele ⁇ ronics.
- the thin film Au conductor 14 is formed by etching the AuCr alloy layer 8 on the surface 12 of an integrated circuit to form the desired pattern of interconnection line condu ⁇ ors for the specific circuit.
- the Au alloy interconnection lines 10 are formed by etching in a manner well known in the integrated circuit art. After the Au alloy lines 10 are etched on the integrated circuit surface they are heated in an appropriat atmosphere. In practicing the invention the chromium can be oxidized by heating the patterned conductor lines 10 Ln air. When the AuCr thin film conductor 10 is heated in air some Cr diffuses to the surface and oxidizes forming a thin coating 16. This produces an excellent conformal passivating film of Cr 2 O 3 . The passivation properties of Cr 2 O_ in stainless steels are well established. As shown in FIG. 3 after heating the Cr is depleted in the Au alloy thin film condu ⁇ or 10 which increases its condu ⁇ ivity.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Improved high temperature conductors (14) and contacts are formed by utilizing a film of gold with a small percentage of a reactive element. After the thin film of gold and the reactive element is patterned into the desired conductor (10) configuration the wafer surface (12) on which it is being utilized is heated in an appropriate atmosphere causing the reactive element to diffuse to the thin film conductor (10) surface and react with the atmosphere. Preferably, a gold alloy with a chronium content of approximately 2 % is utilized. Heating the gold alloy conductor in air creates a conformal passivating coating (16) of Cr2O3 on all surfaces of the conductor (10) with virtually no flaws.
Description
Low Resistivity Thin Film Conductor for High Temperature Integrated Circuit Electronics
Background of the Invention
1. Field of the Invention
This invention relates to high temperature electronics and more particularly to metal alloy conductors for use in high temperature semi¬ conductor integrated circuit electronics.
2. Description of Prior Art
Power integrated circuit electronics require high current densities (J) in parts of their thin film on-chip conduαor networks. The mean time to failure
(MTTF) due to electromigration (EM) in metal conductors used in integrated circuits varies as JN where N is normally equal to or greater than two. The electromigration rate also increases exponentially with temperature. These two factors, current density and temperature, combine to make electromigration produced conductor opens (voids) or shorts (hillocks) major concerns as failure mechanisms in high temperature power integrated circuit electronics.
Aluminum is clearly the present metal of choice for IC conductors. It provides low resistivity, resistance to corrosion, and with proper processing an excellent step coverage over non-smooth surface moφhology. However, the same basic property which permits good step coverage, intra-atom bonds that are relatively easily broken, makes a material more susceptible to electromigration. While aluminum films are sufficiently stable to yield acceptable life in most power ICs at 125βC, there are serious life problems well below 200°C. Considerable effort has been expended to increase the high current density life of aluminum films through the addition of small percentages of other elements. Increases in life by over an order of magnitude have been reported with several different additions. However, the addition of other
elements are also associated with increases in resistivity of the conductor.
Even if the increased resistivity is tolerable, a practical life for these alloys at power IC current densities have not been demonstrated for temperatures much above 200°C.
At the Second International High Temperature Electronics Conference two metalization schemes with conductors utilizing tungsten (W) for high temperature electronics were reported on. The first was a patterned WN-W- WN sandwich with a passivating conformal silicon nitrite (Si3N4) coating. This combination exhibited excellent stability even at 400*C and an acceptable resistivity. However, the growth pattern of sputter deposited W films creates a fundamental problem with voids in step coverage. The reliability and life problems introduced by voids caused efforts to continue to find another conductor for high temperature integrated circuit applications.
The second metalization scheme used titanium tungsten (TiW) which was also passivated with a conformal Si3N4 coating after patterning and which was even more stable than the WN-W-WN conductor. This alloy, with 30 atomic percent Titanium, yields a much larger mobility for sputter deposited atoms. This eliminates the fibrous grain structure and produces much more conformal step coverage. However, the resistivity of TiW is greater than that for W films by four times at 300°C and three times at 400°C. While various conductors have been developed for high temperature operation, no clear choice has emerged. The need still remains for reliable interconnection line conductors and contacts with good step coverage, acceptable resistivities, and low susceptibility to corrosion and electromigration for use in high temperature semiconductor integrated circuits.
Summary of the Invention
An alloy film of Au with a small percentage of a reactive element, such as Cr, is utilized in high temperature integrated circuit electronics to obtain thin Au conductor films with a near perfect conformal passivating coating that greatly suppresses void injection and surface atom transport. This reduαion of void injeαion and surface transport reduces the Au eleαromigration (EM) by
orders of magnitude. After the Au alloy is produced and patterned into the desired conduαor network, the integrated circuit wafer is heated in an appropriate atmosphere, such as air, causing the reaαive element to diffuse to the surface of the Au film and reaα with the atmosphere. When the reaαive element is Cr this creates a conformal passivating coating of Cr:O, on all exposed surfaces of the Au alloy conductor with virtually no flaws.
Brief Description of Drawings
For a better understanding of the invention reference may be had to the preferred embodiments exemplary of the inventions shown in the accompanying drawings in which:
FIG. 1 is a seαion view of an Au alloy thin film layer on an integrated circuit surface prior to etching to form the patterned interconneαion lines;
FIG. 2 is a seαion view of an Au alloy thin film layer on an integrated circuit surface after etching to form the patterned interconneαion lines but prior to passivation;
FIG. 3 is a seαion view, taken in FIG. 4 along the line H -III, of an Au alloy thin film conduαor according to the present invention; and,
FIG. 4 is a perspeαive view of a portion of an integrated circuit showing some exemplary interconneαion line conduαors.
Detailed Description of the Preferred Embodiments
Referring now to the drawings and FIG. 3 in particular there is shown an improved thin film metalization conduαor 14, according to the teaching of the present invention, particularly suitable for high temperature semiconduαor integrated circuit eleαronic conduαors and contaαs. This improved thin film metalization construction incorporates gold (Au) to obtain a lower resistivity, such as 4.9μΩcm at 300CC, than is available in the prior art.
This invention, utilizing an Au reaαive element alloy, presents a superior approach for obtaining conductor films 14 with a near perfeα sealing conformal passivating coating that greatly suppresses void injeαion and surface atom transport. The large reduαion of void iηjeαion and surface transport reduces the eleαromigration damage rate by orders of magnitude. Instead of depositing a capping layer (which inherently will have many flaws), an alloy layer 8 of Au with a small percentage of a reactive element, preferably Cr, is utilized. After the Au alloy layer 8 is patterned into the desired conductor network, the wafer is heated in air causing the Cr to diffuse to the surface and reaα with the atmosphere. This creates a conformal passivating Cr.O. coating 16 on all exposed surfaces of the conduαor 14 with virtually no flaws.
The thin file conduαor 14 is formed by producing an Au alloy layer 8, as shown in FIG. 1, on an insulating layer 12 which will form part of an integrated circuit. The thin film Au alloy conducting layer 8 can be formed on layer 12 by means well known in the art such as sputtering, vacuum evaporation, electroplating or the like. The Au alloy layer 8 is then etched to form the conduαor 10, as shown in Fig. 2, with the desired pattern of interconnection lines, as shown in FIG. 4. The layer 12 on which conduαor 14 is formed can be for example SiO. or SijN«. FIG. 2 shows the Au thin film conduαor 10 deposited on layer 12 after etching but before passivation and formation of the conformal CτtOi coating 16.
The Au thin film conduαor 10 does not need passivation to avoid corrosion. However, uncoated Au films condυαing large current densities yield disappointingly short operational life due to EM. This is greatly accelerated by the void injeαion and atomic transport that occurs at free polycrystalline Au surfaces. Encapsulating all free Au surfaces within a passivating layer 16 nearly eliminates both of these processes and greatly reduces EM induced damage. The lack of detectable EM damage in Cr2O_ coated Au films with our normal accelerated life test makes extrapolation to a MTTF at 300βC questionable, but it is likely to be many years even for high temperature power eleαronics.
The thin film Au conductor 14 is formed by etching the AuCr alloy layer 8 on the surface 12 of an integrated circuit to form the desired pattern of interconnection line conduαors for the specific circuit. The Au alloy interconnection lines 10 are formed by etching in a manner well known in the integrated circuit art. After the Au alloy lines 10 are etched on the integrated circuit surface they are heated in an appropriat atmosphere. In practicing the invention the chromium can be oxidized by heating the patterned conductor lines 10 Ln air. When the AuCr thin film conductor 10 is heated in air some Cr diffuses to the surface and oxidizes forming a thin coating 16. This produces an excellent conformal passivating film of Cr2O3. The passivation properties of Cr2O_ in stainless steels are well established. As shown in FIG. 3 after heating the Cr is depleted in the Au alloy thin film conduαor 10 which increases its conduαivity.
The praαicality of this process has been demonstrated with an Au -2% Cr alloy. As formed, a lμm thick conduαor film of this alloy had a room temperature resistivity of 3.8μΩcm. After 400 hours, at 400°C with a J of 106 A/cm the resistivity had dropped to within 6% of gold's bulk resistivity of 2.35μΩcm. The Cr had diffused out and oxidized into a Cr2O3 layer formed on the surface of the gold film. No evidence of EM damage could be detected as the samples were free of voids and hillocks and the resistivity had steadily decreased to almost the bulk Au value. Because no onset of failure was evident, estimation of the MTTF is difficult. Using conservative models it was estimated that the MTTF at 300°C for J = 4xl03 A/cm2 will be greater than 5 years.
Because Cr2O3 films have such outstanding performance in the passivation of stainless steels, it is likely that Cr is the best reaαive element for this invention. However, it should be realized that the basic invention could be used with other reaαive elements. The Inventors also recognizes that other
gaseous atmospheres can be used to form different conformal coating layers such as nitrides, carbides, or the like.
Claims
1. A thin film conduαor for high temperature power integrated circuit electronics comprising: a thin film gold alloy conductor with a small percentage of a reaαive element some of which is diffused to the thin film gold conduαor surface to create a conformal passivating coating.
2. A thin film conduαor as claimed in Claim 1 wherein the conduαor is formed with gold and approximately a 2% chromium alloy.
3. A thin film conduαor as claimed in Claim 2 wherein the conformal passivating coating comprises Cr2O3
4. A mαhod of fabricating a thin film conduαor for high temperature power integrated circuit eleαronics comprising the steps of: a) forming a thin film of gold with a small percentage of a reaαive element on the integrated circuit insulating wafer to form the desired conduαor network; and, b) heating the wafer in an appropriate atmosphere causing some of the reactive element to diffuse to the gold film surface and reaα with the atmosphere to create a conformal passivating coating on exposed surfaces of the thin film conduαor.
5. A method as claimed in Claim 4 wherein the thin film of gold is an alloy comprising approximately 2% chromium.
6. A method as claimed in Claim S wherein the thin film conduαor is formed by producing a layer of the gold alloy on the integrated circuit insulating wafer and etching away a portion of the layer to form the desired conduαor network.
7. A mαhod as claimed in Claim 6 wherein the atmosphere in which the wafer is heated comprises air.
8. A low resistivity thin film conductor for high temperature power integrated circuit eleαronics comprising a gold alloy with approximately 2% chromium.
9. A low resistivity thin film conductor as claimed in Claim 8 comprising a conformal passivating coating of Cr2O3
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US60267596A | 1996-02-16 | 1996-02-16 | |
| US08/602,675 | 1996-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1997030480A1 true WO1997030480A1 (en) | 1997-08-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1997/002280 WO1997030480A1 (en) | 1996-02-16 | 1997-02-12 | Low resistivity thin film conductor for high temperature integrated circuit electronics |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3591838A (en) * | 1967-12-28 | 1971-07-06 | Matsushita Electronics Corp | Semiconductor device having an alloy electrode and its manufacturing method |
| JPS512997A (en) * | 1974-06-27 | 1976-01-12 | Copal Co Ltd | KUMAKUKAHENTEITEIKOSOSHINO SEIZOHOHO |
| EP0335383A2 (en) * | 1988-03-30 | 1989-10-04 | Hitachi, Ltd. | Semiconductor device having a metallization film layer |
| EP0499050A1 (en) * | 1991-02-13 | 1992-08-19 | International Business Machines Corporation | Method for depositing interconnection metallurgy using low temperature alloy processes |
| EP0601509A1 (en) * | 1992-12-07 | 1994-06-15 | Nikko Kyodo Co., Ltd. | Semiconductor devices and method of manufacturing the same |
-
1997
- 1997-02-12 WO PCT/US1997/002280 patent/WO1997030480A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3591838A (en) * | 1967-12-28 | 1971-07-06 | Matsushita Electronics Corp | Semiconductor device having an alloy electrode and its manufacturing method |
| JPS512997A (en) * | 1974-06-27 | 1976-01-12 | Copal Co Ltd | KUMAKUKAHENTEITEIKOSOSHINO SEIZOHOHO |
| EP0335383A2 (en) * | 1988-03-30 | 1989-10-04 | Hitachi, Ltd. | Semiconductor device having a metallization film layer |
| EP0499050A1 (en) * | 1991-02-13 | 1992-08-19 | International Business Machines Corporation | Method for depositing interconnection metallurgy using low temperature alloy processes |
| EP0601509A1 (en) * | 1992-12-07 | 1994-06-15 | Nikko Kyodo Co., Ltd. | Semiconductor devices and method of manufacturing the same |
Non-Patent Citations (3)
| Title |
|---|
| C.A.HEWETT ET AL.: "Oxidation behavior of Au-Si films", APPLIED PHYSICS LETTERS, vol. 50, no. 13, 30 March 1987 (1987-03-30), NEW YORK US, pages 827 - 829, XP000197237 * |
| DATABASE WPI Section Ch Week 7609, Derwent World Patents Index; Class L03, AN 76-15399x, XP002032631 * |
| G.BEENSH-MARCHWICKA ET AL.: "Aging mechanisms in thin film Cr, CrAu and TiNx resistors", THIN SOLID FILMS, vol. 36, no. 2, 2 August 1976 (1976-08-02), SWITZERLAND, pages 361 - 363, XP000673822 * |
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