WO1997024756A1 - Procede de fabrication d'un transistor bipolaire vertical a hyperfrequences sur un soi a conducteur metallique a base enterree - Google Patents

Procede de fabrication d'un transistor bipolaire vertical a hyperfrequences sur un soi a conducteur metallique a base enterree Download PDF

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Publication number
WO1997024756A1
WO1997024756A1 PCT/IB1996/001392 IB9601392W WO9724756A1 WO 1997024756 A1 WO1997024756 A1 WO 1997024756A1 IB 9601392 W IB9601392 W IB 9601392W WO 9724756 A1 WO9724756 A1 WO 9724756A1
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WO
WIPO (PCT)
Prior art keywords
layer
emitter
base
forming
oxide
Prior art date
Application number
PCT/IB1996/001392
Other languages
English (en)
Inventor
Manjin J. Kim
Original Assignee
Philips Electronics N.V.
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics N.V., Philips Norden Ab filed Critical Philips Electronics N.V.
Priority to JP9524142A priority Critical patent/JPH11501464A/ja
Priority to EP96939269A priority patent/EP0812469A1/fr
Publication of WO1997024756A1 publication Critical patent/WO1997024756A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors

Definitions

  • the present invention is directed to a method of making a microwave, vertical bipolar transistor on an SOI where there is a buried metal conductor.
  • the method of the present invention uses oxide spacer widths and diffusion to provide critical dimension in the device without using lithography.
  • the present invention offers a method of making vertical bipolar transistors on an SOI in which critical dimensions in the device can be controlled by a different technique. Namely, the use of oxide spacers and controlled diffusion enables the formation of such devices without using lithographic techniques, such as used in applicant's corresponding application (see Serial No. 08/579,703), filed on the same date as this application.
  • the device is made according to the present invention by the steps of forming an SOI wafer of n and n-l- layers of silicon on an insulating layer on a substrate, implanting an n-l- collector through the n layer of silicon into the n+ layer of silicon, forming a p type base within an active region at the surface of the n layer, forming an n + polysilicon emitter on the p type base within the active region, providing oxide spacers about the emitter for a distance, forming p+ base contacts and contact metalization to the base spaced from the emitter by the oxide spacers, depositing a planar dielectric layer over the formed structure, and providing conductive contacts to the collector and the emitter through the planar dielectric layer.
  • suicide contacts are formed over the emitter and the p+ base contacts before the contact metalization is made. This improves conductivity of the emitter and the base, and may be formed by any metal suicide. Such metal suicide may be formed by a metal film deposition followed by a subsequent sintering. Cobalt suicide is preferred since it has a high conductivity and a low probability of forming a bridge across the oxide spacer.
  • the contact metalization is provided by using a double layer refractory metal.
  • a double layer would preferably include a TiW layer with a stacked layer of Mo thereover.
  • the TiW layer provides a good adhesion with the oxide spacers, and forms a good ohmic contact with the p+ base contact layer or the suicide.
  • the high conductivity molybdenum provides a stable contact with the TiW layer at high temperatures.
  • Figure 1 shows the vertical bipolar SOI device according to the present invention
  • FIGS 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12 show in sequence the process for making the device of Figure 1.
  • the self-aligned vertical bipolar transistor on an SOI wafer is shown in Figure 1.
  • the SOI wafer is formed by the substrate 1 on which an isolation or buried oxide 2 is disposed. Over this oxide 2 is a semiconductor layer, being in this case an n+ layer 3 provided on the oxide layer 2 and an n layer 4.
  • the n+ layer 3 under the n layer 4 has a high conductivity so that it will provide a low loss collector.
  • the substrate 1 may be a silicon layer and the layers 3 and 4 may also be silicon, while the oxide layer may be SiO 2 .
  • an n-l- collector region 6 is provided through the n layer 4 between oxide regions 5 which are buried into the n layer 4. Beside this collector region is provided a base region and emitter region between one of the buried oxide regions 5 and a further buried oxide region 5, according to the present invention.
  • the base region includes a base 7, base contact regions 9 and base contact metalization 15 provided in contact with a silicide 10.
  • the emitter region 8 is provided over the base region 8 with an n type emitter junction 12.
  • a silicide layer 10 is also disposed on the emitter 8 which is surrounded by oxide spacers 11 which are given dimensions to control the distance between the emitter 8 and the base contact regions 9.
  • LTO low temperature oxide
  • the contact metalization 15 to the base runs beneath the surface of the device to an edge of the device to make electrical connection.
  • the SOI wafer is formed, as shown in Figure 2, with the n+ layer 3 provided on the isolated oxide layer 2 on the substrate 1 of silicon, for example.
  • the silicon layer 4 is etched to eventually provide recessed oxide layers 5 which will define an active area 30, and a second area 31 in which a collector will be formed.
  • a nitride such as silicon nitride
  • RIE reactive ion etch
  • the etch stops at the surface of the silicon layer 4 etching in this case is carried on to below the silicon surface by using a different RIE chemistry.
  • the depth of the recessed etching is about half of the silicon thickness, which generates a smooth surface, as shown in Figure 3.
  • an oxide planarization instead of the recessed LOCOS could also produce a similar result.
  • the n+ collector 6 is produced in Figure 4 by a selective implantation to drive dopant down to the n+ layer 3.
  • dopant As an example, phosphorus is used for a fast diffusion to save thermal effort. Some of the dopant laterally diffuses under the recessed LOCOS oxide 5.
  • p type dopant is selectively implanted into the active area 30 to form the p type base 7.
  • This implantation is carried out with a doping concentration for the p type base that is higher than the doping for the n+ collector 6. But the doping concentration should be low enough for high injection efficiency.
  • the p dopant can be diffused into or just activated to eliminate defects generated by implantation that would cause a subsequent abnormal diffusion during emitter formation from a n-f- type poly emitter layer.
  • a heavily doped n-t- poly semiconductive layer is deposited and an emitter
  • Oxide spacers 11 are formed at the steps of the emitter 8 from the base, as seen in Figure 7. This may be achieved by a deposition of LTO followed by an anisotropic RIE etching. The width of the spacers 1 1 are determined by the oxide thickness.
  • a self- aligned implantation is carried out to form p+ type conductivity base contacts 9.
  • the most critical dimension which is the distance between the emitter 8 and the p+ base contacts 9, is not determined by a photolithographic technique, but by the width of the spacers 1 1.
  • the recessed oxide layers 5, the poly emitter 8 and the spacers 1 1 form a mask for implanting ions into the p+ base contact areas, so that a photoresist mask is not needed according to the present invention.
  • the n type dopant in the n-t- poly doped emitter 8 is also diffused into the p base 8 to form a buried emitter junction 12.
  • a silicide 10 is formed over the p-f- base contact 9 and the n-f poly emitter 8, as seen in Figure 9, to improve the conductivity of the poly emitter and the base.
  • Any metal silicide may be formed with a first metal film deposition and subsequent sintering.
  • a metal silicide of cobalt is preferred because of its high conductivity and low probability for forming a bridge across the spacers 1 1. The formation of this metal silicide may be an option in the process of the present invention.
  • Metalization to the base contacts 9 is preferably provided by a double layer refractory metal.
  • a thin layer 13 of TiW is first deposited and a layer of molybdenum 14 is formed thereon, as may be seen in Figure 10.
  • the layer 13 may be about lOOOA thick and have about 10 to 20 weight percent of Ti in tungsten.
  • the molybdenum layer 14 may be about 2000A to 5000A in thickness.
  • This metalization 13, 14 may be partially formed by lithographic and RIE etching processes over the exposed p+ base contacts 9
  • the TiW metalization not only provides a good adhesion to the buried oxide regions 5 but also forms a good ohmic contact with the p+ base contact 9 or silicide 10.
  • the high conductivity refractory molybdenum region 14 and the TiW region 13 provides a stable contact at a high temperature without causing electric spiking in operation.
  • a thick mterlevel dielectric layer 16 is deposited and piana ⁇ zed, as seen in Figure 1 1 , to produce a smooth surface.
  • a LTO may be used and plana ⁇ zed by using a photoresist of a low viscosity mate ⁇ al and/or reflowmg it over the surface. By selecting a RIE chemistry of an equal etch rate for both the resist and the LTO, the LTO hills may be leveled.
  • the emitter and collector contacts 17 are formed by opening areas 20 and 21, respectively, over the emitter 8 and collector 6. This may be done by conventional lithography.
  • a disadvantage of the plana ⁇ zation step is a reduction of the LTO thickness on top of the emitter, leading to a variation in the contact depth.
  • the plana ⁇ zed surface may be produced by a high resolution lithography so that it is possible to align the contact to the emitter which acts as an etch stop.
  • the metalization areas 17 may be formed by aluminum and alloyed to form ohmic contacts to the emitter and collector.
  • the base contact metalization 15 may be extended to the edge or end of the device where a highly conductive metal contact may be provided.
  • Such device isolation is not shown but may be easily formed by a trench etching through the thin SOI film.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

La présente invention se rapporte à un procédé de fabrication d'un transistor bipolaire, vertical, à hyperfréquences sur un dispositif SOI (silicium sur isolant) dans lequel on utilise des séparateurs à couche d'oxyde pour fabriquer la structure sans avoir à déposer plusieurs couches. Des régions oxydes enterrées sont utilisées pour former des régions de base, les émetteurs étant formés sur les régions de base et les séparateurs à couche d'oxyde entourant les émetteurs. Les séparateurs à couche d'oxyde empêchent le contact électrique entre les régions de base et l'émetteur.
PCT/IB1996/001392 1995-12-28 1996-12-09 Procede de fabrication d'un transistor bipolaire vertical a hyperfrequences sur un soi a conducteur metallique a base enterree WO1997024756A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP9524142A JPH11501464A (ja) 1995-12-28 1996-12-09 埋込ベース金属導体を有するｓｏｉ上にマイクロ波バーチカルバイポーラトランジスタを製造する方法
EP96939269A EP0812469A1 (fr) 1995-12-28 1996-12-09 Procede de fabrication d'un transistor bipolaire vertical a hyperfrequences sur un soi a conducteur metallique a base enterree

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57970295A 1995-12-28 1995-12-28
US08/579,702 1995-12-28

Publications (1)

Publication Number Publication Date
WO1997024756A1 true WO1997024756A1 (fr) 1997-07-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1996/001392 WO1997024756A1 (fr) 1995-12-28 1996-12-09 Procede de fabrication d'un transistor bipolaire vertical a hyperfrequences sur un soi a conducteur metallique a base enterree

Country Status (3)

Country Link
EP (1) EP0812469A1 (fr)
JP (1) JPH11501464A (fr)
WO (1) WO1997024756A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19842106A1 (de) * 1998-09-08 2000-03-09 Inst Halbleiterphysik Gmbh Vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
WO2002078061A2 (fr) * 2001-03-23 2002-10-03 Honeywell International Inc. Oxydation de silicium en retrait destine a des dispositifs tels qu'un cmos soi a microcircuits integres

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682409A (en) * 1985-06-21 1987-07-28 Advanced Micro Devices, Inc. Fast bipolar transistor for integrated circuit structure and method for forming same
EP0590804A1 (fr) * 1992-09-03 1994-04-06 STMicroelectronics, Inc. Transistor bipolaire monolithique à haute puissance verticalement isolé avec un collecteur de dessus
US5312765A (en) * 1991-06-28 1994-05-17 Hughes Aircraft Company Method of fabricating three dimensional gallium arsenide microelectronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682409A (en) * 1985-06-21 1987-07-28 Advanced Micro Devices, Inc. Fast bipolar transistor for integrated circuit structure and method for forming same
US5312765A (en) * 1991-06-28 1994-05-17 Hughes Aircraft Company Method of fabricating three dimensional gallium arsenide microelectronic device
EP0590804A1 (fr) * 1992-09-03 1994-04-06 STMicroelectronics, Inc. Transistor bipolaire monolithique à haute puissance verticalement isolé avec un collecteur de dessus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CONFERENCE PROCEEDINGS 19TH EUROPEAN MICROWAVE CONFERENCE, Sept. 1989, KEIICHI OHATA, "Microwave Heterojunction Devices", pages 136-146. *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19842106A1 (de) * 1998-09-08 2000-03-09 Inst Halbleiterphysik Gmbh Vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
US6627972B1 (en) 1998-09-08 2003-09-30 Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh Vertical bipolar transistor
WO2002078061A2 (fr) * 2001-03-23 2002-10-03 Honeywell International Inc. Oxydation de silicium en retrait destine a des dispositifs tels qu'un cmos soi a microcircuits integres
WO2002078061A3 (fr) * 2001-03-23 2002-12-19 Honeywell Int Inc Oxydation de silicium en retrait destine a des dispositifs tels qu'un cmos soi a microcircuits integres

Also Published As

Publication number Publication date
EP0812469A1 (fr) 1997-12-17
JPH11501464A (ja) 1999-02-02

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