WO1997022993A1 - Electronic package with spacer means - Google Patents
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- WO1997022993A1 WO1997022993A1 PCT/EP1995/004972 EP9504972W WO9722993A1 WO 1997022993 A1 WO1997022993 A1 WO 1997022993A1 EP 9504972 W EP9504972 W EP 9504972W WO 9722993 A1 WO9722993 A1 WO 9722993A1
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- cte
- substrate
- die device
- electronic package
- glue
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions
- the present invention relates to an electronic package and particularly, but not exclusively, to an electronic package including at least one die device having a first CTE (Coefficient of Thermal Expansion) and a substrate having a second CTE, said die device being attached to said substrate by means of an intermediate layer including an attach material having a third CTE greater than the lower between said first and said second CTE.
- an attach material such as a glue
- BGA Ball Grid Array
- BGA packages or modules are a quite recent development in the electronic packaging industry replacing the current products as the Quad Flat Packs (QFP).
- the main difference is the connection system to the printed circuit board (PCB), also called second level attachment, that is made through eutectic Tin Lead alloy balls arranged in a matrix lay-out on the bottom side of a substrate, instead of metal leads placed along the peripheral edge of the plastic component body.
- PCB printed circuit board
- One or more die devices arc then attached on the top side of the substrate by means of a glue layer.
- BGA and QFP packages are described in "Circuits Assembly (USA) - Vol.6, No.3 March 1995 Pag.38-40".
- a problem in these electronic packages is due to the difference of the Coefficient of Thermal Expansion (CTE) of the substrate and the die device.
- CTE Coefficient of Thermal Expansion
- the difference of the Coefficient of Thermal Expansion creates regions where strains are resulting from the presence of a first stiffener material that reduces the normal expendability of the second material.
- This problem is particular serious in BGA packages, where these strains are acting on the balls connecting the module to the Printed Circuit Board, causing these balls connections starting to fracture for fatigue, particularly after thermal power-on/power-off cycling. All the eutectic balls included in corresponding area of the attached die to the substrate have cracks, exposing the BGA package to reliability problems. The driver for these cracks is the different Coefficient of Thermal Expansion of the die device that is lower than the substrate.
- the solution known in the art for relieving the stiffness driven by the attached die device to the substrate is that of using a thick layer of solder mask to create a cushion effect between the die device rigidity and the substrate expendability.
- This solution involves the use of a special solder mask (dry films) in order to increase the thickness of the protective material layer on the module substrate top side; the die device is then attached to a layer of this insulating material.
- This solution proved to work at a relatively low cost; the working thicknesses are achievable with some materials and related processes only, but once they are implemented no further special precautions/process steps are required.
- a drawback with this prior art is the lower capability of thermal dissipation of the package, because heat can be dissipated through the module substrate core only.
- the insulating material layer thickness reduces the number of the possible applications.
- a different solution would be to increase the thickness of the attach material that has a compatible CTE with the substrate material; this material may have elastic properties, being also thermally conductive.
- the difficulty of this approach is due to the fact that the attach material has a medium low viscosity, so that the die can easily float above the glue dot or sink in it causing a scrap part.
- the present invention provides an electronic package as set out above which i ⁇ characterized in that said intermediate layer further includes spacer means for spacing said die device form said substrate.
- spacer ⁇ mean ⁇ are not collap ⁇ ible inclu ⁇ ion within the attach material, stopping the die device sinking in it and automatically ⁇ etting the required stand-off of die attach material between the die device and the substrate, providing a high thick attach material layer.
- This attach material layer provides a cushion effect between the die device and the substrate; the present invention allows then obtaining strain relieved packages in the die attach area, with the result of avoiding fatigue failures.
- the proposed invention i ⁇ fully compatible with the existing materials and does not affect their physical and chemical properties. It is a low cost and of an extremely easy implementation. In addition, this technique guarantee a silicon chip planarity with better yield in automatic bonding operation reducing the silicon tilt yield detractor.
- the solution according to the present invention may be applied both when the ⁇ ubstrate is more rigid that the device and on the contrary when the ⁇ ubsrrate material has a CTE lower that the CTE of the die device material.
- said first CTE is lower than said second CTE.
- the substrate materials commonlv used in fact are rigid, having a high CTE, such as plastic material, fiberglass laminate, epoxy reinforced woven fiberglass laminate, ceramic, polyimide, alumina.
- the die device is typically realized with a material having a lower CTE, for example Silicon, Germanium or Gallium Arsenide.
- said attach material is a glue, such as a thermoplastic glue, a termoset glue or a mix of thermoplastic and termoset materials; typically, the glue is an epoxy glue, generally loaded with Silver particles for a better heat dissipation.
- said spacer means have a fourth CTE not greater than said third CTE.
- said spacer means are made of glass or corundum.
- the glass is useful in the case the CTE has to be driven by the compatibility with the composite laminate fiberglass material; the corundum is preferred in the case the CTE has to be the closest possible to the Silicon or Alumina CTE.
- the volume of said spacer means is not more that the 30% of the volume of said intermediate layer.
- This quantity of included spacer means does not affect the functionality of the attach material in its performances as adhesion, heat transfer and electrical conductivity.
- spacer means may be used according to the pre ⁇ ent invention, such as rods, cubes; in an advantageous embodiment, said spacer means include at least three spheres.
- These spheres may be easily mixed to the attach material and does not have any problem in the dispensing of the same attach material onto the substrate; in addition, they have a very low cost being commonly used for sandbla ⁇ ting operation ⁇ .
- the number of three spheres per dispensed attach material spot 1 s in addition useful for determining a sitting plane for the die device.
- These balls can be mixed or added to the die attach glue with a predetermined diameter based on the targeted glue thickness.
- said sphere ⁇ have a diameter comprised between 20 ⁇ m and 130 ⁇ m.
- said electronic package i ⁇ a BGA.
- the application of this solution to a BGA package allows obtaining strain relieved BGA in the die attach area, with the result of avoiding fatigue failures at second level connection joints. All the balls placed underneath the die attach area are then available, increasing the Input/Output capability of the electronic package and allowing production of smaller BGA.
- the pre ⁇ ent invention also provides a method of manufacturing an electronic package including a die device having a fir ⁇ t CTE (Coefficient of Thermal Expan ⁇ ion) and a ⁇ ubstrate having a second CTE, said method including the step ⁇ of di ⁇ pensing an attach material onto said substrate, said attach material having a third CTE greater than the lower between said first and said second CTE, attaching said die device to said substrate by means of said attach material, characterized by the step of mixing spacer means into said attach material for spacing said die device form said substrate.
- fir ⁇ t CTE Coefficient of Thermal Expan ⁇ ion
- ⁇ ubstrate having a second CTE
- the packaging method according to the present invention does not require any additional step of forming a dry film onto the substrate; in addition, it is fully compatible with the current processes and related equipment used in the industry.
- said step of mixing is performed before said step of dispensing. This embodiment it is low cost and does not require any additional equipment for placing the spacer means in the attach material after dispensing.
- Fig. 1 is an electronic package according to rhe prior art
- Fig. 2 depicts an electronic package according to an embodiment of the present invention
- Fig. 3 shows the high thick glue layer used in an embodiment of the present invention.
- FIG. 1 a cross-sectional view of an electronic package according to the prioi art is shown.
- the figure depicts in particular a BGA 100 including a die device 110 attached to a substrate 120.
- the substrate 120 is provided on its bottom side with a plurality of connecting balls or bumps 142, 144 arranged in a matrix lay-out; the connecting balls 142, 144 are typically eutectic solder, such as Tin Lead alloy.
- These balls 142, 144 are used to connect the BGA package to a Printed Circuit Board (not shown).
- BGA ⁇ uch a ⁇ Plastic Ball Grid Array
- CBGA Ceramic Ball Grid Array
- TBGA Tape Ball Grid Array
- This substrate 120 is generally fairly thin, in the order of 0.3 - 0.7 mm; this values increase the problem involved by the difference in the CTE of the die device 110 and the substrate 120.
- a thick layer of solder mask (dry film) 150 is provided in order to increase the thickness of the protective material layer on the module substrate 120 top side, creating a cushion effect between the die device 110 rigidity and the substrate 120 expansivity.
- the die device 110 is then attached to a layer of thi ⁇ in ⁇ ulating material 150 by means of the glue 130.
- the device 110 is wired to the electrical circuit on the substrate 120 by means of wires 160, through a thermo-sonic wire bonding operation and the assembly is then molded with a plastic re ⁇ in 170.
- FIG.2 a cro ⁇ - ⁇ ectional view of an electronic package according to an embodiment of the pre ⁇ ent invention is shown.
- the figure depicts a BGA 200, wherein the die device 110 is attached to the substrate 120.
- the substrate 120 is realized with different materials, such as plastic material, fiberglass laminate, epoxy reinforced woven fiberglass laminate, ceramic, polyimide, alumina.
- the substrate materials commonly used are rigid, having a high Coefficient of Thermal Expansion, with a value typically between 14 ppm and 25 ppm.
- the die device 110 such as a chip or an active device, is typically realized with a material having a lower CTE; typically, such die 110 is made of Silicon,
- Germanium or Gallium Arsenide with a CTE usually comprised between 2.5 ppm to 5 ppm.
- the die device 110 is attached to the substrate 120 by means of a high thick attach material layer 210, providing a predetermined mechanical stand-off between the die device 110 and the substrate 120.
- the attach material has a low viscosity, commonly comprised between 500 and 50.000 cps at 25°C; typically, the attach material i ⁇ a glue, such as a thermoplastic glue, a termoset glue or a mix of thermoplastic and termoset materials; preferably, the glue is an epoxy glue, generally loaded with Silver particles for a better heat dissipation.
- the attach material 210 has a CTE that is greater than the CTE of the die device, thereby providing a cushion effect between the die device 110 rigidity and the substrate 120 expansivity.
- the present invention allows then obtaining strain relieved BGA packages in the die attach area, with the result of avoiding fatigue failures at second level connection joints. All the balls 142 and 144, including the balls 144 placed underneath the die attach area, are then available, increasing the Input/Output capability of the electronic package and allowing production of smaller BGA.
- Fig. 3 shows in detail the high thick attach material layer used in an embodiment of the present invention.
- the controlled ⁇ tand-off of the attach material 210 between the die device 110 and the substrate 120 is obtained by means of a plurality of spacer means 310. These spacers are not collapsible inclu ⁇ ion within the glue 210, stopping the die device sinking in the glue and automatically setting the required stand-off of die attach material.
- spacers 310 may be used according to the present invention, such a rods, cubes; in an advantageous embodiment, these spacers 310 are small spheres. These spheres may be easily mixed to the attach material and does not have any problem in the dispensing of this glue onto the substrate; in addition, they have a very low cost being commonly used for sandblasting operations and they are available commercially in several diameters. These balls can be mixed or added to the die attach glue with a predetermined diameter based on the targeted glue thickness. Tested spheres diameters were in the range from 30 ⁇ to 130 ⁇ using commercially available die attach glues.
- a minimum number of spacers 310 are necessary, that is two rods or three cubes or ⁇ phere ⁇ .
- the mixing operation has to statistically guarantee that at least three spheres are present per dispensed glue spot.
- the possible quantity of included spheres without affecting the functionality of the glue material in its performances as adhesion, heat transfer, electrical conductivity, goes from three to a very high number up to representing the 30% of the total volume of the attach material (including the spacer means) between the silicon device and the die pad on the substrate.
- the spacers 310 may be realized with different materials.
- the spacers 310 have a CTE not greater than the CTE of the glue material; this embodiment of the invention reduces the risk of any detachment of the die device from the sub ⁇ trate, due to the expan ⁇ ivity of the spacer ⁇ .
- the spacers 310 are made of glas ⁇ ( Si02) in the case the CTE has to be driven by the compatibility with the composite laminate fiberglass material or corundum (A1203) in the case the CTE has to be the closest Oossible to the Silicon or Alumina CTE.
- the proposed invention is ful v compatible with the existing materials and does not affect their physical and chemical properties. It is a low cost and of an extremely easy implementation. In addition, this technique guarantee a silicon chip planarity with better yield in automatic bonding operation reducing the silicon tilt yield detractor.
- BGA odule ⁇ are commonly manufactured ⁇ tarting from the ⁇ ub ⁇ trate 120, ⁇ uch a ⁇ an epoxy reinforced woven fiberglass laminate core structure.
- the glue 210 typically epoxy glue loaded with Silver particles i ⁇ dispensed onto the sub ⁇ trate 120 top ⁇ ide, typically in dots or according to a cross form.
- the spacer ⁇ typically epoxy glue loaded with Silver particles i ⁇ dispensed onto the sub ⁇ trate 120 top ⁇ ide, typically in dots or according to a cross form.
- the ⁇ e spacers 310 are mixed to the glue 210, either before or after di ⁇ pen ⁇ ing.
- the ⁇ e spacers 310 are mixed to the glue 210 before the step of dispensing the glue 210 onto the substrate 120; this embodiment it is low cost and does not require any additional equipment for placing the spacers 310 in the glue 210.
- These spacers 310 are not collapsible inclusion within the glue 310, so that the die device 110, placed either manually or by a machine, is a flat surface that will soon meet the balls in the glue, stopping its sinking in the resin and automatically setting the required die attach material stand-off .
- the device 110 is then wired to electrical circuit on the sub ⁇ trate and molded with a plastic resin as in the prior art process. It should be noted that the process according to the present invention does not require any additional step of forming a dry film onto the substrate.
Abstract
An electronic package, particularly a BGA, including a die device (110) attached to a substrate (120) by means of an attach material (210), commonly a glue. This glue layer (210) includes spacer means (310) providing a high thick glue layer setting a required stand-off between the die device (110) and the substrate (120). These spacer means are preferably small spheres made of glass or corundum, with a diameter comprised between 20νm and 130νm. At least three spheres are required for determining a sitting plane for the die device (110); the possible quantity of included spacer means (310), without affecting the functionality of the glue material in its performances as adhesion, heat transfer, electrical conductivity, is up to the 30 % of the total volume of the attach material (210) between the die device (110) and the substrate (120).
Description
ELECTRONIC PACKAGE WITH SPACER MEANS
The present invention relates to an electronic package and particularly, but not exclusively, to an electronic package including at least one die device having a first CTE (Coefficient of Thermal Expansion) and a substrate having a second CTE, said die device being attached to said substrate by means of an intermediate layer including an attach material having a third CTE greater than the lower between said first and said second CTE. The use of an attach material, such as a glue, is common in electronic packaging applications for attaching die devices or components to a substrate, particularly in Ball Grid Array (BGA) packages.
BGA packages or modules are a quite recent development in the electronic packaging industry replacing the current products as the Quad Flat Packs (QFP). The main difference is the connection system to the printed circuit board (PCB), also called second level attachment, that is made through eutectic Tin Lead alloy balls arranged in a matrix lay-out on the bottom side of a substrate, instead of metal leads placed along the peripheral edge of the plastic component body. One or more die devices arc then attached on the top side of the substrate by means of a glue layer. BGA and QFP packages are described in "Circuits Assembly (USA) - Vol.6, No.3 March 1995 Pag.38-40".
A problem in these electronic packages is due to the difference of the Coefficient of Thermal Expansion (CTE) of the substrate and the die device. The difference of the Coefficient of Thermal Expansion creates regions where strains are resulting from the presence of a first stiffener material that reduces the normal expendability of the second material. This problem is particular serious in BGA packages, where these strains are acting on the balls connecting the module to the Printed Circuit Board, causing these balls connections starting to fracture for fatigue, particularly after thermal power-on/power-off cycling. All the eutectic balls included
in corresponding area of the attached die to the substrate have cracks, exposing the BGA package to reliability problems. The driver for these cracks is the different Coefficient of Thermal Expansion of the die device that is lower than the substrate. The result of this expendability mismatch iε a localized stiffness of the substrate that is not allowed to expand as it would without the die presence. When this module is attached to a printed circuit mother board, that is also made with epoxy woven fiberglass laminate, the module and the board should be in an ideal situation and should expand at the very same range of CTE values : unfortunately in the module area underneath the die device the substrate material behaves with a different CTE. All the balls connections within this area are then exposed to a strain driven by the unequal material expansion factors where the balls two ends are attached to. All the balls placed underneath the die attach area ended up with their fracture for fatigue with a resulting reliability exposure for the user or driving the non utilization of those module Input/Outputs. The solution known in the art for relieving the stiffness driven by the attached die device to the substrate is that of using a thick layer of solder mask to create a cushion effect between the die device rigidity and the substrate expendability. This solution involves the use of a special solder mask (dry films) in order to increase the thickness of the protective material layer on the module substrate top side; the die device is then attached to a layer of this insulating material. This solution proved to work at a relatively low cost; the working thicknesses are achievable with some materials and related processes only, but once they are implemented no further special precautions/process steps are required.
A drawback with this prior art is the lower capability of thermal dissipation of the package, because heat can be dissipated through the module substrate core only. In addition, the insulating material layer thickness reduces the number of the possible applications.
In order to avoid the previously mentioned heat transfer problems, instead of having a thick layer of insulating extra material, a different solution would be to increase the thickness of the attach material that has a compatible CTE with the substrate material; this material may have elastic properties, being also thermally conductive. The difficulty of this approach is due to the fact that the attach material has a medium low viscosity, so that the die can easily float above the glue dot or sink in it causing a scrap part. A solution would require the usage of Computer Numeric Controlled (CNC machines capable of placing the die on a theoretical plane within the glue dot; unfortunately either the substrate and the die device thicknesses have wide tolerances making the resulting glue thickness very theoretical. The same result would be achieved with a cheaper machine working with a positive mechanical stop, the variability of the two thicknesses will affect the final results. Either equipment supported soϋutions do not guarantee that the planned stand off is not affected by the polymerization process of the glue resin. In addition, they involve a high cost versus the resulting low process control and the high impact on the product price, well above the target for this low cost electronic package.
The above drawbacks of the prior art are overcome by the invention as claimed. Accordingly, the present invention provides an electronic package as set out above which iε characterized in that said intermediate layer further includes spacer means for spacing said die device form said substrate.
These spacerε meanε are not collapεible incluεion within the attach material, stopping the die device sinking in it and automatically εetting the required stand-off of die attach material between the die device and the substrate, providing a high thick attach material layer.
This attach material layer provides a cushion effect between the die device and the substrate; the present invention allows then obtaining strain relieved packages in the die attach area, with the result of avoiding fatigue
failures.
It should be noted that the proposed invention iε fully compatible with the existing materials and does not affect their physical and chemical properties. It is a low cost and of an extremely easy implementation. In addition, this technique guarantee a silicon chip planarity with better yield in automatic bonding operation reducing the silicon tilt yield detractor.
The solution according to the present invention may be applied both when the εubstrate is more rigid that the device and on the contrary when the εubsrrate material has a CTE lower that the CTE of the die device material.
Typically, said first CTE is lower than said second CTE. The substrate materials commonlv used in fact are rigid, having a high CTE, such as plastic material, fiberglass laminate, epoxy reinforced woven fiberglass laminate, ceramic, polyimide, alumina. On the contrary, the die device is typically realized with a material having a lower CTE, for example Silicon, Germanium or Gallium Arsenide. In a particular embodiment of the present invention, said attach material is a glue, such as a thermoplastic glue, a termoset glue or a mix of thermoplastic and termoset materials; typically, the glue is an epoxy glue, generally loaded with Silver particles for a better heat dissipation. Advantageously, said spacer means have a fourth CTE not greater than said third CTE.
This feature reduces the risk of any detachment of the die device from the substrate, due to the expendability of the spacers. Particularly, said spacer means are made of glass or corundum.
The glass is useful in the case the CTE has to be driven by the compatibility with the composite laminate fiberglass material; the corundum is preferred in the case the CTE has to be the closest possible to the Silicon or Alumina CTE.
Advantageously, the volume of said spacer means is not more that the 30% of the volume of said intermediate layer.
This quantity of included spacer means does not affect the functionality of the attach material in its performances as adhesion, heat transfer and electrical conductivity.
Different types of spacer means may be used according to the preεent invention, such as rods, cubes; in an advantageous embodiment, said spacer means include at least three spheres.
These spheres may be easily mixed to the attach material and does not have any problem in the dispensing of the same attach material onto the substrate; in addition, they have a very low cost being commonly used for sandblaεting operationε. The number of three spheres per dispensed attach material spot 1 s in addition useful for determining a sitting plane for the die device.
These balls can be mixed or added to the die attach glue with a predetermined diameter based on the targeted glue thickness. Typically, said sphereε have a diameter comprised between 20μm and 130μm.
In a particular advantageouε embodiment of the present invention, said electronic package iε a BGA. The application of this solution to a BGA package allows obtaining strain relieved BGA in the die attach area, with the result of avoiding fatigue failures at second level connection joints. All the balls placed underneath the die attach area are then available, increasing the Input/Output capability of the electronic package and allowing production of smaller BGA.
The preεent invention also provides a method of manufacturing an electronic package including a die device having a firεt CTE (Coefficient of Thermal Expanεion) and a εubstrate having a second CTE, said method including the stepε of diεpensing an attach material onto said substrate, said attach material having a third CTE greater than the lower between said first and said second CTE, attaching said die device to said substrate by means of said attach material, characterized by the step of mixing spacer means into said attach material for spacing said die device form said substrate.
The packaging method according to the present invention
does not require any additional step of forming a dry film onto the substrate; in addition, it is fully compatible with the current processes and related equipment used in the industry. Advantageously, said step of mixing is performed before said step of dispensing. This embodiment it is low cost and does not require any additional equipment for placing the spacer means in the attach material after dispensing.
Various embodiments of the invention will now be described in detail by way of examples, with reference to accompanying figures, where:
Fig. 1 is an electronic package according to rhe prior art;
Fig. 2 depicts an electronic package according to an embodiment of the present invention;
Fig. 3 shows the high thick glue layer used in an embodiment of the present invention.
With reference now to the figures and in particular with reference to Fig.1, a cross-sectional view of an electronic package according to the prioi art is shown. The figure depicts in particular a BGA 100 including a die device 110 attached to a substrate 120. The substrate 120 is provided on its bottom side with a plurality of connecting balls or bumps 142, 144 arranged in a matrix lay-out; the connecting balls 142, 144 are typically eutectic solder, such as Tin Lead alloy. These balls 142, 144 are used to connect the BGA package to a Printed Circuit Board (not shown). Different types of BGA are available, εuch aε Plastic Ball Grid Array (PBGA), Ceramic Ball Grid Array (CBGA) and Tape Ball Grid Array (TBGA), the primary difference being the type of εubstrate material. This substrate 120 is generally fairly thin, in the order of 0.3 - 0.7 mm; this values increase the problem involved by the difference in the CTE of the die device 110 and the substrate 120. A thick layer of solder mask (dry film) 150 is provided in order to increase the thickness of the protective material layer on the module substrate 120 top side, creating a cushion
effect between the die device 110 rigidity and the substrate 120 expansivity.
The die device 110 is then attached to a layer of thiε inεulating material 150 by means of the glue 130. The device 110 is wired to the electrical circuit on the substrate 120 by means of wires 160, through a thermo-sonic wire bonding operation and the assembly is then molded with a plastic reεin 170.
With reference now to Fig.2, a croεε-εectional view of an electronic package according to an embodiment of the preεent invention is shown. The figure depicts a BGA 200, wherein the die device 110 is attached to the substrate 120.
The substrate 120 is realized with different materials, such as plastic material, fiberglass laminate, epoxy reinforced woven fiberglass laminate, ceramic, polyimide, alumina. The substrate materials commonly used are rigid, having a high Coefficient of Thermal Expansion, with a value typically between 14 ppm and 25 ppm.
On the contrary, the die device 110, such as a chip or an active device, is typically realized with a material having a lower CTE; typically, such die 110 is made of Silicon,
Germanium or Gallium Arsenide, with a CTE usually comprised between 2.5 ppm to 5 ppm.
In the depicted embodiment of the present invention, the die device 110 is attached to the substrate 120 by means of a high thick attach material layer 210, providing a predetermined mechanical stand-off between the die device 110 and the substrate 120. The attach material has a low viscosity, commonly comprised between 500 and 50.000 cps at 25°C; typically, the attach material iε a glue, such as a thermoplastic glue, a termoset glue or a mix of thermoplastic and termoset materials; preferably, the glue is an epoxy glue, generally loaded with Silver particles for a better heat dissipation. The attach material 210 has a CTE that is greater than the CTE of the die device, thereby providing a cushion effect between the die device 110 rigidity and the substrate 120 expansivity. The present invention allows then
obtaining strain relieved BGA packages in the die attach area, with the result of avoiding fatigue failures at second level connection joints. All the balls 142 and 144, including the balls 144 placed underneath the die attach area, are then available, increasing the Input/Output capability of the electronic package and allowing production of smaller BGA. Those skilled in the art will appreciate that this solution is applicable even if the CTE of the die device iε greater than the CTE of the substrate. Fig. 3 shows in detail the high thick attach material layer used in an embodiment of the present invention. The controlled εtand-off of the attach material 210 between the die device 110 and the substrate 120 is obtained by means of a plurality of spacer means 310. These spacers are not collapsible incluεion within the glue 210, stopping the die device sinking in the glue and automatically setting the required stand-off of die attach material.
Different types of spacers 310 may be used according to the present invention, such a rods, cubes; in an advantageous embodiment, these spacers 310 are small spheres. These spheres may be easily mixed to the attach material and does not have any problem in the dispensing of this glue onto the substrate; in addition, they have a very low cost being commonly used for sandblasting operations and they are available commercially in several diameters. These balls can be mixed or added to the die attach glue with a predetermined diameter based on the targeted glue thickness. Tested spheres diameters were in the range from 30 ^ to 130 ^ using commercially available die attach glues. To determine a sitting plane for the die 110, a minimum number of spacers 310 are necessary, that is two rods or three cubes or εphereε. In a preferred embodiment of the present invention, then the mixing operation has to statistically guarantee that at least three spheres are present per dispensed glue spot.
The possible quantity of included spheres, without affecting the functionality of the glue material in its
performances as adhesion, heat transfer, electrical conductivity, goes from three to a very high number up to representing the 30% of the total volume of the attach material (including the spacer means) between the silicon device and the die pad on the substrate.
The spacers 310 may be realized with different materials. Advantageously, the spacers 310 have a CTE not greater than the CTE of the glue material; this embodiment of the invention reduces the risk of any detachment of the die device from the subεtrate, due to the expanεivity of the spacerε. Preferably, the spacers 310 are made of glasε ( Si02) in the case the CTE has to be driven by the compatibility with the composite laminate fiberglass material or corundum (A1203) in the case the CTE has to be the closest Oossible to the Silicon or Alumina CTE.
The proposed invention is ful v compatible with the existing materials and does not affect their physical and chemical properties. It is a low cost and of an extremely easy implementation. In addition, this technique guarantee a silicon chip planarity with better yield in automatic bonding operation reducing the silicon tilt yield detractor.
The packaging method involved by the present invention is fully compatible with the current processes and related equipment used in the industry. BGA oduleε are commonly manufactured εtarting from the εubεtrate 120, εuch aε an epoxy reinforced woven fiberglass laminate core structure.
The glue 210, typically epoxy glue loaded with Silver particles iε dispensed onto the subεtrate 120 top εide, typically in dots or according to a cross form. The spacerε
310 are mixed to the glue 210, either before or after diεpenεing. In an advantageouε embodiment of the present invention, theεe spacers 310 are mixed to the glue 210 before the step of dispensing the glue 210 onto the substrate 120; this embodiment it is low cost and does not require any additional equipment for placing the spacers 310 in the glue 210.
These spacers 310 are not collapsible inclusion within the glue 310, so that the die device 110, placed either manually or by a machine, is a flat surface that will soon meet the balls in the glue, stopping its sinking in the resin and automatically setting the required die attach material stand-off .
The device 110 is then wired to electrical circuit on the subεtrate and molded with a plastic resin as in the prior art process. It should be noted that the process according to the present invention does not require any additional step of forming a dry film onto the substrate.
Claims
1. An electronic package (200) including at least one die device (110) having a first CTE (Coefficient of Thermal Expansion) and a subεtrate (120) having a εecond CTE, εaid die device (110) being attached to εaid εubεtrate (120) by means of an intermediate layer (210) including an attach material having a third CTE greater than the lower between said first and said second CTE, characterized in that said intermediate layer (210) further includes spacer meanε (310) for spacing said die device (110) form said substrate (120) .
2. The electronic package (200) according to Claim 1, wherein said first CTE is lower than said second CTE.
3. The electronic package (200) according to Claim 1 or 2 , wherein said attach material (210) is a glue.
4. The electronic package (200) according to any Claim from 1 to 3 , wherein said spacer means (310) have a fourth CTE not greater than said third CTE.
5. The electronic package (200) according to any Claim from 1 to 4 , wherein said spacer means (310) are made of glasε or corundum.
6. The electronic package (200) according to any Claim from 1 to 5, wherein the volume of said spacer means (310) iε not more that the 30% of the volume of εaid intermediate layer (210).
7. The electronic package (200) according to any Claim from 1 to 6, wherein said spacer means include at least three spheres (310) .
8. The electronic package (200) according to Claim 7, wherein εaid εphereε (310) have a diameter compriεed between 20um and 130μm.
9. The electronic package (200) according to any Claim from 1 to 8, wherein said electronic package iε a BGA.
10. A method of manufacturing an electronic package (200) including a die device (110) having a first CTE (Coefficient of Thermal Expansion) and a substrate (120) having a second CTE, said method including the steps of: dispenεing an attach material (210) onto said subεtrate (120), εaid attach material (210) having a third CTE greater than the lower between said first and said second CTE, attaching said die device (110) to said substrate (120) by means of said attach material (210), characterized by the step of mixing spacer means (310) into said attach material (210) for spacing said die device (110) form said substrate (120).
11. The method according to Claim 10, wherein said step of mixing is performed before said step of dispensing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP1995/004972 WO1997022993A1 (en) | 1995-12-15 | 1995-12-15 | Electronic package with spacer means |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP1995/004972 WO1997022993A1 (en) | 1995-12-15 | 1995-12-15 | Electronic package with spacer means |
Publications (1)
Publication Number | Publication Date |
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WO1997022993A1 true WO1997022993A1 (en) | 1997-06-26 |
Family
ID=8166141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP1995/004972 WO1997022993A1 (en) | 1995-12-15 | 1995-12-15 | Electronic package with spacer means |
Country Status (1)
Country | Link |
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WO (1) | WO1997022993A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000067310A1 (en) * | 1999-04-30 | 2000-11-09 | Daimlerchrysler Ag | Microelectronic subassembly |
DE10240460A1 (en) * | 2002-08-29 | 2004-03-11 | Infineon Technologies Ag | Universal semiconductor package with pre-crosslinked plastic investment materials and process for producing the same |
US7807547B2 (en) * | 2006-03-28 | 2010-10-05 | Innovative Micro Technology | Wafer bonding material with embedded rigid particles |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4545840A (en) * | 1983-03-08 | 1985-10-08 | Monolithic Memories, Inc. | Process for controlling thickness of die attach adhesive |
JPS61182215A (en) * | 1985-02-08 | 1986-08-14 | Toshiba Corp | Manufacture of semiconductor device |
US5467252A (en) * | 1993-10-18 | 1995-11-14 | Motorola, Inc. | Method for plating using nested plating buses and semiconductor device having the same |
-
1995
- 1995-12-15 WO PCT/EP1995/004972 patent/WO1997022993A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4545840A (en) * | 1983-03-08 | 1985-10-08 | Monolithic Memories, Inc. | Process for controlling thickness of die attach adhesive |
JPS61182215A (en) * | 1985-02-08 | 1986-08-14 | Toshiba Corp | Manufacture of semiconductor device |
US5467252A (en) * | 1993-10-18 | 1995-11-14 | Motorola, Inc. | Method for plating using nested plating buses and semiconductor device having the same |
Non-Patent Citations (2)
Title |
---|
"CHIP-HEATSINK ATTACH USING CONTOURED ADHESIVE WITH GLASS STAND-OFFS", 1 August 1991, IBM TECHNICAL DISCLOSURE BULLETIN, VOL. 34, NR. 3, PAGE(S) 161 - 162, XP000210487 * |
PATENT ABSTRACTS OF JAPAN vol. 011, no. 007 (E - 469) 9 January 1987 (1987-01-09) * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000067310A1 (en) * | 1999-04-30 | 2000-11-09 | Daimlerchrysler Ag | Microelectronic subassembly |
DE19919716A1 (en) * | 1999-04-30 | 2001-08-09 | Daimler Chrysler Ag | Microelectronic assembly |
US6740982B2 (en) | 1999-04-30 | 2004-05-25 | Conti Temic Microelectronic Gmbh | Microelectronic package with an attachment layer including spacer elements |
DE19919716B4 (en) * | 1999-04-30 | 2005-11-03 | Conti Temic Microelectronic Gmbh | Microelectronic assembly |
DE10240460A1 (en) * | 2002-08-29 | 2004-03-11 | Infineon Technologies Ag | Universal semiconductor package with pre-crosslinked plastic investment materials and process for producing the same |
US7517722B2 (en) | 2002-08-29 | 2009-04-14 | Infineon Technologies Ag | Method of producing a universal semiconductor housing with precrosslinked plastic embedding compounds |
US7807547B2 (en) * | 2006-03-28 | 2010-10-05 | Innovative Micro Technology | Wafer bonding material with embedded rigid particles |
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