WO1997020316A3 - Automated process for generating boards from defective chips - Google Patents

Automated process for generating boards from defective chips Download PDF

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Publication number
WO1997020316A3
WO1997020316A3 PCT/IL1996/000171 IL9600171W WO9720316A3 WO 1997020316 A3 WO1997020316 A3 WO 1997020316A3 IL 9600171 W IL9600171 W IL 9600171W WO 9720316 A3 WO9720316 A3 WO 9720316A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
operative
perfect
memory elements
automated process
Prior art date
Application number
PCT/IL1996/000171
Other languages
French (fr)
Other versions
WO1997020316A2 (en
Inventor
Yaakov Friedman
Mark Schneider
Efim Sutzkever
Craig M Coel
Original Assignee
Yaakov Friedman
Efim Sutzkever
Craig M Coel
Memsys Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaakov Friedman, Efim Sutzkever, Craig M Coel, Memsys Ltd filed Critical Yaakov Friedman
Publication of WO1997020316A2 publication Critical patent/WO1997020316A2/en
Publication of WO1997020316A3 publication Critical patent/WO1997020316A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

An automated apparatus for generating a plurality of memory systems from a population of memory elements (90) including non-perfect memory elements each including at least one defective memory cell, the apparatus comprising: a region tester (80) operative to test regions within each non-perfect memory element for defective cells and to generate a regional testing result for each non-perfect memory element; a memory element grouper (100) operative to group the population of memory elements into a plurality of sets based on the regional testing results; and a controlling program generator (140) operative to automatically generate a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets.
PCT/IL1996/000171 1995-11-30 1996-11-28 Automated process for generating boards from defective chips WO1997020316A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IL11622095A IL116220A0 (en) 1995-11-30 1995-11-30 Automated process for generating boards from defective chips
IL116220 1995-11-30

Publications (2)

Publication Number Publication Date
WO1997020316A2 WO1997020316A2 (en) 1997-06-05
WO1997020316A3 true WO1997020316A3 (en) 1997-09-04

Family

ID=11068261

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL1996/000171 WO1997020316A2 (en) 1995-11-30 1996-11-28 Automated process for generating boards from defective chips

Country Status (2)

Country Link
IL (1) IL116220A0 (en)
WO (1) WO1997020316A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2367655A (en) * 2000-10-06 2002-04-10 Nokia Mobile Phones Ltd Method of using an integrated circuit with defects
US7060512B2 (en) * 2002-02-26 2006-06-13 Celetronix, Inc. Patching methods and apparatus for fabricating memory modules

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897626A (en) * 1971-06-25 1975-08-05 Ibm Method of manufacturing a full capacity monolithic memory utilizing defective storage cells
US4254477A (en) * 1978-10-25 1981-03-03 Mcdonnell Douglas Corporation Reconfigurable memory circuit
US4376300A (en) * 1981-01-02 1983-03-08 Intel Corporation Memory system employing mostly good memories
US4463450A (en) * 1980-08-29 1984-07-31 Siemens Aktiengesellschaft Semiconductor memory formed of memory modules with redundant memory areas
US4471472A (en) * 1982-02-05 1984-09-11 Advanced Micro Devices, Inc. Semiconductor memory utilizing an improved redundant circuitry configuration
US5058059A (en) * 1989-05-25 1991-10-15 Nec Corporation Memory circuit having a redundant memory cell array for replacing faulty cells
US5278793A (en) * 1992-02-25 1994-01-11 Yeh Tsuei Chi Memory defect masking device
US5293386A (en) * 1990-05-10 1994-03-08 Siemens Aktiengesellschaft Integrated semiconductor memory with parallel test capability and redundancy method
US5299202A (en) * 1990-12-07 1994-03-29 Trw Inc. Method and apparatus for configuration and testing of large fault-tolerant memories
US5359570A (en) * 1992-11-13 1994-10-25 Silicon Storage Technology, Inc. Solid state peripheral storage device
US5469390A (en) * 1993-09-16 1995-11-21 Hitachi, Ltd. Semiconductor memory system with the function of the replacement to the other chips
US5528539A (en) * 1994-09-29 1996-06-18 Micron Semiconductor, Inc. High speed global row redundancy system
US5539697A (en) * 1994-08-03 1996-07-23 Bi-Search Corporation Method and structure for using defective unrepairable semiconductor memory
US5572470A (en) * 1995-05-10 1996-11-05 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column
US5574688A (en) * 1995-05-10 1996-11-12 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column
US5577050A (en) * 1994-12-28 1996-11-19 Lsi Logic Corporation Method and apparatus for configurable build-in self-repairing of ASIC memories design
US5608678A (en) * 1995-07-31 1997-03-04 Sgs-Thomson Microelectronics, Inc. Column redundancy of a multiple block memory architecture

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897626A (en) * 1971-06-25 1975-08-05 Ibm Method of manufacturing a full capacity monolithic memory utilizing defective storage cells
US4254477A (en) * 1978-10-25 1981-03-03 Mcdonnell Douglas Corporation Reconfigurable memory circuit
US4463450A (en) * 1980-08-29 1984-07-31 Siemens Aktiengesellschaft Semiconductor memory formed of memory modules with redundant memory areas
US4376300A (en) * 1981-01-02 1983-03-08 Intel Corporation Memory system employing mostly good memories
US4471472A (en) * 1982-02-05 1984-09-11 Advanced Micro Devices, Inc. Semiconductor memory utilizing an improved redundant circuitry configuration
US5058059A (en) * 1989-05-25 1991-10-15 Nec Corporation Memory circuit having a redundant memory cell array for replacing faulty cells
US5293386A (en) * 1990-05-10 1994-03-08 Siemens Aktiengesellschaft Integrated semiconductor memory with parallel test capability and redundancy method
US5299202A (en) * 1990-12-07 1994-03-29 Trw Inc. Method and apparatus for configuration and testing of large fault-tolerant memories
US5278793A (en) * 1992-02-25 1994-01-11 Yeh Tsuei Chi Memory defect masking device
US5359570A (en) * 1992-11-13 1994-10-25 Silicon Storage Technology, Inc. Solid state peripheral storage device
US5432748A (en) * 1992-11-13 1995-07-11 Silicon Storager Technology, Inc. Solid state peripheral storage device
US5469390A (en) * 1993-09-16 1995-11-21 Hitachi, Ltd. Semiconductor memory system with the function of the replacement to the other chips
US5539697A (en) * 1994-08-03 1996-07-23 Bi-Search Corporation Method and structure for using defective unrepairable semiconductor memory
US5528539A (en) * 1994-09-29 1996-06-18 Micron Semiconductor, Inc. High speed global row redundancy system
US5577050A (en) * 1994-12-28 1996-11-19 Lsi Logic Corporation Method and apparatus for configurable build-in self-repairing of ASIC memories design
US5572470A (en) * 1995-05-10 1996-11-05 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column
US5574688A (en) * 1995-05-10 1996-11-12 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column
US5608678A (en) * 1995-07-31 1997-03-04 Sgs-Thomson Microelectronics, Inc. Column redundancy of a multiple block memory architecture

Also Published As

Publication number Publication date
WO1997020316A2 (en) 1997-06-05
IL116220A0 (en) 1996-01-31

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