WO1997013324A1 - A semi-conductor integrated circuit - Google Patents
A semi-conductor integrated circuit Download PDFInfo
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- WO1997013324A1 WO1997013324A1 PCT/GB1996/002461 GB9602461W WO9713324A1 WO 1997013324 A1 WO1997013324 A1 WO 1997013324A1 GB 9602461 W GB9602461 W GB 9602461W WO 9713324 A1 WO9713324 A1 WO 9713324A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Definitions
- TITLE A semi-conductor integrated circuit
- the present invention relates to a semi ⁇ conductor integrated circuit, and especially, but not exclusively, to a semi-conductor integrated circuit of the type comprising configurable logic circuit arrays.
- a semi-conductor integrated circuit comprises a plurality of resources which can be divided up into routing resources, function resources and storage/program resources.
- a configurable logic circuit array having a matrix of discrete sites or cells at each of which is a logic circuit which is adapted to perform a simple logic function.
- the simple logic function is implemented by means of a two input NAND gate as a primary function and each site has a secondary function.
- the cells are arranged in tiles being a grouping of 2 x 2 core cells and a selection of different secondary functions are available within a tile.
- Each cell connects to others by way of a restricted local interconnect structure where each output of a cell connects to a sub-set of the inputs of its 8 perpendicular neighbours.
- the cells also connect to each other by medium connection paths that extend between a porting arrangement and at least some of the cells in the zone.
- the zone connects to the rest of the logic array by means of a porting arrangement which supplies connections between the core cells within the zone via medium buses and with other zones by either global interconnect or by the medium interconnect of the adjacent zones.
- a restriction of configurable logic circuit arrays is that the full use of all the functions available within the array is not possible, due to restrictions in routing the required signals to and from the function cells. The problem is exacerbated by the requirement to reduce the silicon area used by the device to a minimum, to provide a large function to silicon cost ratio.
- the logic circuit of the cells provide function resources or can be used as routing resources at a local level.
- Other interconnect structures must be effectively used and the silicon area used is determined by the functions implemented on the silicon and by the number of programming bits required to control the specified functions. Thus, to keep the silicon cost as low as possible the number of programming bits used needs to be a minimum, with as few unused programming bits as possible.
- To facilitate silicon layout of the device as much uniformity of the physical layout as possible is maintained. In the device according to British Patent Specification No. 9410980.8 all the core cell tiles have the same physical layout and the use of the two input core cell function dictates that implementation of a three input function requires at least two core cells to be used together with the interconnect resources to connect the two cells together.
- a common function used within circuits is a multiplexer.
- a two input multiplexer requires three inputs and hence with the prior art multiple core cells have to be used to generate the function, together with the associated interconnect resources used. Making the cells more complex would require a considerable increase in the silicon area.
- a first aspect of the invention proposes a semi-conductor integrated circuit which, as made, comprises an area thereof formed with a plurality of cells, each cell having a plurality of resources which comprise storage/programming resources and functional resources, the functional resources comprising at least one of routing resources and logic function resources according to the cell type and whereas, as made, each cell has a finite number of resources in it, and wherein the improvement comprises augmenting the resources available to a cell by utilising resources from at least one other cell.
- the present invention proposes sharing of resources between cells so as to maximise silicon utilisation and circuit efficiency.
- the cells are disposed in a matrix array which is divided into zones.
- the secondary function can become a three input function (eg. a two input multiplexer) by sourcing the third input from another cell.
- a three input function eg. a two input multiplexer
- the function of the source cell which is preferably an adjacent cell, is not disabled.
- This offers a saving in core cells used, allowing circuits of greater complexity to be implemented upon the array. Its also has the advantage of increasing the speed a function can be run at, when compared with the prior device. More specifically according to this embodiment cells are arranged in tiles, for example comprising a matrix array of 2 x 2 core cells, each core cell having a common primary function (eg. 2 input NAND gate) and a secondary function.
- each tile will be identical.
- the cells are conveniently disposed in rows and columns.
- the third input for the multiplexer is taken from the vertically adjacent cell in the same tile.
- the output is taken from the medium bus output driver. This means that the driving cell can still be configured as a totally independent function, the only restriction being that the driving cell could only output via its local interconnect structure, except where the driving cell also generates the signal to the third input of the driven cell.
- the logic sites or cells as made have a local interconnect structure by which any one cell is only connectable with some of the other cells. Usually any one cell will only connect with its eight nearest perpendicular neighbours. In addition, there are medium connection paths by which signals are routed to or from a cell via a port cell associated with the zone in which the cell concerned is located.
- the core cells at the zone boundaries having spare programming bits.
- the core cells in the corners of the zones have four spare bits since they could have had four local interconnections that bridged the port cells, ie. two in the horizontal direction, two in the vertical direction.
- the core cells along the sides have two spare bits corresponding to removal of two local interconnections across the zone boundary.
- the above- described local interconnects for these boundary core cells can be physically removed.
- the programming bits which were previously employed controlling local interconnect at the zone boundaries are reassigned to be used by the port cells to provide greater connectivity from the port cell multiplexers onto the medium busses, thereby enabling connectivity between the global interconnect and the medium interconnect to be increased.
- the physical location at the reassigned programming bit remains unchanged, ie. they stay in their respective core cells.
- a logic circuit array which, as made, comprises an area thereof formed with a plurality of logic circuits at discrete cells respectively defining a matrix array of cells.
- the matrix array of cells is sub-divided at least into zones (each comprising a matrix array of cells) and further comprising a porting arrangement for each zone and a hierarchical routing structure comprising global connection paths having selectable connections with a porting arrangement of each zone, medium connection paths extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and local direct connection paths comprising a restricted signal translation system.
- a restriction of configurable logic circuit arrays is that the full use of all the functions available within the array is not possible, due to restrictions in routing the required signals to and from the function cells across the whole array.
- the problem is exacerbated when larger devices are implemented, due to the greater number of signals that are required to be passed around the array.
- the routing paths across the array becomes slower, due to the physical length of these paths and the loading effects of the resources connecting to them, hence effecting the overall effectiveness of the array.
- One solution, and perhaps the obvious solution is to create more resources at each level, ie. more global connection paths and more medium connection paths.
- this is disadvantageous in terms of silicone utilisation and accordingly the present invention aims to provide a solution.
- this aspect of the invention provides a semi-conductor integrated circuit which, as made, comprises an area thereof formed with a plurality of logic circuits and defining a matrix array of cells divided into zones (preferably there is a matrix array of zones) and a zone porting arrangement for each zone, and further comprising a hierarchical routing structure disposed in successive layers and wherein the successive layers of routing resource comprise: zone interconnect comprising local direct connection paths connecting at least some of the cells with some other cells, and medium connection paths extending from the porting arrangement and selectably connectable with at least some of the cells in a zone; and global connection paths having selectable connections with the porting arrangement of each zone, and further comprising one or more further successive levels of routing resource having a respective porting arrangement to connect that level of routing resource with the preceding level of routing resource.
- each porting arrangement connects two adjacent levels of routing hierarchy.
- the porting arrangement also provides connection to other busses within the same layer of hierarchy.
- the porting arrangement at each level reflects the typical layout of an integrated circuit in which the cells are disposed in rows and columns, and comprises port cells and conveniently there are port cells which extend in the horizontal direction and in the vertical direction. Conveniently these are referred to as horizontal port cells and vertical port cells respectively.
- connection paths conveniently referred to as busses, which run in the horizontal direction and in the vertical direction.
- additional busses conveniently referred to as x busses.
- these additional busses connect to switches situated at discrete cites within the array, their purpose being to connect the horizontal and vertical segments of these busses together to implement 90° turns within that layer of interconnect.
- These x busses connect to their level of hierarchy at the porting arrangements.
- a preferred arrangement is for the switches for these types of busses to be situated within some of the core cells. Just as there is a port cell for each zone of cells, it is preferred that the porting arrangements for each successive layer will be zoned such that any port cell for that level will have access to a plurality of port cells of the preceding lower level via the connection paths for that level.
- a super-port cell will connect with a plurality of port cells of the adjacent lower level via the global connection path linking those port cells.
- each super-port cell is associated with a plurality of zones. This is conveniently referred to as a super-zone.
- Each porting arrangement also allows connection of the same type of busses between adjacent zones in the same layer.
- the device has at least three levels of hierarchy.
- a preferred construction comprises tiles consisting of four individual core cells, with 25 tiles (100 core cells) making up a zone, and wherein the zones are structured into super-zones with preferably 5 x 5 zones making up a super-zone.
- interconnect hierarchy comprises zone interconnect made using either local or medium interconnect, with the port cells (ie. vertical and horizontal port cells) around each zone used to connect the medium busses to the next higher layer of routing hierarchy.
- Local interconnect is used to connect a cells output for example to each cells nearest perpendicular neighbours, and with the medium busses running horizontally and vertically, providing connections to core cells within the zone.
- Interconnect further comprises a global interconnect layer consisting of global and x busses.
- connections from zone level medium busses to/from global and x busses are made via the port cells.
- the global busses, as well as connecting to the port cells also connect to 10 cells and what are termed super-port cells, ie. the port cells of the next higher routing resource.
- Global busses run vertically and horizontally across the super- zones, ie. between the ports of the next higher level of resource.
- the x busses are used to make turns at the global routing level. There are preferably three global busses and one x bus for every row and column of core cells. Switches between horizontal and vertical x busses (to make 90° turn between horizontal and vertical global busses) are situated in each of the core cells.
- Interconnect further comprises a super-global interconnect layer comprises super-global and super-x busses. This layer is used for connections that span the whole device (that is, across super-zones between the super port cells and other super port cells IO cells) . Connections between the global and the super- global resources are made using the super-port cells situated between super-zones. There is preferably one super-global bus and two super-x busses per row and column of core cells. The super-x busses are used to make turns at the super global level. The super-port cells are also used to make liner connections between global and super-global busses.
- the hierarchical interconnect structure can be further extended to at least a further successive layer of routing conveniently referred to as hyper-global above the super-global interconnect.
- the super-global interconnect would only span across super-zones whilst the extra layer would extend across at least some super-zones and partitioned by a porting arrangement (hyper-port cells).
- the porting arrangement would connect the super-global interconnect to the extra level of interconnect and to the super-global interconnect of the adjoining partitioned area. Within the extra layer, the porting would extend in both horizontal and vertical directions.
- the busses in the extra layer would run in the horizontal and vertical directions, turns between the horizontal and vertical busses are accommodated by additional busses of type x. These additional busses connect to switches situation at discrete cites within the array, their purpose being to connect the horizontal and vertical segments of these busses together to implement 90° turns within that layer of interconnect, these x busses connect to their level of hierarchy at the porting arrangements.
- Figure lb is a diagrammatic illustration of part of a hierarchical routing structure according to another embodiment
- Figure 2.I.A is an overall schematic of an array structure embodying the invention.
- Figure 2.2.A illustrates the location of super-x bus switches
- Figure 2.2.B is a schematic of a super-port cell
- Figure 2.3.A illustrates connections for vertical port cells
- Figure 2.3.B is a vertical port cell schematic.
- Figure 2.3.C illustrates connections for a horizontal port cell,
- Figure 2.3.D is a horizontal port cell schematic,
- Figure 2.3.E-H are port cell schematics for the top, bottom, left and right edges respectively.
- Figure 2.4.A illustrates diagrammatically a zone structure
- Figure 2.4.B illustrates a preferred embodiment of local cell to cell signal connection possibilities
- Figure 2.4.C illustrates the medium bus connections for a Type A tile
- Figure 2.4.D illustrates the medium bus connections for a Type B tile
- Figure 2.4.E illustrates a preferred arrangement of tiles in a zone.
- Figure 2.5.A is a schematic of a core cell structure
- Figure 2.5.B is a diagrammatic illustration of core cell tiling
- Figure 2.5.C is a schematic for the core cell input multiplexer
- Figure 2.5.D is a schematic for the core cell output multiplexer
- Figure 2.5.E is a schematic illustration of the combinatorial core cells of Type 1 to 3
- Figure 2.5.F is a schematic for a tile showing the derivation of the third input from vertically adjacent cells
- Figure 2.5.G is a schematic for a Type 4 core cell
- Figure 2.5.1 is a diagrammatic illustration showing the arrangement of configuring ram bits for cells in the vicinity of the horizontal and vertical port cell boundary.
- FIG. la is a diagrammatic illustration of the present invention.
- Core cells comprising a matrix array of integrated circuits are shown in dotted outline as a block of cells.
- Each block represents a zone (Z).
- Each zone has associated with it a porting arrangement or port cell (PC).
- G global signal connection paths
- SZ super-zones
- a further layer of signal interconnect is provided by super-global bus (SGB) which extends across the super-zone (SZ) between super-port cells (SPC) by which signals as the SG bus or busses are routed either between super-zones or down to the global bus(es) (G).
- SGB super-global bus
- SZ super-zone
- SPC super-port cells
- FIG lb is a diagrammatic illustration of a further embodiment of the invention and extends the arrangement described in Figure la to suit yet larger arrays.
- Like reference numerals denote the same features as described with reference to ' Figure la and the corresponding description applies and has not been repeated.
- the super-zones SZ are themselves grouped into what are conveniently terms hyper-zones (HyZ), and there are signal connections paths conveniently referred to as hyper-global busses (HyG) , which extends across the hyper-zones to form a further layer of routing resource.
- the hyper-global busses connect with hyper-global port cells (HyPC) which control passage of the signals between the hyper-zones or down to the lower level resource - namely the super-global busses (SG).
- HyPC hyper-global port cells
- each successively higher level of global routing resource will span a greater number of zones. It is also preferred that each further successive layer of routing resource comprises a decreased number of routing lines, ie. there are fewer super-global busses than global busses, and fewer hyper-global busses than super-global busses, etc.
- a preferred array structure is illustrated with reference to Figure 2.1.A for the case of a 22.5k cell array.
- the array is partitioned hierarchically into super-zones SZ, zones Z and tiles T.
- Each tile consists of four individual core cells CC, and 25 tiles (or 100 core cells make up a zone.
- Zones are structured into super-zones, with 9 super-zones plus input/output cells 10 making up the 22.5 k cell device.
- Each zone comprises a matrix array of 10 x 10 core cells and each tile consists of a matrix array of 2 x 2 core cells.
- a super-zone is made up of a matrix array of 5 x 5 zones.
- Each zone is bordered on two of its edges by port cells PC conveniently referred to as horizontal port cells HPC along a horizontal edge of the zone and vertical port cells VPC disposed along a vertical edge of the zone.
- Super-port cells SPC are associated with each of the super-zones and there are horizontal super-port cells HSPC and vertical super-port cells VSPC.
- the array is comprised of a matrix array of 3 x 3 super-zones and separated from each other by respective super-port cells, horizontal and vertical cells as the case may be.
- the first layer is conveniently referred to as zone interconnect and includes connections within zones using either local or medium interconnect.
- Local interconnect (see Figure 2.4.B) is used for fast connections to each cell's eight nearest perpendicular neighbours (B, BB, F, FF, U, UU, L, LL) , and medium busses (M1-M6) run horizontally and vertically to provide connections to core cells anywhere in the zone.
- M1-M6 medium busses
- Port cells (HPC and VPC) around each zone are used to connect the medium busses to the next layer of routing hierarchy - the global layer described further hereinafter. These port cells also allow medium bus connections to neighboring zones (see Figures 2.3.A-2.3.D) .
- the second layer of routing referred to as global interconnect consists of global G and x busses referenced x. Connections from zone level medium busses to/from global and x busses are made via the port cells PC. Global busses run vertically and horizontally across the super-zones (see Figure 2.4.A). The x busses are used to make turns at the global routing level. There are three global busses and one x bus for every row and column of core cells. Switches between horizontal and vertical x busses (to make 90° turns between horizontal and vertical global busses) are situated in each of the core cells.
- Global busses as well as connecting to port cells, also connect to IO cells and super-port cells.
- the third routing layer is conveniently referred to as super-global interconnect and it refers to routes that run across the device between respective super-port cells or between super-zones and/or 10 cells) and comprise super-global SG and super-x (ref. SX) busses with each spanning a super-zone. Connections between the global and super-global resources are made using the super-port cells SPC, situated between super-zones (see Figures 2.2.B). There is one super-global bus SG and two super-x (SX) busses per row and column of core cells. The super-port cells are also used to make linear connections between global and super-global busses (ie. from global to global, or super-global to super-global busses).
- each core cell can be used an simple NAND gate (see Figure 2.5.A).
- each core cell also implements a range of secondary functions.
- the cells are conveniently referred to as types 1, 2, 3 and 4 (see Figure 2.5.B).
- Each has the NAND as its primary function, whilst types 1, 2 and 3 have X-OR/MUX as the secondary function and type 4 has as its secondary function a D-type flip-flop- abbreviated DFF (with reset and enable).
- the clocks and resets are distributed via the dedicated interconnect to the DFF cells in the array.
- user configurable 10 cells provide connections to/from the array (via super-global, super-x, global, x and medium busses). 10 cells are also arranged into zones - the 10 zones pitch match the array zones, and there are four 10 cells for every 10 core cells. Each 10 cell can also connect to a four bit peripheral bus that runs around the array.
- the peripheral bus can be divided into four sections using switches at the corners of the device. It can be used either as a conventional bus, or as a wired-OR bus for address de-coding etc.
- the super-global resources SG, SX provide the top level interconnection.
- Super-global busses SG provide connections between super-zones, and to/from the 10 cells.
- Super-x busses SX are used to implement 90° turns between super-global busses and are also used to connect to the IO cells.
- Super-port cells SPC provide connections between the super-global and the global resource layers. There is one super-global bus for every row/column of core cells. Each super-global bus spans a single super-zone, and can be connected only at the super-port cells or in the case of super-zones that are at the edge of the array to/from the IO cells.
- Super-global busses are a fast method of carrying signal long distances. There are two super-x busses for every row/column of core cells.
- each super-x bus spans a single super-zone, and can be connected to only at the super-port cells, or (for super-zones at the each of the array) at the 10 cells.
- super X-busses connect to switches SXBS situated in the core cells so that horizontal and vertical super-x busses can be joined to implement 90° turns. Turn switches are located in every tile (ie. every 4 core cells).
- Figure 2.2.A shows the detail of the positioning of the switches within each tile.
- Super-x busses may also be used to route signals across super-zones (ie. like super-global busses), but they are a slower resource for this than using super-global busses, because of the extra loading of the switches.
- FIG.I.A The device illustration in Figure 2.I.A is partitioned into 9 super-zones. Between each super-zone are horizontal and vertical super-port cells - one super-port cell for every row and column of core cells.
- Figure 2.2.B shows the available connections in schematic form for a super-port cell.
- Horizontal and vertical super-port cells have identical functionality.
- Each super-port cell requires 24 configuration RAM bits.
- Each I/O cell can be connected to/from the super- global bus and both super-x busses in three rows/columns of core cells. Since there are four I/O cells to every zone (ie. 10 core cells), 1 in 5 rows/columns can be connected to either one or two 1/0 cells (all other rows/columns to connect to just one I/O cell) .
- Each array zone (10 x 10 core cells) has ten port cells on each side (see Figure 2.I.A).
- the port cells above and below a zone are call the Vertical Port Cells (since they handle vertical interconnect, and the port cells to the left and right of each zone are called the Horizonal Port Cells (since they handle the horizontal interconnect) .
- Port cells are used for connections between zonal routing resources (medium busses) and the global resources (global and 'x' busses). Port cells also support connections between medium busses in adjacent zones. All 6 medium busses in each row/column connect to the port cells (M1..6). Primary clocks and resets are distributed via the vertical port cells.
- Port cells are symmetrical, and buffering is only used when changing from one layer of hierarchy to another.
- Figure 2.3.A represents the Vertical Port cell connections, and shows how the zone and global busses are connected. Connections between zones (ie. medium bus to medium bus, or , x' bus to medium bus) are unbuffered. Port cells are arranged in pairs, aligned with the core cells tiling. This is to allow port cells to access medium busses in both columns of the tile. For example, medium bus M2 of the right hand column in Figure 2.3.A can be connected to medium, global or 'x' busses of the left hand column using the crossover connection at the bottom of the port cell pair (ie. by using the centre "A2" mux connection in the left hand port cell in Figure 2.3.A).
- the medium busses from the adjacent columns are called “M1P” or “M2P” in the schematic diagrams. Connections to and from the global routing layers (ie. to and from the global and , x' busses, via the "AS" and “C3” muxes) are buffered in both direction.
- the "B" mux in the centre of each port cell allows two direct, unbuffered connections from M3- M3 and M4-M4 in adjacent zones.
- Four primary clock/reset lines run through the vertical port cells (2 clocks and 2 resets) . Alternate port cells have either a primary clock or reset multiplexer - these select the source for the dedicated clock and reset lines to the D flip-flop core cells.
- a programmable inversion and tie- off are also provided in the clock/reset multiplexer.
- the primary clock/reset can be connected into the zone, from the clk/rst mux, via muxes "C3" and "C2". Secondary clocks/resets are sourced, via "C3" and the clk/rst mux, from the global busses. Thirty configuration RAM bits are required to programme each vertical port cell.
- a complete schematic is shown in Figure 2.3.B. Horizontal Port Cells provide similar resources to the vertical port cells, with two differences. Firstly, the "B" mux provides a crossover switch between M3 and M4.
- each horizontal port cell allows two direct, unbuffered connections either from M3-M3 and M4-M4, or M3-M4 and M4-M3, in adjacent zones, and secondly there is no clock-reset distribution in the horizontal port cells.
- Figure 2.3.c shows horizontal port cell connections
- Figure 2.3.D is the full schematic.
- Port cells are symmetrical and are designed to interface to/from zones on either side of the port cell (top and bottom for vertical ports, or left and right for horizontal ports) . However, around the edges of the array, port cells only have any array on one side (10 cells are on the other side). Therefore, cut-down port cells are used around the edges of the array, to save configuration RAM bits and to reduce bus loading. There are four different edge port cells, for each side of the array. Schematics for each edge port cells are shown in Figures 2.3.E to 2.3.H.
- the bottom, left and right edge port cells need 13 configuration RAM bits for programming.
- the top-edge port cells requires 17 configuration RAM bits (the extra bits in this cell are needed for clock/reset mux).
- Connections should always be made through the port cell multiplexers (for example, global to medium bus through Mux A3 and Mux A2). Connections should not be made in and out of the same side of a port cell mux ("bank-shots") .
- Gl should not be joined to G2 via Mux A3.
- the exception to this rule is that medium busses may be joined using Muxes A2 and C2. Connections to 'x' busses are to be buffered. For example, M to X via A1-A2 not allowed, but the preferred route is M to X via A1-A3.
- the device in Figure 2.4.A shows a zone structure for the device.
- the medium, global and 'x' busses are only shown in one row/column in Figure 2.4.A for clarity.
- the super-global and super-x busses are not shown in Figure 2.4.A because they do not connect to the zone level resources.
- Local interconnect provides a connection from the output of each core cell to one input multiplexer of its eight nearest perpendicular neighbours. Local interconnect is the fastest connection between core cells.
- the available connections are shown in Figure 2.4.B. Local interconnect does not continue across zone and super- zone boundaries.
- the naming convention used in Figure 2.4.B is to name destination core cells relative to the source core cell. For example, core cell UU is two core cells up from the driving cell, B is one core cell back. and FF is two core cells forward.
- Medium interconnect is used for connections within a zone that are not possible using local interconnect, and for inter-zone connections via the horizontal and vertical port cells. Four of them can also be connected to global resources via the port cells. Ml..2 and M5..6 can all be connected to global or 'X' busses via the port cells. M3..4 do not connect up to global-layer routing, but are used for inter-zone connections (using the 'B' mux in the port cells). See Section 2.3.3 (Port Cells). Inside each zone, the horizontal and vertical medium busses connect to the input and output multiplexers of each core cell. Each core cells has two input multiplexers - each of which can connect to three medium busses.
- the core cell output multiplexer can drive 6 medium busses. There are 12 medium busses running vertically and horizontally across each core cell. Therefore, each core cell can only connect to half the total number of medium busses available. To compensate for this, there is a hierarchical, repeated pattern of medium bus connections across each zone. Ml..4 connections are arranged in a pattern that repeats every tile (2 x 2 core cells) and M5..6 are transposed in adjacent tiles. Each core cell in a tile has the same M5..6 connections, but adjacent tiles have M5/M6 connections reversed (ie. M5 inputs become M6 inputs, M6 outputs become M5 outputs, and vice versa).
- Figure 2.4.C shows the medium bus connections in a tile, where M5 is an input and M6 is an output. This is called Tile Type A.
- Figure 2.4.D shows the medium bus connections for the adjacent tile (M6 inputs and M5 outputs) - called Tile Type B.
- Figure 2.4.E shows the arrangement of Tiles A and B within a zone. Note that the Ml..4 connections are identical in both tile types.
- Each 10 cell can be connected to/from two of the medium busses (M3/4) in three rows/columns of core cells.
- the core cell is the basic functional block in the array. Each core cell can be programmed to implement either a 2-input NAND gate, or one of alternative functions. Each core cell has the same basic structure - shown in Figure 2.5.A. Each core cell contains: two input multiplexers (7 inputs each (3, medium,
- Core cells are arranged in 2 x 2 tiles - each tile supports all the available alternative functions.
- the fourth cell in each tile supports a D-type flip-flop (ie. NAND + DFF).
- the reset and clock for the DFF cell (type 4) are provided via dedicated interconnect from the vertical port cells.
- Each DFF can have its reset tied inactive if required- the reset enable is located in the Type 3 cell to provide an even distribution of RAM bits between the 4 core cells.
- Core cells also contain the SX and X bus switches.
- Figure 2.5.B shows the arrangement of cells within each tile.
- Each core cell has two input multiplexers (A, B) - each mux can input from 3 medium busses and 4 local connections.
- the local interconnect can be swapped between the A and B muxes using a crossover switch. See
- the output multiplexer connects each cell's output to up to 6 medium busses (3 vertical and 3 horizontal). If a core cell is not required to drive a medium bus, then the output mux of that cell may be used to connect medium busses together.
- the core cell output mux may also be used to supply the 'select' input for the 2-to-l MUX function in vertically adjacent core cells.
- each core cell provides the basic functional block in the array and that each core cell can be programmed to implement either a 2-input NAND gate, or one of a range of alternative functions.
- Each core cell has the same basic structure as shown and described with reference to Figure 2.5.A. Reference is also directed to Figures 2.5.B, 2.5.C and 2.5.D.
- Core cell Types 1 to 3 all have identical functional resources. They differ only in the location fo the super x bus switches and rest enable logic.
- Figure 2.5.E shows the schematic for the Type 1 to 3 core cells - but exclusively the input multiplexer and medium bus output multiplexer. Programmable inversion is provided at both the A and B inputs by 2 RAM bits. Two further ram bits determine the core cell function.
- the illustration shows a third input to the core cell at 100 and is the select line for the 2-to-l mux. It is sourced from the vertically adjacent core cell in the tile (ie. the core cell above for Types 3 and 4, and the core cell for Types 1 and 2) - see Figure 2.5.F.
- Figure 1.5.D shows how the select line is generated from the medium bus output multiplexer.
- This arrangement means that there are two ways of routing a select line to the 2-to-2 mux function. The first is direct from horizontal/vertical medium buses.
- the medium bus output mux 102 of the vertically adjacent core cell in the tile is used as an input multiplexer.
- the mux select can be sourced from one of the six medium buses that are connected to the output mux.
- the core cell is still available as a function or routing resource, with the limitation that its output mux is no longer available - ie. the output must go onto local interconnect only.
- the mux select line can also be sourced from any of the signals available at the core cell A and B input multiplexers.
- the core cell is no longer able to function as a function or routing resource.
- the secondary core cell function of at least some of the cells in a tile can have functions with greater than two inputs, and more specifically, three inputs. More particulary, the three input function is 'a multiplexer' and the third input is the select line for the multiplexer.
- the third input is driven by a resource from an adjacent cell.
- the source of the third input is the medium bus output multiplexer, and conveniently from an adjacent cell. This resource can be isolated from the output of the adjacent core cells primary function. The adjacent core cells primary function is thus driven out via local interconnect.
- FIG. 2.5.G here there is illustrated the schematic for a Type 4 cell which provides the D-type flip-flop function.
- the DFF is configurable with an asynchronous reset if required, and the clock is sourced form the primary or secondary clocks via the vertical port cells.
- the schematic excludes the schematic for the input multiplexer and medium bus output multiplexer. Programmable inversion is provided on both the A and B inputs.
- the D-input to the DFF has a mux cell in front of it. If the cell is configured as a simple DFF then the 2-to-l mux can be used as a switch to select whether the D-input is sourced from either the A or B core cell input multiplexers (ie. using the programmable inversion on the select input, in conjunction with the pull down).
- port cells have to pitch-match to the array of core cells. That is to say, the vertical port cells have to have the same number of programming bits as the core cells.
- each core cell requires 26 configuration RAM bits - these are physically arranged in 2 rows of 13, with the cells logic in between. This core cell layout restricts the dimensions of the port cells.
- Vertical port cells must use multiples of 13 bits to match to core cells. Twenty-six RAM bits in 2 rows of 13 is a practical maximum when taking die size into account.
- Horizontal port cells have to pitch match to the number of rows of RAM in a core cell (ie. 2 rows), and there is no theoretical limit on the number of bits in a row.
- the width ie.
- bits/row) of the horizontal port cell has to be limited to minimise the total width of the die. For the proposed architecture, 2 rows of 12 bits gives a reasonable width. This is illustrated in Figure 2.3.1. Eight of the RAM bits of the core cells are normally allocated to enable local interconnections with the cells eight nearest perpendicular neighbours. However, since local interconnect is not continuous across zone and super zone boundaries in this embodiment, core cells around the edge of zones have either 2 or 4 redundant RAM bits which are normally used for local interconnect inputs. Core cells in the corner of a zone have 4 redundant bits, since both vertical and horizontal local interconnect is redundant/removed. Other edge cells only lose 2 bits. These redundant bits are borrowed by the port cells to increase the RAM bits available to each port cell. This is illustrated diagrammatically on Figure 2.3.1.
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09514085A JP2000513511A (en) | 1995-09-30 | 1996-10-01 | Semiconductor integrated circuit |
EP96934983A EP0853840A1 (en) | 1995-09-30 | 1996-10-01 | A semi-conductor integrated circuit |
AU73091/96A AU7309196A (en) | 1995-09-30 | 1996-10-01 | A semi-conductor integrated circuit |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9520027.5A GB9520027D0 (en) | 1995-09-30 | 1995-09-30 | A semi-conductor integrated circuit |
GB9520026.7 | 1995-09-30 | ||
GBGB9520026.7A GB9520026D0 (en) | 1995-09-30 | 1995-09-30 | Semi-conductor integrated circuit |
GB9520027.5 | 1995-09-30 |
Publications (1)
Publication Number | Publication Date |
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WO1997013324A1 true WO1997013324A1 (en) | 1997-04-10 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB1996/002461 WO1997013324A1 (en) | 1995-09-30 | 1996-10-01 | A semi-conductor integrated circuit |
Country Status (7)
Country | Link |
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EP (1) | EP0853840A1 (en) |
JP (1) | JP2000513511A (en) |
CN (1) | CN1203706A (en) |
AU (1) | AU7309196A (en) |
CA (1) | CA2235927A1 (en) |
GB (1) | GB2305759A (en) |
WO (1) | WO1997013324A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US6275064B1 (en) * | 1997-12-22 | 2001-08-14 | Vantis Corporation | Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits |
US6215326B1 (en) | 1998-11-18 | 2001-04-10 | Altera Corporation | Programmable logic device architecture with super-regions having logic regions and a memory region |
JP3616518B2 (en) | 1999-02-10 | 2005-02-02 | 日本電気株式会社 | Programmable device |
EP1465345A3 (en) * | 1999-03-04 | 2006-04-12 | Altera Corporation | Interconnection resources for programmable logic integrated circuit devices |
EP1078463B1 (en) | 1999-03-04 | 2004-08-04 | Altera Corporation | Interconnection resources for programmable logic integrated circuit devices |
WO2000069072A1 (en) * | 1999-05-07 | 2000-11-16 | Morphics Technology Inc. | Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array |
KR20150127608A (en) * | 2013-03-01 | 2015-11-17 | 아토나프 가부시키가이샤 | Data processing device and control method therefor |
US8853815B1 (en) * | 2013-03-14 | 2014-10-07 | Qualcomm Incorporated | Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains |
DE102019006292A1 (en) * | 2019-09-05 | 2021-03-11 | PatForce GmbH | Arrangement of switch boxes |
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US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5357153A (en) * | 1993-01-28 | 1994-10-18 | Xilinx, Inc. | Macrocell with product-term cascade and improved flip flop utilization |
GB2279186A (en) * | 1993-06-16 | 1994-12-21 | Daiichi Denso Buhin | An electrical connector assembly |
EP0630115A2 (en) * | 1993-06-18 | 1994-12-21 | Pilkington Micro-Electronics Limited | Configurable logic array |
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US5144166A (en) * | 1990-11-02 | 1992-09-01 | Concurrent Logic, Inc. | Programmable logic cell and array |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
ATE214210T1 (en) * | 1994-04-14 | 2002-03-15 | Btr Inc | ARCHITECTURE AND CONNECTION SCHEMES FOR PROGRAMMABLE LOGIC CIRCUITS |
US5689195A (en) * | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
US5592106A (en) * | 1995-05-17 | 1997-01-07 | Altera Corporation | Programmable logic array integrated circuits with interconnection conductors of overlapping extent |
-
1996
- 1996-09-27 GB GB9620362A patent/GB2305759A/en not_active Withdrawn
- 1996-10-01 EP EP96934983A patent/EP0853840A1/en not_active Ceased
- 1996-10-01 CN CN 96198716 patent/CN1203706A/en active Pending
- 1996-10-01 CA CA 2235927 patent/CA2235927A1/en not_active Abandoned
- 1996-10-01 AU AU73091/96A patent/AU7309196A/en not_active Abandoned
- 1996-10-01 WO PCT/GB1996/002461 patent/WO1997013324A1/en not_active Application Discontinuation
- 1996-10-01 JP JP09514085A patent/JP2000513511A/en active Pending
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US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5357153A (en) * | 1993-01-28 | 1994-10-18 | Xilinx, Inc. | Macrocell with product-term cascade and improved flip flop utilization |
GB2279186A (en) * | 1993-06-16 | 1994-12-21 | Daiichi Denso Buhin | An electrical connector assembly |
EP0630115A2 (en) * | 1993-06-18 | 1994-12-21 | Pilkington Micro-Electronics Limited | Configurable logic array |
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Also Published As
Publication number | Publication date |
---|---|
CN1203706A (en) | 1998-12-30 |
AU7309196A (en) | 1997-04-28 |
JP2000513511A (en) | 2000-10-10 |
CA2235927A1 (en) | 1997-04-10 |
GB9620362D0 (en) | 1996-11-13 |
GB2305759A (en) | 1997-04-16 |
EP0853840A1 (en) | 1998-07-22 |
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