WO1997012444B1 - Programmable logic device with configurable power supply - Google Patents
Programmable logic device with configurable power supplyInfo
- Publication number
- WO1997012444B1 WO1997012444B1 PCT/US1996/015075 US9615075W WO9712444B1 WO 1997012444 B1 WO1997012444 B1 WO 1997012444B1 US 9615075 W US9615075 W US 9615075W WO 9712444 B1 WO9712444 B1 WO 9712444B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- verify
- programming
- circuit
- control gate
- Prior art date
Links
Abstract
An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexer that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.
Claims
1. A programmable logic device (PLD) comprising: a flash storage transistor having a control gate, a source terminal, and a drain terminal, the storage transistor having a programmable threshold voltage; a programming voltage supply providing a programming voltage to the storage transistor, the programming voltage supply including a programming voltage generator; a configurable verify-voltage generator providing a verify voltage to the control gate of the storage transistor, wherein the verify-voltage generator further comprises a plurality of memory elements, wherein the memory elements are programmable to select one of a plurality of verify voltage levels; a switch coupled to the programming voltage supply, the verify-voltage generator, and the control gate, the switch for providing either of the programming voltage or the verify voltage to the control gate; and a verify sense amplifier coupled to the source and drain terminals of the storage transistor, the sense amplifier indicating whether current passes through the storage transistor when the verify voltage is applied to the gate of the storage transistor.
2. (Amended) An integrated circuit comprising: a memory cell having a control gate, a source terminal, and a drain terminal, the memory cell having a programmable threshold voltage; a programming voltage supply for providing a programming voltage to the control gate; and a configurable verify-voltage generator for providing a verify voltage to the control gate, wherein the verify- voltage generator is capable of providing a plurality of voltage levels for testing whether the cell is programmed.
2 6
3. The circuit of Claim 2, further comprising a switch coupled to the programming voltage supply, the verify-voltage generator, and the control gate, the switch for providing either of the programming voltage or the verify voltage to the control gate.
4. The circuit of Claim 2, further comprising a verify sense amplifier coupled to the source and drain terminals.
5. The circuit of Claim 2, wherein the programming voltage supply comprises a programming voltage generator.
6. The circuit of Claim 5, wherein the programming voltage generator is capable of providing a plurality of programming voltage levels.
7. The circuit of Claim 6, wherein the programming- voltage generator further comprises a plurality of programmable memory elements, wherein the elements are programmable to select one of the plurality of programming voltage levels.
8. The circuit of Claim 7, wherein the memory elements are flash memory cells.
9. (Amended) The circuit of Claim 2, wherein the programming voltage supply comprises a pin, wherein the programming voltage is supplied to the integrated circuit through the pin by an external power supply.
10. The circuit of Claim 2, wherein the verify-voltage generator further comprises a plurality of programmable memory elements, wherein the elements are programmable to select one of the plurality of voltage levels for testing whether the cell is programmed.
11. (Amended) The circuit of Claim 3, wherein the programming voltage supply comprises: a voltage selector connected to the switch; a pin coupled to the switch, wherein an external voltage is supplied to the integrated circuit through the pin by an external power supply; and a high-voltage detector coupled between the pin and the voltage selector, the high-voltage detector having a high-voltage threshold.
12. (Amended) The circuit of Claim 11, wherein if the external voltage is less than the high-voltage threshold, the voltage selector selects the external voltage as a verify voltage.
13. (Amended) The circuit of Claim 11, wherein if the external voltage is greater than the high-voltage threshold, the voltage selector selects the verify-voltage generator to provide a verify voltage.
2 8
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9513509A JPH11512899A (en) | 1995-09-25 | 1996-09-18 | Programmable logic device with configuration specific power supply |
| EP96935873A EP0852848A1 (en) | 1995-09-25 | 1996-09-18 | Programmable logic device with configurable power supply |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/533,131 | 1995-09-25 | ||
| US08/533,131 US5661685A (en) | 1995-09-25 | 1995-09-25 | Programmable logic device with configurable power supply |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO1997012444A1 WO1997012444A1 (en) | 1997-04-03 |
| WO1997012444B1 true WO1997012444B1 (en) | 1997-04-24 |
| WO1997012444A9 WO1997012444A9 (en) | 1998-05-28 |
Family
ID=24124620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1996/015075 WO1997012444A1 (en) | 1995-09-25 | 1996-09-18 | Programmable logic device with configurable power supply |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5661685A (en) |
| EP (1) | EP0852848A1 (en) |
| JP (1) | JPH11512899A (en) |
| WO (1) | WO1997012444A1 (en) |
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| US6175952B1 (en) * | 1997-05-27 | 2001-01-16 | Altera Corporation | Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions |
| US6025737A (en) * | 1996-11-27 | 2000-02-15 | Altera Corporation | Circuitry for a low internal voltage integrated circuit |
| US6118302A (en) * | 1996-05-28 | 2000-09-12 | Altera Corporation | Interface for low-voltage semiconductor devices |
| US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
| US5821776A (en) * | 1997-01-31 | 1998-10-13 | Actel Corporation | Field programmable gate array with mask programmed analog function circuits |
| US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
| JP3087839B2 (en) * | 1997-08-28 | 2000-09-11 | 日本電気株式会社 | Semiconductor device and test method thereof |
| US5898618A (en) * | 1998-01-23 | 1999-04-27 | Xilinx, Inc. | Enhanced blank check erase verify reference voltage source |
| US6150835A (en) * | 1998-05-08 | 2000-11-21 | Intel Corporation | Method and apparatus for fast production programming and low-voltage in-system writes for programmable logic device |
| US6232893B1 (en) * | 1998-05-27 | 2001-05-15 | Altera Corporation | Method and apparatus for programmably providing a power supply voltage to an integrated circuit |
| US5889701A (en) * | 1998-06-18 | 1999-03-30 | Xilinx, Inc. | Method and apparatus for selecting optimum levels for in-system programmable charge pumps |
| KR100287545B1 (en) * | 1998-09-17 | 2001-04-16 | 윤종용 | Nonvolatile Semiconductor Memory Devices |
| US6327183B1 (en) | 2000-01-10 | 2001-12-04 | Advanced Micro Devices, Inc. | Nonlinear stepped programming voltage |
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| US7936184B2 (en) * | 2006-02-24 | 2011-05-03 | Altera Corporation | Apparatus and methods for adjusting performance of programmable logic devices |
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| US8987868B1 (en) | 2009-02-24 | 2015-03-24 | Xilinx, Inc. | Method and apparatus for programmable heterogeneous integration of stacked semiconductor die |
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| US9015023B2 (en) | 2010-05-05 | 2015-04-21 | Xilinx, Inc. | Device specific configuration of operating voltage |
| CN102298959B (en) * | 2010-06-24 | 2015-10-21 | 中兴通讯股份有限公司 | Programmable logic device (PLD) and access method thereof |
| US9000490B2 (en) | 2013-04-19 | 2015-04-07 | Xilinx, Inc. | Semiconductor package having IC dice and voltage tuners |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4896296A (en) * | 1985-03-04 | 1990-01-23 | Lattice Semiconductor Corporation | Programmable logic device configurable input/output cell |
| JP2709751B2 (en) * | 1990-06-15 | 1998-02-04 | 三菱電機株式会社 | Nonvolatile semiconductor memory device and data erasing method thereof |
| KR960002006B1 (en) * | 1991-03-12 | 1996-02-09 | 가부시끼가이샤 도시바 | Eeprom with write/verify controller using two reference levels |
| US5237218A (en) * | 1991-05-03 | 1993-08-17 | Lattice Semiconductor Corporation | Structure and method for multiplexing pins for in-system programming |
| US5428568A (en) * | 1991-10-30 | 1995-06-27 | Mitsubishi Denki Kabushiki Kaisha | Electrically erasable and programmable non-volatile memory device and a method of operating the same |
| US5452229A (en) * | 1992-12-18 | 1995-09-19 | Lattice Semiconductor Corporation | Programmable integrated-circuit switch |
| KR960000616B1 (en) * | 1993-01-13 | 1996-01-10 | 삼성전자주식회사 | Non-volatile semiconductor memory device |
| US5463586A (en) * | 1993-05-28 | 1995-10-31 | Macronix International Co., Ltd. | Erase and program verification circuit for non-volatile memory |
-
1995
- 1995-09-25 US US08/533,131 patent/US5661685A/en not_active Expired - Lifetime
-
1996
- 1996-09-18 WO PCT/US1996/015075 patent/WO1997012444A1/en not_active Application Discontinuation
- 1996-09-18 EP EP96935873A patent/EP0852848A1/en not_active Withdrawn
- 1996-09-18 JP JP9513509A patent/JPH11512899A/en active Pending
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