WO1996041271A1 - Arbitre de bus programmable comprenant des champs indicateurs de priorite en temps reel pour la selection d'une priorite d'arbitrage - Google Patents
Arbitre de bus programmable comprenant des champs indicateurs de priorite en temps reel pour la selection d'une priorite d'arbitrage Download PDFInfo
- Publication number
- WO1996041271A1 WO1996041271A1 PCT/US1996/009756 US9609756W WO9641271A1 WO 1996041271 A1 WO1996041271 A1 WO 1996041271A1 US 9609756 W US9609756 W US 9609756W WO 9641271 A1 WO9641271 A1 WO 9641271A1
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- real time
- bus
- request
- master
- coupled
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
Definitions
- This invention relates to bus arbitration within computer systems and, more particularly, to a computer system having an improved bus arbiter for arbitrating bus accesses of a CPU, real time DSP hardware, and other system resources.
- Computer architectures generally include a plurality of devices interconnected by one or more buses.
- conventional computer systems typically include a CPU coupled through bridge logic to a main memory.
- the bridge logic also typically couples to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus.
- PCI Peripheral Component Interconnect
- VESA Video Electronics Standards Association
- Modern local bus standards such as the PCI bus and the VL bus are not constrained by a requirement to be backwards compatible with prior expansion bus adapters and thus provide much higher throughput than older expansion buses.
- Examples of devices which can be coupled to local expansion buses include SCSI adapters, network interface cards, video accelerators, audio cards, telephony cards, etc.
- An older-style expansion bus may also be coupled to the local expansion bus to provide compatibility with earlier-version expansion bus adapters.
- expansion buses include the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, and the microchannel architecture (MCA) bus.
- ISA industry standard architecture
- EISA extended industry standard architecture
- MCA microchannel architecture
- Various devices may be coupled to this second expansion bus, including a fax/modem, sound card, etc.
- a CPU local bus arbiter as well as a PCI bus arbiter are typically included as part of the bridge logic in many computer systems.
- the CPU local bus arbiter determines and prioritizes ownership of the CPU local bus, while the PCI bus arbiter determines and prioritizes ownership of the PCI bus. Mastership of either bus is typically based on a fixed arbitration fairness scheme, such as a round-robin algorithm. In some situations, a master must acquire ownership of both the PCI bus and the CPU local bus before it can proceed with a particular transfer cycle.
- Computer systems were originally developed for business applications including word processing and spreadsheets, among others. Recently, computer systems have evolved toward more real time applications, including multimedia applications such as video and audio, video capture and playback, telephony, and speech recognition. Computer systems originally designed for business applications, however, are not well suited for the real time requirements of modern multimedia applications for a variety of reasons. For example, current operating systems for personal computers are not real time operating systems. In addition, the bus architecture of modern personal computer systems still presumes that the majority of applications executing on the computer system are non-real time, business applications such as word processing and/or spreadsheets which are executed solely by the main CPU.
- bus arbiter which arbitrates between real time resources, non-real time resources and the CPU is typically designed to provide the CPU with maximum availability to the system memory, or is otherwise not cognizant of the real time accesses of other bus mastering devices.
- Real time devices can accordingly be "starved" for memory access, particularly when a relatively large number of real time devices are included within the system. This can correspondingly result in degraded performance, unsynchronized audio and video, and the dropping of frames during video or animation sequences. Therefore, a new bus arbiter system and method are desirable which provide greater access to the bus subsystems and main memory for real time devices to thus better facilitate real time applications.
- a programmable bus arbiter in accordance with the present invention, includes a plurality of arbitration priority registers each having a real time field for arbitration priority selection.
- Each real time bus master is associated with a designated real time field within the bus arbiter.
- Each real time field includes a real time access bit indicative of whether a real time access is to be initiated by the associated master and a priority code which sets the arbitration priority for the master with respect to other masters which may contend for the bus.
- the real time field for a particular master may be programmed to indicate the real time transfer as well as to set the priority level for the request.
- a bus arbitration state machine detects the real time fields and grants bus mastership to real time bus agents in favor of other contending bus requests by non-real time agents.
- the bus arbiter is incorporated within a bus bridge coupled between a CPU local bus and a PCI bus.
- the bus arbiter prioritizes and controls ownership of the PCI bus.
- the bus bridge may further include memory controller logic for controlling data transfers between a main memory and masters residing on either the CPU local bus or the PCI bus.
- a variety of peripheral devices are coupled to the PCI bus, including both real time resources and non-real time resources.
- a SCSI controller for example, in one configuration a SCSI controller, a network interface card, a video adapter, a video capture card, an audio adapter, and a telephony adapter are coupled to the PCI bus.
- the system is capable of supporting numerous real time processing resources while maintaining proper overall operation.
- Figure 1 is a block diagram of a computer system including a variety of real time resources and a bus arbiter in accordance with the present invention.
- Figure 2 is a block diagram which depicts internal portions of the bus arbiter of Figure 1.
- Figure 3 is a diagram which illustrates the real time priority indicator fields associated with the bus arbiter of Figure 2.
- the computer system includes a central processing unit (CPU) 102 which is coupled through a CPU local bus 104 to a host/PCI/cache bridge 106.
- the bridge 106 includes memory control logic and is coupled through a memory bus 108 to a main memory 110.
- a cache memory subsystem (not shown) may further be coupled to bus bridge 106.
- Bus bridge 106 also interfaces to a peripheral component interconnect (PCI) bus 120.
- PCI bus 120 Further details regarding PCI bus 120 may be found within the publication "PCI Local Bus Specification”; Revision 2.0; April 30, 1993; PCI Special Interest Group; Hillsboro, Oregon. This publication is incorporated herein by reference in its entirety. It is noted that other local buses could be alternatively employed, such as the VESA (Video Electronics Standards Association) VL bus.
- PCI bus 120 peripheral component interconnect
- CPU 102 is illustrative of, for example, an x86 microprocessor such as an 80486 microprocessor or a Pentium-compatible microprocessor. It is understood, however, that a system according to the present invention may employ other types of microprocessors. It is further understood that the present invention may be employed within a multiprocessing environment.
- a video adapter 170 for controlling video functions is coupled to PCI bus 120.
- Other real time DSP devices are also preferably coupled to the PCI bus, including an audio adapter 172, a telephony adapter 174, and a video capture board 176, among others.
- a SCSI (small computer systems interface) disk controller 122 and a network interface card 140 are additionally shown coupled to the PCI bus 120.
- SCSI controller 122 is configured to provide an interface to SCSI devices such as a CD-ROM device, a tape drive device, and/or a composite disk array.
- the network interface card 140 interfaces to a local area network (LAN) 142.
- LAN local area network
- An expansion bus bridge 150 is also preferably coupled to the PCI bus 120.
- the expansion bus bridge 150 interfaces to an expansion bus 152.
- the expansion bus 152 may be any of a variety of types, including the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, or the microchannel architecture (MCA) bus.
- ISA industry standard architecture
- EISA extended industry standard architecture
- MCA microchannel architecture
- Various devices may be coupled to the expansion bus 152, including expansion bus memory 154 and a modem 156.
- a bus arbiter 180 configured to control ownership of PCI bus 120 is illustrated as a portion of bus bridge 106 .
- the arbitration scheme employed by the computer system of Figure 1 provides a unique request signal REQ# and grant signal GNT# for each PCI master. When a particular master requires ownership of PCI bus 120, it asserts its associated request signal REQ#.
- bus arbiter 180 is configured to allow selected bus request channels to be programmed as real time bus requests. Real time bus requests are given a higher priority for bus access in comparison to non-real time bus requests.
- the bus arbiter 180 may further be programmed to provide differing priority levels for different real time masters. In accordance with the arbitration mechanism provided by bus arbiter 180, non-real time masters will lose an arbitration for PCI bus 120 to real time masters. Further details regarding bus arbiter 180 will be provided further below in conjunction with Figures 2 and 3.
- each bus master of Figure 1 asserts a unique request signal REQ# when bus access is desired.
- These request signals (shown collectively as REQ[7:0]) are routed to bus arbiter 180.
- request signal REQ2 is generated by video adapter 170
- request signal REQ5 is generated by telephony adapter 174.
- Corresponding grant signals GNT[7:0] are similarly routed back to the masters from bus arbiter 180 to indicate the current owner of PCI bus 120.
- request signal REQ4 may be asserted by expansion bus bridge 150 if access of PCI bus 120 is required by an agent of expansion bus 152, such as modem 156.
- each request signal/grant signal pair is referred to as a bus request channel.
- FIG. 2 is a diagram that depicts internal portions of bus arbiter 180.
- bus arbiter 180 includes an arbitration state machine 202 coupled to a request detection unit 204, a grant generator 208 and programmable arbitration priority registers 210.
- a decoder 212 is additionally shown coupled to programmable arbitration priority registers 210.
- Programmable arbitration priority registers 210 are provided to allow a particular bus request channel to be designated as a real time channel. Programmable arbitration priority registers 210 are further provided to set the arbitration priority associated with the processing of real time bus requests by arbitration state machine 202.
- Figure 3 is a diagram that illustrates a plurality of real time fields 300 included within the programmable arbitration priority registers 210. Each real time field 300 includes a real time access bit and a priority code. Decoder 212 is provided to allow software programming of each real time field 300. It is noted that in this implementation, a separate real time field 300 is provided for (i.e., is associated with) each request signal REQ[7:0].
- the real time access bit associated with a particular request signal REQ# may be cleared if the master corresponding to the request signal REQ# is going to initiate a non-real time data transfer, and may be set if the master is going to perform a real time data transfer.
- the priority code may further be set to select the arbitration priority level to be associated with a particular master.
- Arbitration state machine 202 is configured to transition between several bus arbitration states depending upon assertions of the bus request signals REQ[7:0] detected by request detection unit 204 . Transitions between the various arbitration states of arbitration state machine 202 are further dependent upon values stored within the real time fields 300.
- arbitration state machine 202 is configured to provide the lowest level of arbitration priority to any request signals REQ# which do not have an associated real time access bit set. Thus, any contending request signal REQ# having an associated real time access bit set will gain access to the bus in favor of any non-real time requests. In one embodiment, contending non-real time requests are handled by state machine 202 in a round-robin fashion.
- the priority code associated with a particular real time priority indicator field sets the priority for contending real time requests.
- Priority code "00" is given the lowest priority, while priority code "11" is given the highest priority.
- a contending request by the master asserting the request signal REQ6 will win over a contending request of any of the other masters.
- a bus request by the master asserting request signal REQ1 will win over a bus request of the master asserting request signal REQ4, but will lose to a contending request by the master asserting request signal REQ5.
- the same priority code is given to more than one contending request signal REQ#, such contending bus requests are treated in a round-robin manner after any higher priority real time requests have been serviced.
- bus arbiter 180 ensures that real time requests are serviced expeditiously. Accordingly, a relatively large number of real time devices may be employed within the computer system while maintaining proper overall operation. The system further allows differentiation in bus arbitration priorities for differing bus masters, as desired.
- bus requests of a particular bus agent to be designated at one time during the operation as a non-real time master and at other times of operation as a real time master.
- request signal REQ7 is associated with requests invoked by bridge 106 in response to cycles initiated by CPU 102.
- the system programmer may cause the real time access bit associated with request signal REQ7 to be cleared, thus indicating a non-real time data transfer.
- arbitration state machine 202 provides a higher priority to the subsequent real time transfers in comparison to that provided for the earlier non-real time transfer.
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Abstract
On décrit un arbitre de bus programmable comportant une pluralité de registres de priorité d'arbitrage possédant chacun un champ en temps réel destiné à une sélection de priorité d'arbitrage. Chaque maître bus en temps réel est associé à un champ en temps réel désigné dans l'arbitre de bus. Chaque champ en temps réel comprend un bit d'accès en temps réel indiquant si un accès en temps réel doit être amorcé par le maître associé, ainsi qu'un code de priorité établissant la priorité d'arbitrage du maître par rapport aux autres maîtres qui peuvent être en conflit pour la priorité d'accès au bus. Avant de commencer un transfert de données en temps réel, le champ en temps réel d'un maître en particulier peut être programmé afin d'indiquer le transfert en temps réel ainsi que le niveau de priorité destiné à la demande. Un automate fini d'arbitrage de bus détecte les champs en temps réel et accorde une maîtrise de bus à des agents de bus en temps réels pour satisfaire d'autres demandes de bus en conflit, émises par des agents en temps non réel.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US47978195A | 1995-06-07 | 1995-06-07 | |
US08/479,781 | 1995-06-07 |
Publications (1)
Publication Number | Publication Date |
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WO1996041271A1 true WO1996041271A1 (fr) | 1996-12-19 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US1996/009756 WO1996041271A1 (fr) | 1995-06-07 | 1996-06-07 | Arbitre de bus programmable comprenant des champs indicateurs de priorite en temps reel pour la selection d'une priorite d'arbitrage |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0854614A2 (fr) * | 1996-12-30 | 1998-07-22 | Compaq Computer Corporation | Système d'arbitrage programmable pour déterminer la priorité de ports d'un commutateur de réseau |
US6189061B1 (en) | 1999-02-01 | 2001-02-13 | Motorola, Inc. | Multi-master bus system performing atomic transactions and method of operating same |
WO2001048617A2 (fr) | 1999-12-28 | 2001-07-05 | Intel Corporation | Logique de mise en ordonnancement des demandes bus par ordre de priorite pour processeurs |
Citations (1)
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WO1993016434A1 (fr) * | 1992-02-13 | 1993-08-19 | Tandy Corporation | Procede et appareil destine a reduire la servitude d'entrelacement d'un bus d'un systeme informatique |
-
1996
- 1996-06-07 WO PCT/US1996/009756 patent/WO1996041271A1/fr active Application Filing
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WO1993016434A1 (fr) * | 1992-02-13 | 1993-08-19 | Tandy Corporation | Procede et appareil destine a reduire la servitude d'entrelacement d'un bus d'un systeme informatique |
Non-Patent Citations (1)
Title |
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6389480B1 (en) | 1996-12-30 | 2002-05-14 | Compaq Computer Corporation | Programmable arbitration system for determining priority of the ports of a network switch |
EP0854614A3 (fr) * | 1996-12-30 | 1999-06-16 | Compaq Computer Corporation | Système d'arbitrage programmable pour déterminer la priorité de ports d'un commutateur de réseau |
US6098109A (en) * | 1996-12-30 | 2000-08-01 | Compaq Computer Corporation | Programmable arbitration system for determining priority of the ports of a network switch |
EP0854614A2 (fr) * | 1996-12-30 | 1998-07-22 | Compaq Computer Corporation | Système d'arbitrage programmable pour déterminer la priorité de ports d'un commutateur de réseau |
US6189061B1 (en) | 1999-02-01 | 2001-02-13 | Motorola, Inc. | Multi-master bus system performing atomic transactions and method of operating same |
WO2001048617A3 (fr) * | 1999-12-28 | 2002-01-31 | Intel Corp | Logique de mise en ordonnancement des demandes bus par ordre de priorite pour processeurs |
WO2001048617A2 (fr) | 1999-12-28 | 2001-07-05 | Intel Corporation | Logique de mise en ordonnancement des demandes bus par ordre de priorite pour processeurs |
US6499090B1 (en) | 1999-12-28 | 2002-12-24 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US6606692B2 (en) | 1999-12-28 | 2003-08-12 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US6782457B2 (en) | 1999-12-28 | 2004-08-24 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US7133981B2 (en) | 1999-12-28 | 2006-11-07 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US7487305B2 (en) | 1999-12-28 | 2009-02-03 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
EP2157515A1 (fr) * | 1999-12-28 | 2010-02-24 | Intel Corporation | Mécanisme de planification priorisée des demandes de bus pour dispositifs de traitement |
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