WO1996038914A1

WO1996038914A1 - Semiconductor integrated circuit device and signal processor

Info

Publication number: WO1996038914A1
Application number: PCT/JP1995/001084
Authority: WO
Inventors: Haruo Kamimaki; Yuji Hatano; Koichi Ono; Masanori Otsuka; Mitsuru Hiraki
Original assignee: Hitachi, Ltd.
Priority date: 1995-06-02
Filing date: 1995-06-02
Publication date: 1996-12-05

Abstract

A CMOS logic circuit which efficiently uses the relatively high power supply voltage of the system and consumes less electric power. The CMOS circuit is divided into a plurality of circuit blocks (5 and 6) and is formed on layers so as to divide the power supply voltage. A power supply voltage stabilizing unit (1) is provided for each layer and level converting circuits (7 and 8) for transferring signals. The power consumption of a system requiring a relatively high power supply voltage can be reduced without increasing the circuit scale by using a low-voltage CMOS logic circuit constituted of random logics, etc.

Description

Description Semiconductor integrated circuit device and signal processing device

The present invention relates to a CMOS logic circuit that operates at a low voltage. In particular, a power supply voltage supplied to a semiconductor integrated circuit that constitutes a logic circuit is high, and the power supply voltage is divided so that a CM〇S logic circuit can be operated at a low voltage. Related to operating technology. Background art

Conventionally, when a plurality of circuit blocks are configured using a plurality of semiconductor integrated circuits (LSIs) on a single printed circuit board, the power supply voltage of the circuit requires the highest power supply voltage in the system. It is supplied according to the voltage of.

FIG. 25 shows the configuration of a general mobile phone. In the figure, reference numeral 236 denotes an antenna for receiving or transmitting a radio signal, reference numeral 235 denotes a modulation / demodulation circuit for demodulating a high-frequency signal from the antenna, and reference numeral 234 denotes audio coding / decoding for encoding / decoding an audio signal. AZD, D / A converter for converting a digital signal from an audio encoding / decoding circuit into an analog signal or an analog signal into a digital signal, and 230 for AZD, DZA A speaker that reproduces the output of the converter and a microphone 23 that captures the audio signal to be transmitted are shown. Although not particularly limited, AZD, D ZA converter

2 32 2, the voice coding and decoding circuit 2 3 4 and the modulation and demodulation circuit 2 3 5 are each composed of a semiconductor integrated circuit device and mounted on a printed circuit board. The system power supply voltage ( Power supply potential 2 3 7 and ground potential 2

3 8 have been supplied.

In such a system, the system power supply voltage (237, 238) is configured so that the highest power supply voltage in the system is supplied in accordance with the required circuit block. For example, in the figure, the AZD and DZA converters 232 that currently operate at a power supply voltage of 3 V have been put into practical use, and it is thought that further lowering of the voltage is possible. Also, the CM〇S logic circuit such as the voice encoding / decoding circuit 2 3 4 operates at 3 V at present. Research and development is also underway on V operation, and it can operate at voltages lower than 3 V even at this stage. However, the high-frequency radio circuit 235 is not practical at 3 V or less from the viewpoint of its radio performance rather than circuit technology. In addition, since miniaturization is an important factor in mobile phones, it is desirable to use only one kind of power supply voltage in order to minimize the circuit scale. Therefore, in these systems, 3 V required for the high-frequency radio circuit 235 is supplied to the power supply voltage 237 (operating potential point of the system), and the ground is connected to 238 (operating potential point of the system). In this case, all circuits operate, and even circuit blocks that can be operated at relatively low operating voltages are disadvantageous in that they receive high power supply voltages due to circuit blocks that require high power supply voltages. Has occurred. On the other hand, as a conventional technique for efficiently using a power supply voltage by dividing a power supply voltage of a circuit, a technique of stacking IIL logic circuits using bipolar transistors is disclosed in Japanese Patent Laid-Open No. 50-7882. No. 68 (Prior Art 1), Japanese Patent Application Laid-Open No. 62-105463 (Prior Art 2), Japanese Patent Application Laid-open No. 62-25070 Gazette (Prior art 3), Japanese Patent Laid-Open No. 4-10972 (Prior art 4), Japanese Patent Laid-Open No. 4-315153 (Prior art 5) and "Low-Power On-Chip" A supply voltage conversion scheme for Ultrahigh-Density DRAM's "(IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, No. 4, APRIL 1993) (prior art 6) is known. Disclosure of the invention

In recent years, development of portable terminals and the like requires low power consumption as well as system miniaturization. As a means for reducing power consumption, a technique for reducing the power consumption of each circuit block using a low-voltage circuit is widely used, but as described above, there are circuits in the system that cannot reduce the voltage. In this case, even the CM〇S logic circuit that can lower the voltage in the system cannot lower the voltage. Also, preparing multiple system power supply voltages is a factor that hinders miniaturization of the system.

On the other hand, although the above-described conventional technologies are known, the technology of laminating bipolar transistor circuits as in the conventional technology 1 is directly applied to a CMOS circuit in which a pulse-like through current flows through the circuit. Can not do. Through current flow rate Is not constant, and the power supply voltage (potential difference) between the layers cannot be kept constant.

In addition, even in a circuit using MOS as in the prior art 6, even if the stacked upper and lower layers have a substantially constant current amount like a memory such as DRAM (dynamic random access memory). If the circuit is a circuit, it is possible to use a relatively low power supply voltage by laminating the circuits and dividing the system power supply voltage between each layer.However, in logic circuits such as processors and random logic circuits, it is necessary to divide the power supply voltage by means of power supply division means. A circuit for stabilizing the obtained voltage is required.

In the remaining conventional technology, the power supply is divided by a voltage follower, and the power consumption of the power supply dividing circuit increases, which may hinder the initial purpose of reducing power consumption.

Furthermore, in these conventional techniques, it is assumed that the circuits arranged in each layer operate in parallel, and the result of the processing in each layer is directly output as the power supply level amplitude, such as a processor circuit. Circuits that need to exchange signals between circuits arranged in each layer are not considered.

The present invention maintains the miniaturization of a CMOS logic circuit capable of operating at a low voltage even when there is a circuit capable of operating at a low voltage in the same system as a CMOS logic circuit capable of operating at a low voltage. Another object of the present invention is to provide a means for enabling low-voltage operation while performing a low-voltage operation, such as a processor circuit, in a circuit that requires transmission and reception of signals between CM〇S logic circuits. (In addition, for the sake of simplicity of description, the following MOS will be described as including a MIS using a gate insulating film other than an oxide film.)

A semiconductor integrated circuit according to a representative embodiment of the present invention includes:

A first operating potential (for example, 3.0 V) and a second operating potential (for example, 0.0 V) are supplied, and the first operating potential and the second operating potential are different from both potentials. A power supply division unit (1) that outputs an operating potential (for example, 1.5 V) of the third operating potential, and operates between the first operating potential and the third operating potential. A first logic circuit (5) configured between the third operating potential and the second operating potential, and a second logic circuit (6) configured by complementary field-effect transistors. ) And a level conversion circuit (?) For converting the amplitude of the output signal of the first logic circuit and inputting the converted signal to the second logic circuit.

This makes it possible to rationally configure a logic circuit that operates from a relatively high external power supply voltage to a relatively low power supply voltage. Further, by having a level conversion circuit between the first logic circuit and the second logic circuit, signals can be exchanged between the logic circuits having different amplitudes.

A semiconductor integrated circuit according to another representative embodiment of the present invention further includes:

It has a third logic circuit (10) connected to the first operating potential and the second operating potential.

Thus, even when there is a logic circuit requiring a relatively high power supply voltage, each logic circuit can coexist on a single semiconductor substrate.

A semiconductor integrated circuit according to another representative embodiment of the present invention includes:

The power supply division unit is configured to include means (19) for detecting a third potential and means (14) for correcting a third operating potential. This makes it possible to stably supply the third operating potential constituting the internal power supply voltage.

The level conversion circuit includes a level shift means (71, 72) for shifting the level of the output signal of the first logic circuit, and a latch circuit (70) for receiving the output signal via the level shift means. ), Wherein the latch circuit is configured to operate between the third operating potential and the second operating potential. As described above, according to the present invention, a level conversion circuit that connects the first logic circuit and the second logic circuit can be realized with a relatively simple circuit configuration.

A third operating potential point (103), which is connected to the first operating potential point (2) and the second operating potential point (4) and supplies a potential different from the potentials of the two operating potential points, and a fourth operating potential point (104). Power supply division unit (101) including the operating potential point (104), and a first logic circuit (105) connected to the first operating potential point and the third operating potential point. ), A second logic circuit (106) connected to the third operating potential point and the fourth operating potential point, and a second logic circuit (106) connected to the fourth operating potential point and the second operating potential point. Connected third logical times (107), a first level conversion circuit (108) connected between the first logic circuit and the second logic circuit, a second logic circuit and the third logic circuit, And a second level conversion circuit (109) connected between the first logic circuit and the fourth logic circuit. The first level conversion circuit outputs the output signal of the first logic circuit to the third operating potential point and the fourth The second level conversion circuit converts the output signal of the second logic circuit into an amplitude corresponding to the fourth operating potential point and the second operating potential point. Is configured to be converted to

As described above, according to the present invention, it is possible to configure the logic circuit by dividing the external power supply voltage into three or more. Also, a level conversion circuit is provided for transmitting and receiving signals between the layers.

The power supply unit is divided into a first potential difference, which is a potential difference between the first operating potential point (2) and the fourth (104) operating potential point, a first operating potential point (2), and the first operating potential point (2). (3) a first comparison circuit (124) for detecting a second potential difference, which is a potential difference from the operating potential point (103), and comparing a half value of the first potential difference with the second potential difference; A third potential difference, which is a potential difference between the third operating potential point and the second operating potential point, and a fourth potential difference, which is a potential difference between the third operating potential point and the second operating potential point. A second comparison circuit (125) for detecting and comparing a half value of the third potential difference with the fourth potential difference, and the third and second comparison circuits based on a comparison result of the first and second comparison circuits. 4 is configured to correct the potential at the operating potential point. Thus, the potential of each operating potential point can be stably maintained, and each operating potential can be detected with a small number of voltage comparison circuits.

A power supply dividing unit (101) is connected to a control circuit (170) that outputs a control signal stored in advance at a predetermined timing, receives a control signal of the control circuit at its gate electrode, and connects each operating potential point. And a transistor connected to the transistor (171), and configured to control the amount of current flowing through the transistor by the control signal. This makes it possible to correct the amount of current in each layer and stabilize the intermediate potential with a simple configuration when the amount of current in the logic circuit in each layer is known in advance. A semiconductor integrated circuit according to another representative embodiment of the present invention includes:

A first circuit group that operates at a first amplitude corresponding to the external power supply voltage, a circuit that divides the external power supply voltage to generate at least three internal power supply voltages, and a first circuit group that supports the three internal power supply voltages. A second, a third, and a fourth circuit group operating at an amplitude of 2, a third amplitude, and a fourth amplitude; and a bus related to signal transmission between the circuit groups, and the first circuit. The group includes an interface circuit (205) that receives a signal from the outside and supplies the signal to the bus. The third circuit group is connected to the bus, and connected via the bus. It has an operation unit (203) for performing a predetermined operation on received data. By configuring a microprocessor or the like in this way, a logic circuit that operates at a low voltage inside while maintaining an interface with the outside can be used. In addition, by configuring the arithmetic unit that frequently accesses the bus with a circuit having the third amplitude, an efficient configuration can be achieved without using an extra level conversion circuit.

A semiconductor integrated circuit according to another representative embodiment according to the present invention includes:

In the first circuit group, a memory cell array (201) constituting a memory for temporarily storing data supplied from the outside and a memory cell array I ^ (200) constituting a memory for storing a program are stored. 2) and As a result, the memory array can be operated at a so-called full amplitude, and stable storage of information becomes possible.

The third circuit group includes a sense amplifier circuit (208) for amplifying an output of a memory cell array constituting a memory for storing data supplied from the outside and supplying the amplified signal to the bus. By configuring a sense amplifier circuit that only outputs information to the bus in the third circuit group, an efficient circuit configuration can be achieved without the need to provide a level conversion circuit.

The fourth circuit group has an instruction decoder (206) for decoding a program stored in the memory, and an output of the instruction decoder is a level conversion circuit for converting the amplitude thereof. It is configured to be output to the above bus via 2 16). And By arranging the instruction decoder circuit in the fourth circuit group, it is possible to prevent the circuits from being concentrated on a specific circuit group (layer).

An addressing unit (204) for designating an address of the memory based on a signal transmitted through the bus to the second circuit group; and an address decoder (209) for receiving an output of the addressing unit. ). By arranging the address decoder and the like in the second circuit group, it is possible to prevent the circuits from being concentrated on a specific circuit group (layer).

A typical form of a signal processing device according to the present invention is:

A signal processing device comprising at least a first and a second semiconductor integrated circuit device (234, 235) for supplying an operating potential commonly to the first and second semiconductor integrated circuit devices. The first semiconductor integrated circuit device includes an internal circuit that operates with the first and second operating potentials, and the second semiconductor integrated circuit device includes a first and a second operating potential generating means. The circuit device is configured to have an internal circuit that operates with an operating potential having a potential difference smaller than the potential difference between the first and second operating potentials (237, 238). This makes it possible to efficiently configure a signal processing device in which a semiconductor integrated circuit having a circuit that cannot operate at a low power supply voltage and a semiconductor integrated circuit that can operate at a low power supply voltage coexist efficiently. The power can be reduced.

A signal processing device according to a representative embodiment of the present invention includes:

An antenna (236) connected to the first semiconductor integrated circuit for receiving a radio signal, wherein the first semiconductor integrated circuit device is a modulation circuit for modulating a signal received by the antenna; The second semiconductor integrated circuit device is configured to be a decoding circuit that processes an output signal of the modulation circuit. This makes it possible to efficiently configure a signal processing device including a modulation circuit that is difficult to reduce the power supply voltage and a decoding circuit that can reduce the power supply voltage.

It has a digital-analog converter (232) and a speaker (230), converts the output of the decoding circuit by the digital-analog converter, and operates the speaker based on the conversion result. It is configured to BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a logic circuit which is one embodiment of the present invention.

FIG. 2 is a diagram showing a power split unit which is one mode of the present invention.

FIG. 3 is a diagram showing a control circuit which is one mode of the present invention.

FIG. 4 is a diagram showing a voltage comparison circuit which is one mode of the present invention.

FIG. 5 is a diagram showing a timing circuit which is one mode of the present invention.

FIG. 6 is a diagram showing a dummy gate circuit which is one mode of the present invention.

FIG. 7 is a diagram showing a level conversion circuit which is one mode of the present invention.

FIG. 8 is a diagram showing a level shifter circuit that can be employed in the present invention.

FIG. 9 is a diagram showing another level shifter circuit that can be employed in the present invention.

FIG. 10 is a diagram showing an interlayer level conversion circuit which is one mode of the present invention. The first 1 figure, _t first 2 Figure is a diagram showing another interlayer level converting circuit which is an embodiment of the present invention is a diagram illustrating another inter-level converting circuit which is an embodiment of the present invention _c FIG. 13 is a diagram showing another interlayer level conversion circuit which is an embodiment of the present invention _c . FIG. 14 is a diagram showing another interlayer level conversion circuit which is an embodiment of the present invention _c FIG. 15 is a diagram showing another logic circuit which is one mode of the present invention.

FIG. 16 is a diagram showing another power supply division unit which is an embodiment of the present invention. FIG. 17 is a diagram showing another control circuit which is one mode of the present invention. FIG. 18 is a diagram showing another voltage comparison circuit which is one mode of the present invention.

FIG. 19 is a diagram showing another timing circuit which is one mode of the present invention. FIG. 20 is a diagram showing another dummy gate circuit which is one mode of the present invention. FIG. 21 is a diagram showing another power supply division unit which is an embodiment of the present invention. FIG. 22 is a diagram showing another control circuit which is one mode of the present invention.

FIG. 23 is a diagram showing another dummy gate circuit which is an embodiment of the present invention. FIG. 24 is a diagram showing a signal processing circuit which is one mode of the present invention.

FIG. 25 is a diagram showing a system configuration of a mobile radio telephone. BEST MODE FOR CARRYING OUT THE INVENTION A representative best mode for carrying out the present invention will be described below.

FIG. 1 shows a circuit that divides a power supply voltage into a plurality (here, two) according to the present invention and operates a low screw width logic circuit in a plurality of (here, two) voltage layers. Although not particularly limited, the present circuit is configured as a semiconductor integrated circuit device formed on a single semiconductor substrate, and such a semiconductor integrated circuit device is mounted on a print substrate (wiring substrate) together with other semiconductor devices. is there.

In FIG. 1, reference numeral 1 denotes a power supply dividing unit that divides a power supply potential 2 as a first operating potential point into a ground potential 4 as a second operating potential point, and is mounted on a system or a printed circuit board. The power supply voltage to be supplied to each layer is formed from the power supply potential 2 and the ground potential 4 supplied to the other semiconductor devices (the power supply potential 2 and the ground potential or the potential difference between them for the sake of simplicity of the following description). Are collectively referred to as an external power supply voltage, and the power supply voltage and the like formed by the power supply unit 1 are collectively referred to as an internal power supply voltage). Reference numerals 5 and 6 denote relatively low-amplitude low-amplitude logic circuits that operate on the internal power supply voltage which is approximately 1Z2 of the external power supply voltage formed by the power supply division unit 1. Here, 5 is also called the first low-amplitude logic circuit or the first layer, and 6 is also called the second low-amplitude logic circuit or the second layer. Reference numeral 9 denotes a circuit for level-converting the signals output from the low-amplitude logic circuits 5 and 6 and returning the signals to the full amplitude (the amplitude of the external power supply voltage). In this example, the provision of the level conversion circuit 9 allows a signal having a relatively low amplitude due to the internal power supply voltage to be converted into a signal having a full amplitude corresponding to the external power supply voltage, thereby facilitating the exchange of signals with the outside. . Reference numeral 10 denotes a full amplitude logic circuit which is connected to the external power supply voltage and outputs a full amplitude logic signal corresponding to the external power supply voltage. The interlayer level conversion circuits 7 and 8 output the output of the first low-amplitude logic circuit that operates between the internal power supply voltages 2 and 3, which is set to about 1 external power supply voltage, between the internal power supply voltages 3 and 4. This is a circuit that converts the amplitude when it is input to the second low-amplitude logic circuit that operates in or vice versa. In the present example, such an interlayer level conversion circuit enables signals to be exchanged between the first logic circuit 5 and the second logic circuit 6, and a random logic circuit or the like can be practically formed.

Next, the operation of the logic circuit of this example will be described.

The power supply unit i is connected between the power supply potential 2 which is the external power supply voltage and the ground potential 4. The intermediate potential 3 is formed by dividing the space into two, and the first layer where the first low-amplitude logic circuit is formed by the power supply potential 2 and the intermediate potential 3 is formed, and between the intermediate potential 3 and the ground potential 4 Creating a second layer on which a second low amplitude logic circuit is formed. Further, as described later, the power supply division unit 1 corrects the intermediate potential 3 using the clock 23 and the clock 24 delayed by 14 cycles thereof.

The low-amplitude logic circuits 5 and 6 operating in these two voltage layers receive an input signal 11 from an input terminal, perform logical processing on each of them, and output an output signal 43 or 44. These output signals 43 and 44 are input to the level conversion circuit 9. The level conversion circuit 9 is connected to the power supply potential 2 and the ground potential 4, and converts the output signals 43, 44 output with substantially half the amplitude of the external power supply voltage to the full amplitude of the external power supply voltage and outputs it. The output signal of this level conversion circuit 9 is output as it is to the outside, or is output from the output terminal 12 as an output signal after being subjected to predetermined processing by a full amplitude logic circuit 10 in the figure.

Furthermore, the interlayer level conversion circuits 7 and 8 receive the power supply potential 2, the ground potential 4 and the intermediate potential 3, respectively, and convert the level of the output signal of the first low-amplitude logic circuit 5 to obtain the second low-amplitude logic circuit 6. Also, it works so as to convert the level of the output signal of the second low-amplitude logic circuit 6 and supply it to the first low-amplitude logic circuit 5.

As described above, according to this example, even when the external power supply voltage is relatively large, the power supply voltage can be effectively reduced by providing the power supply division unit, dividing the external power supply voltage, and providing the logic circuits in a stacked manner. It can be used and low-amplitude logic circuits can be used as internal logic circuits, thereby reducing power consumption. In addition, since there is a level conversion circuit that converts the output of the low-amplitude logic circuit to a full amplitude corresponding to the external power supply voltage, the output of the low-amplitude logic circuit can be easily used in an external semiconductor device or the like that operates on the external power supply voltage. Can be used. In addition, by providing a logic circuit that operates at full amplitude at the subsequent stage of the level conversion circuit, the same processing can be performed even when the processing to be performed by the low-amplitude logic circuit and the processing to be performed by the full-amplitude logic circuit are mixed. The processing can be performed in the semiconductor device. In addition, by having an interlayer level conversion circuit between each layer, signals can be exchanged between the layers, and a logic circuit can be arranged on each layer regardless of whether signals are exchanged between the layers. , Efficient circuit design It becomes possible.

Although the low-amplitude logic circuit is formed in two layers in FIG. 1, the present invention is not limited to this, and three or more layers can be used. In this case, it is necessary that the power supply division unit divides the external power supply voltage into three or more and outputs two or more intermediate potentials. Also in this case, it is effective to arrange an interlayer level conversion circuit between each layer.

Next, the power supply division unit 1 of the circuit blocks shown in FIG. 1 will be described. FIG. 2 is a configuration diagram of the power split unit 1.

The power supply division unit 1 includes capacitors 15 and 16 for dividing the power supply potential 2 and the ground potential 4 into two, and a dummy gate 14 and an intermediate potential 3 which are means for correcting the fluctuation of the intermediate potential 3. It consists of a control circuit 13 for observing and making the dummy gate follow the fluctuation. The control circuit 13 observes the intermediate potential 3 and outputs control signals 17 and 18 at the timing obtained from the clock signals 23 and 24 based on the observation result. The internal circuit operates based on, 18 and corrects the value of intermediate potential 3 to a normal value.

Here, the capacitances of the capacitors 15 and 16 are substantially equal, and the value C can be obtained from the following equation 1 based on the average current consumption I, the voltage V divided into two, and the time constant T.

C = (I · T) no V (Equation 1) Hereinafter, the correction of the intermediate potential 3 will be described in detail with reference to FIGS. 3, 4, and 5.

FIG. 3 is a configuration diagram of the control circuit 13.

This control circuit includes a voltage comparator 19 and a timing circuit 20. The voltage comparator 19 observes the intermediate potential 3 and is supplied with the power supply potential 2, the ground potential 4 and the intermediate potential 3, and the potential difference between the power supply potential 2 and the intermediate potential 3 is determined by the intermediate potential 3 and the ground potential. It compares whether it is equal to the potential difference with the potential 4 and outputs the result as signals 21 and 22. The timing circuit 20 outputs the outputs 21 and 22 of the voltage comparator 19 as control signals 17 and 18 for a certain time at a certain timing determined by the clocks 23 and 24, and outputs a dummy gate described later. Control.

FIG. 4 is a configuration diagram of the voltage comparator 19. This voltage comparison circuit is composed of switches 27, 28, 31, 32, capacitors 29, 30 of almost the same capacity, a comparator 25, and a latch circuit 26. In this voltage comparator, first, the switches 27 and 28 are closed, the switch 31 is set to the power supply potential 2 side, the switch 32 is set to the intermediate potential 3 side, and the capacitor 29 is connected between the reference potential of the comparator 25 and the power supply potential 2. The potential difference is stored, and the potential difference between the reference potential and the intermediate potential 3 is stored in the capacitor 30. Next, the switches 27 and 28 are opened, the switch 31 is set to the intermediate potential 3 side, and the switch 32 is set to the ground potential 4 side. As a result, the potential difference between the power supply potential 2 and the intermediate potential 3 and the potential difference between the intermediate potential 3 and the ground potential 4 are input to the comparator 25. At this time, if the potential difference between the power supply potential 2 and the intermediate potential 3 is larger, the output 21 is high, and if the potential difference between the intermediate potential 3 and the ground potential 4 is larger, the output 22 is high. The latch circuit 26 sets the high level of the outputs 21 and 22 to the value of the power supply potential 2 and sets the level of L 0 w to the value of the ground potential 4. According to the configuration of this example, it is possible to compare the power supply voltages of the respective layers and output the result as a signal, and to correct the internal power supply voltage as described later.

FIG. 5 shows a configuration of the timing circuit 20 described in FIG. This timing circuit is composed of a counter 33 that determines the timing of the correction process performed at regular intervals, an AND circuit 34 that determines the output timing and the time, and AND circuits 35 and 36 that output control signals 17 and 18. Is done.

First, the counter 33 counts a fixed number of pulses of the clock 23, and outputs "1" (for example, a high level signal) when the number of pulses reaches a fixed number. This is ANDed by the AND circuit 34 with the clock 23 and the clock 24 to obtain a timing signal 37 which becomes "1" for only 1/4 cycle. The AND circuits 35 and 36 synchronize the voltage comparator outputs 21 and 22 with the timing signal 37 and output them as control signals 17 and 18 having only one to four cycles. With such a configuration, in the present embodiment, it is possible to output control signals 17 and 18 for a fixed period according to the comparison result of the voltage comparator. Voltage fluctuations can be corrected.

FIG. 6 shows voltage correction means for maintaining the power supply voltage of each layer at an appropriate value in this example. This shows the configuration of a certain dummy gate. This dummy gate circuit is the power supply voltage

A current control gate 38 composed of a plurality of MOS transistors (here, NMOS transistors) connected in parallel between 2 and the intermediate potential 3, and connected in parallel between the intermediate potential 3 and the ground potential 4 And a current control gate 39 composed of a plurality of MOS transistors (here, NMOS transistors).

The gate electrodes of these current control gates 38 and 39 are controlled by control signals 17 and 18 from the timing circuit, respectively, and the intermediate potential 3 is corrected by changing the amount of current flowing through each current control gate. Things. For example, if the control signal 17 becomes high level and the drain current of each transistor of the control gate 38 becomes large, the intermediate potential 3 rises, and conversely, the control signal 18 becomes high level and the control gate 39 becomes high. If the drain current of each transistor increases, the intermediate potential 3 drops. In particular, when stacking logic circuits using CM ため S, the internal power supply voltage of each layer, here the intermediate potential, fluctuates because the current such as the through current flowing through each layer is not constant. However, the above problem can be solved by using a means for comparing the values of the power supply voltages of the respective layers and compensating the intermediate potential based on the results as in this example. Further, in this example, by providing the current control gate, the intermediate potential can be stabilized by a relatively simple method such as controlling the amount of current flowing through each layer.

Here, the number N of the NM OS transistors constituting each control gate is represented by the capacity of the power supply dividing capacitors 15 and 16 shown in Fig. 2, the time t for turning on the NM OS transistor, and the unit time in the NM OS transistor. Equation (2) can be obtained from the current amount i flowing around and the potential width V corrected at one time.

N = (CV) / (i t) (Equation 2) In the power split unit 1 having the above configuration, if the intermediate potential 3 is lower than the specified value, the control gate 17 is controlled by the control signal 17. Drive 3 8 to add electric charge from power supply potential 2 to intermediate potential 3 to raise intermediate potential 3. Conversely, if the intermediate potential 3 is higher than the specified value, the control gate 39 is driven by the control signal 18, and charges are released from the intermediate potential 3 to the ground potential 5 to lower the intermediate potential 3.

Next, the level conversion circuit 9 shown in FIG. 1 will be described. Fig. 7 shows the low FIG. 3 shows a configuration of a level conversion circuit for converting a low-amplitude output signal from an amplitude logic circuit into a full-amplitude signal. This level conversion circuit is composed of two level shifter circuits 41 and 42. The level shifter circuit 41 receives the output signal 43 of the first low-amplitude logic circuit and is connected to the power supply potential 2 and the intermediate potential 3, and supplies the output signal 43 of the first-layer low-amplitude CMOS logic circuit 6 to the power supply. The signal is output to the full amplitude logic circuit 10 as the full amplitude signal 45 instead of the voltage signal amplitude. The level shifter circuit 42 receives the output signal 44 of the second low-amplitude logic circuit and is connected to the intermediate potential 3 and the ground potential. The level shifter circuit 42 outputs the output signal 44 of the second-layer low-amplitude CMOS logic circuit 7 to the signal of the power supply voltage. The signal is output to the full amplitude logic circuit 10 as the full amplitude signal 46 instead of the amplitude. In this example, by having such a level shifter circuit, an output signal having an amplitude corresponding to the internal power supply voltage can be made an output signal corresponding to the external power supply voltage, and the signal can be transmitted to another external semiconductor device or the like. The exchange can be done easily.

FIGS. 8 and 9 show a level shifter circuit that can be employed as the level conversion circuit of this example.

The circuit shown in FIG. 8 is a circuit that has already been made in Japanese Patent Application Laid-Open No. 4-97616, but can be used as the level shifter circuit of this example. The circuit in FIG. 8 converts a low-amplitude input signal 50 into an output signal 51 having a power supply level amplitude. More specifically, assuming that the input signal 50 is at a high level, a low-amplitude level 52 is applied to the NMOS transistor 56 and a low-amplitude Low level 53 is applied to the NMOS transistor 57. As a result, the ground potential 4 tends to be applied to both the PMOS transistors 54 and 55, but since the gate voltage of the NMOS transistor 56 is higher, the PM〇S transistor 55 is higher than the PMOS transistor 54. The transistor is turned on earlier, the voltage applied to the gate of the PMOS transistor 54 increases, the PMOS transistor 54 is not turned on, and the source potential of the PMOS transistor 54 becomes the ground potential 4 because the NMOS transistor 56 is on. In order to maintain this, the PMOS transistor 55 always keeps the ON state and fixes the output 51 to the power supply potential 2. Conversely, when the Low potential 53 is applied to the input 50, the PMOS transistor 54 is turned on first, and the output 5 1

-: It is made to be logic.

Next, FIG. 10 shows a specific example of the interlayer level conversion circuits 7 and 8 that can exchange signals between the respective layers shown in FIG. FIG. 10 shows a circuit that performs signal conversion from the upper layer (the first low-amplitude logic circuit) to the lower layer (the second low-amplitude logic circuit).

This level conversion circuit is composed of an inverter 69 which operates at the potential of the input signal 66 and is connected to the power supply potential 2 and the intermediate potential 3 and two inverters which operate at the potential of the output signal 67 or 68. It comprises a latch circuit 70 connected to the ground potential 4 and diode-connected NMOS transistor groups 71 and 72 which are level shift means for lowering the signal amplitude by a threshold voltage (hereinafter referred to as Vth). You.

The operation of this circuit will be described. When the power supply potential 2 in FIG. 10 is 3 V and the intermediate potential 3 is 1.5 V, the potential of the input signal 66 is 3 V which is the high level of the first layer (the first low-amplitude logic circuit 5). If there is, a potential is applied to the latch circuit 70 via the NMOS transistor group 72. At this time, if V th of one NMOS transistor is 0.75 V, the latch circuit 70 receives the high-level 1.5 V of the second layer and the output signal 67 is at the low level of the second layer. 0 V, and the output signal 68 becomes 1.5 V which is the level of the second layer. These output values are compensated by the latch circuit 70. If 68 of the output signals 67 and 68 are used, this interlayer level conversion circuit can be used also as a NOT circuit. If 68 is used, this interlayer level conversion circuit can be used as a simple interlayer level conversion circuit without a logical function. it can. Here, the number N of NMQS transistors used in the NMOS transistor groups 71 and 72 can be determined by Equation 3 based on Vth of the NMOS transistor and the voltage difference V between the layers for voltage conversion.

N = V / V th (Equation 3) In FIG. 11, contrary to the level conversion circuit shown in FIG. 10, the lower layer (low-amplitude logic circuit 6) and the upper layer (low-amplitude logic circuit 5) This is for level conversion, and receives the input signal 73, and shifts the level of the input and output values of the inverter circuit 76 connected to the intermediate potential 3 and the ground potential 4 and the inverter circuit 76. OS transistor groups 7 8 and 7 9, and a latch circuit 7 (configured by connecting two inverter circuits) 7 connected to the power supply potential 2 and the intermediate potential 3, and output from both ends of the latch circuit 7 7 It is configured to take 4, 75. This interlayer level conversion circuit performs the same circuit operation as the interlayer level conversion circuit shown in FIG. 10 to convert a signal having an amplitude based on a lower internal power supply voltage and a signal having an amplitude based on a higher internal power supply voltage. Is converted to The operation of this circuit is almost the same as that of the level conversion circuit shown in FIG. 10, so that the detailed description is omitted.

As described above, by using the circuit shown in FIG. 10 as the interlayer level conversion circuit 7 in FIG. 1 and using the circuit shown in FIG. 11 as the interlayer level conversion circuit 8 in FIG. Signals can be exchanged between the layers.

FIG. 12 shows an inter-layer level conversion circuit that performs bidirectional level conversion from the upper layer to the lower layer and from the lower layer to the upper layer. As shown in FIG. 12, as shown in FIG. 12, latch circuits 63, 6 composed of inverter circuits connected in series with input / output terminals 60, 61 and level shift means 6 for connecting the respective latch circuits. The latch circuit 63 is connected to the power supply potential 2 and the intermediate potential 3, the latch circuit 64 is connected to the intermediate potential 35 and the ground potential 4, and the level shift means 64, 65 are provided. It is composed of multiple NMOS transistors connected in diode. The operation of this circuit can be easily understood from the description of the operation of the interlayer level conversion circuit described above, and thus the description is omitted here. If this circuit is used, the interlayer level conversion circuits 7 and 8 shown in FIG. 1 can be shared by one circuit.

13 and 14 show other examples of the structure of the interlayer level conversion circuit. The description of the same parts as those of the level conversion circuits shown in FIGS. 10 and 11 will be omitted. The circuits shown in FIGS. 13 and 14 are similar to the circuits shown in FIGS. 10 and 11 except that the level shift means of the conversion circuits shown in FIGS. 9 is used.

FIG. 15 shows an embodiment in which the number of power supply divisions is three. In this embodiment, the input signal 11 is processed by the low-amplitude circuit 105 operating at the voltage of the first layer created by the power supply unit 101, and then the signal is changed by the signal level conversion circuit 108. The width is set to the potential of the second layer, and processed by the low-amplitude circuit 106 operating at the voltage of the second layer. Further, after the signal amplitude is set to the potential of the third layer in the interlayer level conversion circuit 109, the signal amplitude is processed in the low-amplitude logic circuit 107 operated by the voltage of the third layer, and further converted to the full amplitude signal by the level shifter circuit 110. The output signal 12 is processed by the full amplitude logic circuit 10.

FIG. 16 is a diagram showing a configuration of a power supply division unit # 01 for dividing the power supply into three parts in the logic circuit shown in FIG.

The power supply dividing unit 101 includes capacitors 117, 118, and 119 for dividing the power supply potential 2 and the Durand potential 4 into three, a dummy gate 114 for correcting fluctuations of the intermediate potentials 103 and 104, and an intermediate potential 103. , 104, and a control circuit 113 for causing the dummy gate to follow the fluctuation. The control circuit 113 observes the intermediate potentials 103 and 104, and outputs control signals 120, 121, 122 and 123 at the timing obtained from the clock signals 23 and 24 based on the observation results, and outputs the dummy gate 1 14 Operates the internal circuit based on the control signals 120, 121, 122, 123, and corrects the values of the intermediate potentials 103, 104 to normal values.

Here, the capacities of the capacitors 1 17, 1 18, 1 19 are almost equal, and the value C can be obtained by the above-mentioned formula 1 as in the configuration example in the case of dividing by 2.

FIG. 17 shows the configuration of the control circuit shown in FIG. This control circuit is composed of two voltage comparators 124, 125 and a timing circuit 126. The voltage comparator 124 observes the intermediate potential 103, compares whether the potential difference between the power supply potential 2 and the intermediate potential 103 is half of the potential difference between the intermediate potential 103 and the ground potential 4, and outputs the result as a signal. Output as 127 and 128. The voltage comparator 125 observes the intermediate potential 104, and compares whether the potential difference between the power supply potential 2 and the intermediate potential 104 is twice as large as the potential difference between the intermediate potential 104 and the ground potential 4. The result is output as signals 129 and 130. The timing circuit 126 uses the outputs 127, 128, 129, 130 of the two voltage comparators 124, 125 as control signals 120, 122, 122, 123 at a fixed timing determined by the clocks 23, 24. Output for a certain period of time. Observing the power supply voltage of each layer can also be realized by providing a voltage comparator that compares the voltage for each layer.However, as in this circuit, the potential difference of the lower layer is the difference between the potential difference of the upper layer and the middle layer. Observe whether it is half or not, By observing whether or not the potential difference of the upper layer is half of the potential difference of the middle layer and the lower layer, the voltage of each layer can be measured with a small number of voltage comparators.

FIG. 18 is a block diagram of the voltage comparators 124 and 125. This comparator is composed of switches 138, 1339, 143, 144, 145, 146, capacitors 140, 141, and 142 of the same capacity, a comparator 136, and a latch circuit 137. In this voltage comparator, first, switches 138 and 139 are closed, switch 145 is set to the input potential 147 side, and switches 143 and 144 are used so that the two capacitors 144 1 and 142 become parallel. The switch 146 is set to the input potential 148 side, the capacitor 140 stores the potential difference between the reference potential of the comparator 136 and the input potential 147, and the capacitors 141 and 142 store the reference potential and the input potential. Save the potential difference from 148. Next, the switches 1 3 8 and 1 3 9 are opened and the switch 1 45 is set to the input potential 148 side. The two capacitors 141 and 142 are connected in series by the switches 143 and 144, and the switch 146 is set to the input potential. 1 Set to the 49 side. As a result, the potential difference between the input potentials 147 and 148 and twice the potential difference between the input potentials 148 and 149 are input to the comparator 1336. At this time, if the potential difference between input potentials 147 and 148 is larger, output 150 will be high, and if twice the potential difference between input potentials 148 and 149 is greater, output 15 1 will be high. . The latch circuit 1337 sets the levels of the outputs 150 and 151 to the value of the power supply potential 2 and the level of Low to the value of the ground potential 4.

When this voltage comparator is used as the voltage comparator 124 in Fig. 15, the power supply potential 2 becomes the input potential 147, the intermediate potential 103 becomes the input potential 148, and the ground potential 4 becomes the input potential 1 4 It becomes 9. The output 150 is used as the output 127 in FIG. 17, and the output 151 is used as the output 128. When used as the voltage comparator 125, the power supply potential 2 becomes the input potential 149, the intermediate potential 104 becomes the input potential 148, and the ground potential 4 becomes the input potential 147. The output 150 is used as the output 130 in FIG. 17, and the output 151 is used as the output 129.

FIG. 19 shows the configuration of the timing circuit 126 shown in FIG. This timing circuit is a counter that determines the timing of the correction process performed at regular intervals. 52, an AND circuit 153 for determining the output timing and its time, and AND circuits 154, 155, 156, 157 for outputting the control signals 120, 121, 122, 123. First, the counter 152 operates similarly to the counter 33 shown in FIG. 5, and the AND circuit 153 operates similarly to the counter 33 shown in FIG. 5 to generate the timing signal 158. The AND circuits 154, 155, 156 and 157 synchronize the voltage comparator outputs 127, 128, 129 and 130 with the timing signal 158 in the same manner as the AND circuits 35 and 36 in FIG. Are output as control signals 120, 121, 122, and 123.

FIG. 20 shows the configuration of a dummy gate. This dummy gate is composed of current control gates 161, 162, 163, 164, 165, 166 composed of a plurality of NMOS transistors. The control gate 161 of this dummy gate raises the potential of the intermediate potential 103 by the control signal 120, and the control gates 162, 164 raise the intermediate potential 104 in conjunction with the control signal 122. The control gates 163 and 165 lower the intermediate potential 103 in conjunction with the control signal 121, and the control gate 166 lowers the intermediate potential 104 according to the control signal 123. Here, the number N of the NMOS transistors constituting each control gate can be obtained from the equation 2 as in the case of the dummy gates 38 and 39 in FIG.

In the power supply division unit 101 having the above configuration, if the intermediate potential 103 is lower than the specified value, the control gate 161 is driven by the control signal 120 and the electric charge is added to the intermediate potential 103 from the power supply potential 2 to apply the intermediate potential. Raise 103. Conversely, if the intermediate potential 103 is higher than the specified value, the control signal 121 drives the control gate 162 and the control gate 164, and the intermediate potential 103 releases the electric charge to the ground potential 4 to generate the intermediate potential 103. Lower it. If the intermediate potential 104 is lower than the specified value, the control signal 122 drives the control gate 163 and the control gate 166, and applies a charge to the intermediate potential 104 from the power supply potential 2 to generate the intermediate potential 104. To raise. On the other hand, if the intermediate potential 104 is higher than the specified value, the control gate 166 is driven by the control signal 123 to discharge the electric charge from the intermediate potential 104 to the ground potential 4 to lower the intermediate potential 104.

FIG. 21 shows another configuration example of the power supply unit. In the figure, the power supply is divided into three Although the example of dividing is shown, the same applies to the case where the number of divisions is different. This power dividing unit comprises capacitors 1 1, 1 1 8, 1 19, a control circuit 170, and dummy gates 171, 172, 173 for dividing the power into three. In this power supply division unit, the intermediate potentials 103 and 104, which are divided into three by the capacitors 1 17 and 1 18 and 1 19, are converted into control signals 174 and 175 output from the control circuit 170. , 176 operate the dummy gates 171, 172, 173 to stabilize.

FIG. 22 shows the configuration of the control circuit 170 of FIG. This control circuit comprises a frequency divider 181, a loop counter 182, an AND circuit 183, a ROM 180, and a timing gate 184. First, the clock signal 23 is frequency-divided by the frequency divider 18 1 by a certain number. As a result, the loop counter 18 2 is counted up by 18 5 and the value of this counter is stored in the address 1 of the ROM 180. Used as 86, the value of ROM 180 is divided into three, and output as control signals 174, 175, 176 by timing gate 184. The timing gate 184 outputs the output timing by the timing signal 187 obtained by ANDing the value 185 obtained by dividing the clock 23 with the frequency divider 18 1 by 1Z4 cycle from the clock 23 with the clock 24 by the AND circuit 183. Is determined. In this example, the amount of current flowing through the logic circuits arranged in each layer is grasped in advance by a method such as simulation, instead of compensating for each intermediate potential by comparing the voltage of each layer with a voltage comparator. This is effective in such a case, and controls to equalize the current amount of each layer at each timing according to the data stored in the memory (ROM) in advance.

FIG. 23 shows the configuration of the dummy gates 171, 172, 173. The dummy gates 171, 172 and 173 are composed of N NMOS transistors and are operated by control signals 174, 175 and 176 respectively. The control signals 174, 175, and 176 are N-bit signals. Each bit corresponds to the NOMS transistor in the dummy gate, and the number of NOMS transistors depends on the "1" and "2" of each bit. Can be specified.

FIG. 24 shows a configuration in which the logic circuit according to the present invention is applied to a DSP (Digital Signal Processor) as a signal processing circuit or a microphone computer. Show. When a signal processing circuit is configured using multilayer logic circuits as shown in FIGS. 1 and 15, it is important to assign each circuit block to which power supply layer. FIG. 24 illustrates an example in which a logic circuit in which an external power supply voltage is divided into three internal power supply voltages is used. Although not particularly limited, the signal processing circuit of this example is a semiconductor integrated circuit (LSI) formed on a single semiconductor substrate, and constitutes a system such as a computer system with other semiconductor devices. is there. The DSP consists of a RAM matrix (memory cell array) 201 in which predetermined data required for signal processing is stored and a ROM matrix (memory cell array) 202 in which instructions are stored. The arithmetic unit (EX) 203, the address arithmetic unit (AU) 204, and the I / unit 205, which serves as an interface with the outside, and the ROM matrix that perform predetermined arithmetic operations in accordance with the It consists of an instruction decoder 206 that decodes the executed instructions, a program control unit (PCU) 207 that controls the execution of the program, a RAM sense amplifier 208, and an address decoder 209. .

Of these circuit blocks, the I / O unit 205 operates at a so-called full amplitude (amplitude corresponding to the external power supply voltage) to maintain an interface with external circuits such as other semiconductor devices. Is desirably configured to be output. In addition, both the RAM matrix 201 and the ROM matrix 202 operate at full amplitude in the same manner as the I / O unit 205 in consideration of the accuracy and access speed of the stored information. It is desirable to have such a configuration.

Also, the bus 220 for transmitting information such as data is connected to a plurality of circuit blocks and needs to transmit data of each circuit block. By maintaining the amplitude of the second layer when divided, the level conversion from each circuit block can be reduced (when divided into three layers, the level conversion is performed at most once). is there.

Since the arithmetic unit 203 performs a predetermined arithmetic operation, the number of accesses to the bus 220 is the largest. Therefore, it is necessary to have the same amplitude as the bus. In this case, since the amplitude of the bus 220 is regarded as the amplitude of the second layer for the reason described above, the arithmetic unit 203 is also formed in the second layer, and the amplitude according to the power supply voltage of the second layer is obtained. Input and output signals To be.

Since the sense amplifier 208 that amplifies the output of the RAM matrix that stores data necessary for the operation accesses only the bus 220, it is preferable that the sense amplifier 208 be configured with the same amplitude as the bus 220, that is, the second layer in the middle.

Next, the addressing unit 204 and the instruction decoder 206 remain. However, if these are arranged on the same layer, the circuit scales of both are too large, so it is desirable to use separate layers. Here, they are assigned to the first and third layers, respectively.

Further, since the addressing unit 204 has a smaller circuit scale than the instruction decoder 206, another PCU is also used as the first layer.

Next, since the RAM address decoder 209 is accessed only from the AU 204, it is the first layer, and sends an address to the RAM matrix 201 via the level conversion circuit 212.

Since the ROM matrix address decoder 210 is also accessed only from the PCU 207, the ROM decoder sends the address to the ROIV [Matritas] through the level conversion circuit 213 as the first layer.

Further, since the ROM matrix sense amplifier 214 accesses only the instruction decoder 206, it is a third layer.

The bus drive circuit 219 for outputting the value of the external I〇 to the bus 220 has the same second layer as the bus 220, and does not require an interlayer level conversion circuit.

Finally, when data is output from the instruction decoder to the bus 220, and when values are fetched from the bus 220 to the AU 204 and the PCU 218, they are performed via the interlayer level conversion circuits 211, 217 and 218, respectively. When sending data from the bus to the RAM matrix 201 and the IO 205, use the level shifters 211 and 215, respectively.On the contrary, when sending data from the RAM matrix 201 to the RAM sense amplifier 208 and from the ROM 202 to the ROM When sending data to the sense amplifier 214 and when sending data from I 0205 to the bus driver 219, a full-amplitude signal is sent directly. This is because operation is possible even when the input signal of the MOS circuit exceeds the power supply amplitude.

By configuring the signal processing circuit with a multi-layer power supply logic circuit as described above, It is possible to efficiently form a low-power signal processing circuit.

FIG. 25 is a diagram schematically showing the system of the mobile radio telephone as described above. The speech encoding / decoding circuit 2 3 4 and the like are configured using the logic circuit of the multi-layer power supply according to the present invention. Therefore, a modem circuit 235 that requires a relatively high external power supply voltage and a logic circuit that can operate with a relatively low power supply voltage can coexist, and from the viewpoint of the scale and power consumption of the system, It is also possible to configure a suitable signal processing system such as a mobile radio telephone.

As described above, according to the present invention, in a system including a circuit in which low-voltage operation is difficult, it is possible to reduce the power consumption of the system using a low-voltage CMOS logic circuit without increasing the circuit scale. Become. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be applied to a logic circuit using CMOS, particularly to a CMOS logic circuit operating at low voltage. Further, when the external power supply voltage of the semiconductor integrated circuit constituting the logic circuit is high, a CMOS logic circuit operating at a low voltage can be efficiently configured. Furthermore, by using the present invention, a simple signal processing circuit with low power consumption and a simple system configuration can be configured.

Claims

Claims 1. A power splitter that is supplied with a first operating potential and a second operating potential, and outputs a third operating potential different from both the first operating potential and the second operating potential. A first logic circuit that operates between the first operating potential and the third operating potential and is configured by a complementary field-effect transistor; And a second logic circuit composed of complementary field-effect transistors, and converts the amplitude of the output signal of the first logic circuit and inputs the converted signal to the second logic circuit. And a level conversion circuit. The third operating potential point is connected to the first operating potential point and the second operating potential point. A power supply unit supplied from the first operating potential point, a first logic circuit connected to the first operating potential point and the third operating potential point, a third operating potential point and the second A second logic circuit connected to the operating potential point of the first logic circuit and a level conversion circuit receiving a signal output from the first logic circuit and a signal output from the second logic circuit; Is configured to convert the signals input from the first and second logic circuits from the potential at the first operating potential point to a signal having an amplitude corresponding to the potential at the second operating potential point. A semiconductor integrated circuit device characterized by the above-mentioned. The semiconductor integrated circuit device further comprises a level conversion circuit for converting the amplitude of the output signal of the second logic circuit and inputting the converted signal to the first logic circuit. 3. The semiconductor integrated circuit device according to claim 2. 4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device further includes a third logic circuit connected to the first operating potential and the second operating potential. 2. The power supply dividing unit according to claim 1, wherein the power dividing unit includes means for detecting the third operating potential, and means for correcting the third operating potential based on the detecting means. Semiconductor integrated circuit device. The means for detecting the third operating potential compares the potential difference between the first operating potential and the third operating potential with the potential difference between the third operating potential and the second operating potential. 6. The circuit according to claim 5, wherein the means for correcting the third operating potential is constituted by a current control circuit that controls an amount of a current flowing based on the comparison result. Semiconductor integrated circuit device. The level conversion circuit has level shift means for shifting a level of an output signal of the first logic circuit, and a latch circuit receiving the output signal via the level shift means. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured to operate between a third operating potential and the second operating potential. The level conversion circuit converts the output signal of the second logic circuit and supplies the output signal to the first logic circuit, wherein the level shift circuit shifts the level of the output signal of the second logic circuit; A latch circuit for receiving the output signal via level shift means, wherein the latch circuit is configured to operate between the first operating potential and the third operating potential. 4. The semiconductor integrated circuit device according to item 3. A power supply connected to the first operating potential point and the second operating potential point and having a third operating potential point and a fourth operating potential point for supplying a potential different from the potentials of the two potential points A split unit, a first logic circuit connected to the first operating potential point and the third operating potential point, and a first logic circuit connected to the third operating potential point and the fourth operating potential point A second logic circuit, a third logic circuit connected to the fourth operating potential point and the second operating potential point, and a connection between the first logic circuit and the second logic circuit. A first level conversion circuit connected to the second logic circuit and a second level conversion circuit connected between the second logic circuit and the third logic circuit; and the first level conversion circuit Converts the output signal of the first logic circuit into an amplitude corresponding to the third operating potential point and the fourth operating potential point, A semiconductor integrated circuit device configured to convert an output signal of the second logic circuit into an amplitude corresponding to the fourth operating potential point and the second operating potential point. . 0 · The power supply unit detects the potential of the third operating potential point and the potential of the fourth operating potential point, and based on the detection results, determines the third operating potential point and the third operating potential point. 10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device is configured to correct the potential of the semiconductor integrated circuit.

1. The power supply unit is

A first potential difference that is a potential difference between the first operating potential point and the fourth operating potential point, and a second potential difference that is a potential difference between the first operating potential point and the third operating potential point And a first comparison circuit for comparing a value of half of the first potential difference with the second potential difference,

A third potential difference, which is a potential difference between the third operating potential point and the second operating potential point, and a fourth potential difference, which is a potential difference between the third operating potential point and the second operating potential point A second comparison circuit that detects half of the third potential difference and the fourth potential difference,

10. The semiconductor integrated circuit device according to claim 9, wherein the potentials of the third and fourth operating potential points are corrected based on a comparison result of the first and second comparison circuits.

2. The power supply unit is

A control circuit that outputs a control signal stored in advance at a predetermined timing; A transistor connected to the gate electrode thereof while receiving a control signal of the control circuit, and configured to control an amount of current flowing through the transistor by the control signal. 10. The semiconductor integrated circuit device according to claim 1, wherein:

3. a first group of circuits operating at a first amplitude corresponding to the external power supply voltage;

A circuit that divides the external power supply voltage to generate at least three internal power supply voltages; and a second and a third operating at a second amplitude, a third amplitude, and a fourth amplitude corresponding to the three internal power supply voltages. , A fourth circuit group,

A bus involved in signal transmission between the respective circuit groups,

The first circuit group includes an interface circuit that receives a signal from outside and supplies the signal to the bus.

A semiconductor integrated circuit device, wherein the third circuit group is configured to include an operation unit connected to the bus and performing a predetermined operation on data received via the bus.

4. The first circuit group further includes

A memory cell array constituting a memory for temporarily storing data supplied from the outside;

14. The semiconductor integrated circuit device according to claim 13, further comprising: a memory cell array forming a memory in which a program is stored.

5. The third circuit group includes a sense amplifier circuit for amplifying an output of a memory cell array constituting a memory for storing data supplied from the outside and supplying the amplified signal to the bus. 15. The semiconductor integrated circuit device according to claim 14, wherein

6. The fourth circuit group has an instruction decoder that decodes a program stored in the memory, and an output of the instruction decoder is output to the bus via a level conversion circuit that converts the amplitude of the instruction decoder. 16. The semiconductor integrated circuit device according to claim 15, wherein:

7. The second group of circuits is configured to specify an address of the memory based on a signal transmitted through the bus, and an addressing unit receiving an output of the addressing unit. Claims characterized by having a decoder 17. The semiconductor integrated circuit device according to item 16.

8. A signal processing device including at least the first and second semiconductor integrated circuit devices,

First and second operating potential generating means for supplying an operating potential commonly to the first and second semiconductor integrated circuit devices,

The first semiconductor integrated circuit device includes an external circuit that operates at the first and second operating potentials,

The signal processing device, wherein the second semiconductor integrated circuit device is configured to have an internal circuit that operates with an operating potential having a potential difference smaller than the potential difference between the first and second operating potentials.

9. The signal processing device further includes:

An antenna connected to the first semiconductor integrated circuit for receiving a radio signal, wherein the first semiconductor integrated circuit device is a modulation circuit for modulating a signal received by the antenna;

19. The signal processing device according to claim 18, wherein the second semiconductor integrated circuit device is a decoding circuit that processes an output signal of the modulation circuit. 0. The signal processing device further comprises:

A digital-to-analog converter and a speaker,

10. The signal processing device according to claim 19, wherein the output of the decoding circuit is converted by the digital-analog converter, and the speaker is operated based on the conversion result. apparatus.