WO1996037994A1

WO1996037994A1 - Pulse width modulation (pwm) circuit

Info

Publication number: WO1996037994A1
Application number: PCT/EP1996/002253
Authority: WO
Inventors: Michael JÄTH
Original assignee: Jaeth Michael
Priority date: 1995-05-26
Filing date: 1996-05-24
Publication date: 1996-11-28
Also published as: DE19519451A1

Abstract

The invention concerns a pulse width modulation (PWM) circuit for controlling a laser in a laser printer, with the following elements: an interface (1) capable of connection to an external data source; a buffer memory (3a, 3b) with an input connection for receiving data via the interface (1) and an output connection which is independent of the input connection and forwards previously received data values onto an internal channel (4) at intervals of period (τ) determined by the timing pulse generator (11); a first digital-analogue converter (7) whose output signal level is updated at intervals of period (τ) on the basis of the forwarded data values; a modulator (8) which includes a ramp generator (81) and on the basis of the output signal level from the first digital-analogue converter (7) generates a pulse-width modulated laser control signal with a modulation period. The circuit is characterised in that the modulation period of the laser control signal is equal to the period (τ) and the ramp generator (81) generates a ramp signal in the form of a symmetrical saw-tooth voltage with period (τ).

Description

PWM CIRCUIT

The invention relates to PWM circuits with high temporal resolution and methods for pulse-width modulation of an output signal.

Such circuits and methods are used to build up a print image in a laser printer.

In addition to a laser, a laser printer comprises, inter alia, a rotatable facet mirror and a drum which is coated with a light-sensitive material and is electrostatically chargeable in order to attract toner particles in accordance with the charge distribution and later on a recording medium, usually guided over the surface of the drum a sheet of paper to transfer. The facet mirror has the shape of a regular polygon in cross section. The laser beam hits one side of the polygon and is from reflected on the drum there. The uniform rotation of the facet mirror guides the beam in the longitudinal direction of the drum over its surface. The intensity of the beam is modulated so that an electrostatic charge distribution corresponding to the beam intensity is created along the path of the beam on the drum, which represents a line of the printed image.

The laser and the facet mirror are arranged with respect to one another such that when the reflected beam has reached one end of the drum, another mirror facet immediately enters the beam path, which first reflects the beam onto the other end of the drum. Due to the further rotation of the mirror, the reflected beam is guided along the drum in a second pass.

At the same time, the drum rotates about its longitudinal axis, so that in the second pass the beam strikes a different area of the drum surface than in the first. In this way, the print image is built up line by line.

The rows themselves consist of a large number of unit cells or pixels. In early laser printers, the pixels could only assume the states on / off or exposed / unexposed and defined the resolution of the printer, as is still the case with screen displays and matrix printers.

In order to be able to display gray levels in the printed image and to avoid undesired levels in the printed image caused by the pixel structure, for example when displaying oblique lines or text, methods and devices have been developed with which pixels with an internal structure can be displayed. Such devices and methods according to the preambles of the independent claims are, for example, from US-A-5 122 883 known. The raster imaging device driver described in this patent receives two data values for each pixel to be printed, which each define positions within the pixel at which the laser is switched on or off. The degree of blackening of the pixel results from the difference between the two values. With this driver, oblique edges can be effectively smoothed, especially in the case of lines which run steeply to the line direction, since the switchover positions can be anywhere in a pixel. For this purpose, however, it is necessary to calculate these positions individually depending on the states of neighboring pixels. When it comes to displaying text, these calculations can be carried out once for all characters in a character set and then tabulated, so that they only have to be called up when text is printed. In the case of graphics in which any shapes and contours can occur, this tabulation is not possible, so that the driver requires a considerable amount of computation to generate the data, which usually has to be done by the computer to which the Printer is connected. This leads to annoying waiting times for the user between the input of a print command and the transfer of "print-ready" data to the driver, in which the computer is not available for other activities.

Another problem arises from the way the laser printer works. The rotational speeds of the facet mirror and the drum must be precisely adjusted to one another and are therefore predefined depending on the design. The time available for exposing the drum for a page to be printed is therefore very narrow. Since the data output speed of the computer is limited, only a limited amount of data can be transmitted during this time. If more data is required to build the page If this is the case, these must be loaded into the laser printer and buffered there before the exposure process begins, which increases the printing times and, due to the required buffer memory, the costs for the printer.

Another problem that can arise with the output of images or graphics stored in a computer is that of the aspect ratio. The ratios of pixel height to width often differ in the screen display and printer. In such a case, if a pixel pattern is transferred identically from the screen to the printer, the proportions appear distorted. In order to avoid this, the image and printed image displayed on the screen have to be converted into one another or both have to be calculated from a common data record describing the image, which in any case takes time.

The object of the invention is to provide PWM circuits and methods for pulse width modulation, with which a high resolution can be achieved with little control effort.

The object is achieved on the one hand by a digitally controlled PWM circuit according to claim 1. According to the invention, the period of the ramp generator is equal to the time interval with which the buffer memory from a data source, for example the bus of a laser printer, is controlled by means of the circuit Computers, receives received data and the first D / A converter forwards updated output signal levels to the modulator. In contrast to US Pat. No. 5,122,883, where the period of the two ramp generators is twice the PWM modulation period, the circuit according to the invention only requires one ramp generator. A complete cycle of the circuit takes place in each period of the clock generator, in which the modulator uses a output memory value generated exactly one voltage pulse of suitable width. With the same output capacity of the data source, twice as many pixels can therefore be defined in a predetermined time with the aid of the circuit according to the invention as with the circuit known from US Pat. No. 5,122,883. In other words, in the time it takes for the laser to expose a line on the drum, it can drive it with twice as many width-modulated pulses, each corresponding to one pixel. Since this halves the width of the pixels, ie doubles the horizontal resolution, the circuit according to the invention makes it possible to dispense with the time-consuming calculation of the transition positions within the pixels.

This is particularly noticeable when printing images in which there are quasi-continuous transitions between different color or gray gradations. With these transitions, the information content for the viewer is not in the exact position of the color dots in the printed image, but merely in the ratio of their size to the total area of the pixel. The smaller the pixels can be made, the more continuously the color gradations appear.

The object is further achieved by a circuit according to claim 12. This circuit makes it possible to change the lengths of the pixels by tuning the clock generator and thereby to adapt the aspect ratio in such a way that any distortions in the printout are avoided without the content of the printing pixels must be calculated individually. The clock frequency can be set under software control, the control data preferably being transmitted from the same data source as the data to be printed. Further features and advantages of the invention result from the following description of exemplary embodiments with reference to the attached figures. Show it:

1 shows a block diagram of a first PWM circuit according to the invention;

FIG. 2 forms of the voltage ramp used in the circuit from FIG. 1;

3 shows a block diagram of a second PWM circuit according to the invention;

4 shows the course of a function stored in a memory element of the circuit from FIG. 3;

5 shows a first embodiment of a tunable clock generator;

6, 7 show two variants of the clock generator from FIG. 5;

8 shows a second embodiment of a tunable clock generator;

FIG. 9 shows a detail of the clock generator from FIG. 8;

10 shows a computer / printer system with a PWM circuit according to the invention.

11 shows a further development of the circuit from FIG. 3.

1 shows a first embodiment of the PWM control circuit according to the invention for a laser printer. The control circuit is connected via a bidirectional interface 1 for the transmission of control information and data with a data tenquelle, here the bus 10 of a computer, connected. Depending on whether the circuit is built into the computer or the printer and depending on the distance to be bridged, this interface can be, for example, a connector, an optical fiber cable with optocouplers, a SCSI interface or the like. It forwards data received from bus 10 to an internal bus 2 on the card. The internal bus 2 has 16 data lines, to which a buffer memory made up of two memory banks 3a, 3b is connected, in which data lying on the internal bus 2 can be temporarily stored. The memory banks 3a, 3b are addressed by address generators 12a and 12b, respectively. The memory banks are each connected to sequencer circuits 5a, 5b, which break down a 16-bit wide data value output from the memory bank into two successive 8-bit values and transfer them successively to a first D / via an internal channel 4 with 8-bit width. Pass on A converter 7. These 8-bit values indicate the desired blackening of a pixel. The output terminal of the first D / A converter 7 is connected to the duty cycle control terminal of a modulator 8.

The modulator 8 essentially comprises a ramp generator 81 and a comparator 82. The ramp generator 81 generates a sawtooth voltage with a period τ, which is predetermined by a tunable clock generator 11, the structure and mode of operation of which will be discussed later. The sawtooth voltage is symmetrical in time, ie the slopes of its rising and falling edges are essentially the same in opposite directions. The harmonic component in the spectral composition of such a signal is lower than in asymmetrical sawtooth signals, so that the symmetrical signal can be generated more simply and precisely in terms of circuitry and the interference radiation emanating from such a circuit is reduced. A filter 83 can be provided between the ramp generator 81 and the ramp input of the comparator 82, which distorts the sawtooth signal. In most laser printers, the relationship between the pulse duty cycle and degree of blackening is not linear. This non-linearity results between the data converted by the D / A converter 7 and the degree of blackening when a linear sawtooth signal is present at the comparator 82. In order to improve the grayscale reproduction, the filter 83 can be used to set a distortion which compensates for this non-linearity.

The filter 83 can be connected to the interface 1 via a control input and the internal bus 2, so that the filter characteristics can be adapted to the respectively connected printer via the computer. In particular if the PWM circuit is intended for installation in a specific printer, it may be sufficient if the filter characteristic e.g. is adjustable on the circuit using trimmers.

The comparator 82 compares the possibly distorted sawtooth voltage with the voltage level present at the duty cycle control connection and outputs a high output signal to switch on the laser exactly when the sawtooth voltage is less than the voltage at the duty cycle control ¬ connection is.

There is also a second D / A converter 9 on the internal bus 2, which controls the slope of the ramp generated by the ramp generator 82 by determining the charging current for a capacitor of the ramp generator 82.

The operation of the circuit will now be described. In an initialization phase, a control step is carried out in a first step via interface 1 and internal bus 2. Data value loaded into the clock generator 11 in order to determine its frequency.

In a second step, a control data value is transmitted to the second D / A converter 9, which then outputs an analog voltage corresponding to the data value, which generates the charge current for the capacitors of the sawtooth generator 81 and thus the slope or the amplitude of the sawtooth signal certainly. In this way, a temperature drift of the modulator can be counteracted or the contrast of the printed image can be regulated, as will be described in more detail below.

After the initialization steps have been carried out in any order, the circuit is ready to receive print data. These are transferred from the computer to the internal bus 2 via interface 1. Controlled by a clock signal from the computer, the address generator 12a generates, for example using the Gray code, a sequence of addresses at which the data are temporarily stored in the first memory bank 3a. As soon as the amount of data required to build up a print line is stored in the first memory bank, the memory bank 3a is decoupled from the internal bus 2, whereupon the data subsequently supplied by the computer are temporarily stored in the second memory bank 3b with the aid of the second address generator 12b become. While the memory bank 3b is being filled up, the address generator 12a generates the address sequence used for storing the print data in the first memory bank again, the sequence of the addresses being determined this time by the clock generator 11. In each clock cycle of the clock generator 11, an 8-bit data value is output on the data channel 4 and converted by the first D / A converter 7 into an analog output signal. As part of a functional check of the circuit, for example when the system is started, the data stored in the memory banks 3a, 3b can be read out by the computer via the internal bus 2 before or instead of being output on the data channel 4.

At the same time, the clock generator 11 controls the ramp generator 81 so that its output signal is in a fixed phase relationship with the change in the output signal level of the first D / A converter 7. The comparator 82 compares the output signal levels of the first D / A converter 7 and the ram generator 81, and outputs a positive output voltage which corresponds to the switch-on state of the laser when the ramp voltage is lower than the output signal level of the first D / A converter 7. If it is larger, the output signal is set to zero, which corresponds to the switched-off state of the laser. The phase relationship is selected so that, taking into account possible phase shifts by the filter 83 or signal delay differences, the ramp signal present at the input of the comparator at the time when the output signal level of the D / A converter 7 changes is at most or at least greater than is the maximum possible output signal from the converter. Controlled in this way, the laser generates one pixel per pixel on the light-sensitive roller per clock period in which the output signal level of the D / A converter 7 is not zero. Since only one data value is required to define the image point, the clock frequency can be chosen twice as high as before and the number of points per line can thus be doubled.

When printing, the problem may arise that if the print data is small, ie the output signal level of the converter 7 is close to zero, the laser will only work for one short subperiod of the period is switched on. If the length of this partial period falls short of a counter value tg, the charge distribution generated by the laser pulse on the photosensitive roller may be too little to absorb toner, for example because it is too small or its potential is not strong enough from that of the Environment deviates so that the desired point is not printed. Likewise, if the pressure data value is large and the output signal level of the converter 7 is high, the length of the interruption of the laser may fall below a limit value t _] _, so that the gap in the charge distribution generated by the interruption becomes so small that it is covered by neighboring exposed areas and thus a solid black pixel is printed. The limit values D _Q , D ^ of the print data value, beyond which this is the case, depend on environmental parameters of the photosensitive drum, such as temperature and humidity, on the degree of wear of its photosensitive layer or on the material to be printed. This effect must be taken into account in order to achieve optimum accuracy in the reproduction of gray levels.

This is done with the aid of the second D / A converter 9 in the manner illustrated in FIG. 2. Fig. 2a shows as Funk¬ tion time t a period of length τ a Rampen¬ from the generator 81 generated sawtooth voltage V (t) whose Ampli¬ tude (V _max - V _m i _n) on the boundary data values Dg and The corresponding voltage values VQ, V ^* J_ go beyond. An output signal from the first D / A converter 7 with a voltage level corresponding to the value Dg corresponding to the dash-dot line in FIG. 2a provides a pulse of length tQ that is just too short to be printed as a dot. The pixel is so white, just like all other Spannungs¬ levels in the voltage range between V I and V _Q _m i _n. Similarly, it can be seen that all voltage levels in the range II between V- * _| _ and V _max must lead to complete blackening of the pixel in question. Only levels in the intermediate range between V _Q and V _] _ are printed as gray levels. The contrast of the image is therefore too high.

The slope of the sawtooth signal is therefore increased with the aid of the second D / A converter 9, as shown in FIG. 2b. Now, the minimum necessary pulse duration is sufficient tg already in the print data value 0 corresponding voltage V _m i _n er¬ so that all pressure data values can be printed in stages as Grau¬ in the region I. The same applies correspondingly to area II.

It is irrelevant for the function of the circuit whether the sawtooth voltage V (t) actually reaches the intersection points Xg, Xi of the sawtooth flanks or whether, for example due to the supply voltages of the ramp generator, the extreme values of the voltage V (t) in Ranges between V _max and Xi or V _m j_ _n and X _Q lie.

The contrast can of course also be increased by reducing the slope of the sawtooth signal.

3 shows a second embodiment of the PWM circuit according to the invention. It differs from that shown in FIG. 1 by a memory element 6, which is inserted between the channel 4 and the first D / A converter 7. The address inputs of the memory element 6 are on the channel 4, its data inputs / outputs with a width of 10 bits used can be connected to the internal bus 2 and, bypassing this bus, to the first D / A converter 7.

In the initialization phase of this embodiment, the bidirectional interface is used in a third step 1 and the internal bus 2, implementation data D 'are entered into the storage element 6, which characterize the desired duty cycle for each possible print data value D. In this way, the pulse duty factor of the modulator is individually determined for each print data value to be subsequently transmitted to the circuit. This enables a practically arbitrary accuracy in the reproduction of different gray levels. Component tolerances and drifts of the circuit according to the invention or of the printer can be compensated for in a simple manner by adapting the implementation data. The storage element 6 can be provided instead of the filter 83 described above, but it can also serve to supplement and fine-tune its effect.

After the implementation data values have been loaded into the memory element 6, they can be queried via the interface 1 and the internal bus 2 from the control computer in order to check the correct functioning of the circuit.

FIG. 4 shows an example of a possible relationship between printing data D and conversion data D ', as can be stored in the memory element 6.

As one can easily see, it does not make sense to use more than one conversion data value, which is converted in the output voltage level of the D / A converter 7 below VQ or above V _] _. The extreme values ^D 'min ⁼ ° ^unc ^ D'max ^{= 2l0} are ^preferably used. In the area between the conversion data values D _Q 'or Di ¹ corresponding to these voltage limit values, however, the function D' (D) should be able to be represented with the greatest possible accuracy. For this purpose, the number of implementation data values that can be represented by circuitry must be in the interval from DQ 'to Di 'must be significantly larger than that of the possible print data values, ie their presentation must be more precise. Therefore, the width of the conversion data values D 'is two bits larger than that of the print data values D.

FIG. 4 shows a monotonically increasing function D ¹ (D). A monotonically falling function can be used just as well, in which case the comparator must then output a voltage corresponding to the switch-on state of the laser if the ramp voltage from generator 81 is greater than the voltage level from D / A converter 7 .

The configurations described with reference to FIGS. 1 and 3 have sequencers 5a, 5b at the output of the memory banks 3a, 3b, which adapt the data output by the memory banks to the width of the channel 4. If the widths of the memory banks and channel 4 are the same, the sequencers can be omitted.

According to a further development of the first and second embodiment, the sequencers can be switched over the bus 2 between the above-described and a second operating mode, in which they output a 16-bit value instead of two 8-bit values, for example four Convert 4-bit values and output them on the higher-order lines of channel 4. This means that each 8-bit value is interpreted as coding the gray levels of two pixels. With constant data throughput through the interface 1, twice as many pulses per unit of time can be generated as in the first operating mode, so that the spatial resolution of the print can be doubled, although instead of 2 = 256 gray levels only 2 = 16 are reproduced can. If such sequencers are used in the second embodiment of the PWM circuit according to FIG. 3, the conversion data values stored therein for the first operating mode can also be used to convert the 4-bit values, since they relate to the higher-order lines of channel 4 be issued.

However, since the ratio of the degree of blackening of the printer to the duty cycle of the control pulses can depend on their frequency, it is more advantageous to use a special implementation table which can be stored in a special area of the memory element 6.

An alternative further development of the second embodiment is shown in FIG. 11. A further sequencer 5c, which is arranged between the output of the memory element 6 and the input of the D / A converter 7, can be activated or deactivated in a controlled manner via the bus 2. In the switched-off state, the data are switched through from the memory element to the D / A converter 7 in unchanged width. In the activated state, the 4 higher and 4 lower bits of the data value present are output to the D / A converter in each half of the clock period τ via the 4 higher output lines.

The memory element 6 contains two sets of conversion data which are output depending on the operating state of the sequencer. The conversion values of the second data set each consist of two sections of 4-bit width, which each encode the conversion data value for the first and second 4 bits of a data value output by one of the sequencers 5a, 5b. This further development has the advantage over the previously described one that a lower access speed of the memory element 6 is required.

According to a third embodiment, a data decompression circuit can be integrated in the memory element 6. Such a circuit enables e.g. to transmit the data of extended printing areas with a constant degree of blackening, in particular the beginning and end of printing lines, in compressed form from the computer, whereby the bus 10 can be relieved or the printing speed can be further increased. ^

The structure and function of the tunable clock generator 11 are described below.

A first exemplary embodiment of the clock generator in the form of a PLL circuit is shown in FIG. 5. The clock generator comprises a D / A converter 27 which receives a data value from the computer via the internal bus 2 and converts it into an analog voltage level. This is applied to the control input of a voltage-controlled oscillator 23 via a superimposition circuit 26. Frequency dividers 21, 24 generate a comparison signal REF from the output signal of the oscillator 23 with a frequency that largely corresponds to the frequency of an external phase control signal BD. This phase control signal BD is derived, for example, from the position of the rotating mirror, for example by registering the point in time at which the laser beam reflected by the mirror sweeps over a detector 28 installed in the printer. A phase comparator 25 compares the phase of the control signal BD with that of the comparison signal REF and generates a DC voltage output signal which is superimposed on the output signal of the D / A converter 27 in the circuit 26. If the phase comparator 25 determines that the shift same signal REF leads the phase control signal BD, it reduces its output voltage in order to reduce the frequency of the oscillator 21. If the comparison signal REF lags, the output voltage of the phase comparator 25 is increased. The superimposition circuit 26 is designed such that the influence of the comparator 25 on the control voltage of the oscillator 23 is significantly smaller than that of the D / A converter 27. The D / A converter 27 thus roughly specifies the frequency, the phase comparator 25 is only used for fine control, which considerably improves the stability of the feedback loop and shortens the transient response.

If the laser for printing on a sheet is to be controlled using the circuit according to the invention, the number of pixels in a print line, i.e. the amount of data required for a line and the corresponding number of clock cycles are fixed.

This number, possibly plus the number of clock cycles between the end of writing a line and the beginning of the next writing process, is loaded into the programmable divider 21 as a division factor n.

The voltage-controlled oscillator 23 generates vibrations with the aid of an LC element. Compared to an RC oscillator, this structure has the advantage of better vibration stability. However, the consequence of the stability is that the currents and charges in the LC element cannot be changed as quickly as desired, so that the phase of the oscillator can only be adapted continuously and with a delay to a control signal. If, in the case of the clock generator shown in FIG. 5, the output signal of the oscillator 23 is used directly to drive the modulator 8, this delay can lead to a spread of the pixel positions in consecutive print lines. This problem is solved with the help of the counter 22. It has a reset input, to which the same phase control signal is present as to the phase comparator 25. When the phase control signal BD arrives, the counter reading in the counter 22 is reset to zero, which corresponds to setting the clock phase to a defined value. This process takes place regularly at the beginning of the line writing process, as a result of which the position of the pixels is precisely defined to l / m of their length in accordance with the divider ratio 1: m of the counter 22.

FIG. 6 shows a first variant of the clock generator from FIG. 5. Here, a delay element 29 is arranged between the beam detector 28 of the printer and the reset input of the counter 22. With this delay element 29, e.g. Controlled via the bus 2, every second control pulse from the divider 22 is delayed by half a period, so that the pixels in successive print lines are not mutually exclusive, but rather are mutually offset.

The same effect can be achieved with the variant shown in FIG. 7. In this case, data inputs of the counter 22 are connected to the internal bus 2, so that when a phase control signal arrives at the reset input of the counter 22, the value present at the data inputs is loaded into the counter 22, and counting continues from this value. This value can be changed by the computer each time the data corresponding to a pixel line has been transferred to the PWM circuit and e.g. alternately set to 0 and 4.

8 shows an alternative embodiment of a tunable clock generator. It is a circuit for digital functional synthesis, with a memory cher element 33, in which a plurality of support points of a function to be synthesized are stored, a fixed-frequency, highly stable oscillator 31 in the form of a quartz crystal, an address generator 32 which has a frequency predetermined by the oscillator that is higher than the pixels frequency, outputs addresses to the memory element, a D / A converter 34 and a low-pass filter 35. As shown in more detail in FIG. 9 as an example, the address generator 32 comprises a register 36 of 16 bits in width, into which the internal bus 2 a value can be entered. Controlled by the signal from the oscillator 31, the content of the register 36 is added to that of an accumulator 35 in an adder 37. The memory element 33 is addressed with the eight most significant bits d8-dl5 of the accumulator content. The memory element 33 then outputs a sequence of function values to the D / A converter 34 (FIG. 8), which generates an analog voltage signal therefrom. This signal has a basic frequency Fg = FQ ^• n: 2 ¹⁶ , where FQ denotes the frequency of the oscillator 31 and n the value stored in the accumulator 36. Because of the scanning process, a signal component with the frequency FQ is superimposed on this fundamental frequency. This is suppressed by the downstream low-pass filter 35, so that a signal is present at its output, the voltage profile of which is modeled on the function stored in the memory element 33.

Like the clock generators described in connection with FIGS. 5 to 7, this is also synchronized with the laser printer by a phase control signal BD. This phase control signal BD is received by a reset input of the address generator 32 and causes the scanning process to start again at a predetermined point in the course of the function to be simulated. Because of the high accuracy and time resolution of the quartz oscillator 31, no feedback control is required in this clock generator. In analogy to those in FIGS. 6 and 7, the BD signal can be fed to the reset input of the address generator 32 via a delay circuit such as the circuit 29, or the address generator can be designed such that the scanning process on arrival of the BD signal can start again at different points in the course of the function, the desired position in each case being able to be given to the address generator 32 via the bus 2.

The tuning range of the tunable clock generators described here can easily span one octave and more. In order to generate a clock signal with a constant amplitude in the entire frequency range, the output voltage of the D / A converter 9 and thus the slope of the sawtooth signal can be regulated inversely proportional to the clock frequency with the aid of the computer.

10 shows a preferred arrangement of the PWM circuit 50 according to the invention in a computer / printer system. Computer and printer 60 are connected via a conventional parallel interface 40, such as a Centronics interface. Text data is transmitted via this interface, in which only black and white representation, but no grayscale representation is required. The printer 60 can have a driver circuit 61 which is optimized for the font representation and which is addressed via the interface 40. The output signals of the PWM circuit 50 and the driver circuit 61 are given via a logical OR combination to the laser diode 62 of the printer in order to build up a print page consisting of text and grayscale images on the light-sensitive roller (not shown) in the shortest possible time. The connection 63 for the input of the PWM signal of the circuit 50 into the printer 60 is present as standard in laser printers from Hewlett Packard and is referred to as a “video port”.

The connection via the interface 40 is not absolutely necessary, since the PWM circuit 50 according to the invention is also capable of displaying black and white graphics and texts.

The PWM circuit according to the invention can be installed in the computer or in the printer, or its components can be distributed over both from the point of view of expediency. It can be hard-wired in their circuits or can be designed as a retrofittable plug-in card, hybrid circuit or ASIC. When configured as a retrofit kit, the ability to tune the clock generator has the particular advantage that the same circuit can be used without changes for laser printers with different aspect ratios, since the clock frequency of the circuit required to generate the density is predefined on the computer by suitable software drivers can be.

It is obvious that the technical teaching given here in connection with a black-and-white printer can be transferred to a color laser printer without substantial modifications to the processing of the individual basic colors.

The teaching is also not limited to use on laser printers. It only presupposes that the printer is set up to produce color dots of different, controllable sizes within one pixel of the printed image. Inkjet printers can also do this. Furthermore, it is obvious that the teaching is not limited to the bit widths of buses, memory elements and other elements mentioned by way of example in the description and the figures.

Claims

claims

PWM circuit for controlling the laser in a laser printer, with

- an interface (1) which can be connected to an external data source,

- A buffer memory (3a, 3b) with an input connection for receiving data via the interface (1) and an output connection which is independent of the input connection and which was previously received with a period (τ) predetermined by a clock generator (11) Forwards data values to an internal channel (4),

- a first D / A converter (7), the output signal level of which is updated with the period τ on the basis of the passed on data values,

- A modulator (8) which is a ramp generator

(81) and based on the output signal level of the first D / A converter (7) generates a pulse-width-modulated laser control signal with a modulation period, characterized in that the modulation period of the laser control signal is equal to the period τ and that the ramp generator ( 81) generates a ramp signal in the form of a symmetrical sawtooth voltage with the period τ.

Circuit according to claim 1, characterized in that the buffer memory comprises two memory banks (3a; 3b) which alternately receive with the interface (1) or can be connected to the internal data channel (4) for forwarding.

3. Circuit according to one of claims 1 to 2, characterized in that the buffer memory is constructed from freely addressable memory elements.

4. Circuit according to claim 1 to 2, characterized gekennzeich¬ net that the buffer memory is constructed from FIFOs.

5. A circuit according to claim 1, characterized in that the buffer memory is a two-port memory.

6. Circuit according to one of claims 1 to 5, characterized in that the data contained in the buffer memory can be output via the interface (1).

7. Circuit according to one of claims 1 to 6, marked by a filter (83) which distorts the output signal of the ramp generator (81).

8. Circuit according to claim 7, characterized in that the characteristic of the filter (83) via the interface (1) is externally controllable.

9. Circuit according to one of claims 1 to 8, characterized ge indicates that it comprises at least one sequencer (5a, 5b, 5c) which, in a first operating mode, breaks down a data value entered into the buffer memory into a first number of sections and which Outputs sections in succession.

10. Circuit according to claim 9, characterized in that the sequencer at least one second mode of operation points, in which it outputs a data value entered into the buffer memory unassembled or disassembled into a second number of sections.

11. A circuit according to claim 2 and claim 9 or 10, characterized in that each memory bank is assigned a sequencer (5a, 5b).

12. PWM circuit for controlling the laser in a laser printer, with

- an interface (1) which can be connected to an external data source,

a first D / A converter (7), the output signal level of which is updated with a period (τ) given by a clock generator (11) on the basis of data received via the interface (1),

- A modulator (8) which generates a pulse-width-modulated laser control signal on the basis of the output signal level of the first D / A converter, characterized in that the period (τ) of the clock generator (11) can be selected in a predetermined range is.

13. The circuit according to claim 12, characterized in that the clock generator has a phase control connection which can be connected to a control signal (BD) in order to set the phase of the clock signal to a predetermined value.

14. Circuit according to claim 13, characterized in that the clock generator (11) is a phase locked loop (PLL) circuit.

15. A circuit according to claim 14, characterized in that the PLL circuit is a voltage controlled oscillator (23), the control voltage of which is roughly predetermined by a D / A converter (27) and by a feedback phase comparator based on the phase control signal

(BD) is fine-tuned.

16. The circuit according to claim 15, characterized by a frequency divider (22), which generates the clock signal (LL) from the output signal of the oscillator (23) and has a reset input via which it can be put into a predefined phase can.

17. The circuit according to claim 16, characterized in that the phase control signal (BD) is present via a controllable delay element (29) at the reset connection.

18. Circuit according to claim 16, characterized in that the phase control signal (BD) is present directly at the reset connection and the predefined phase can assume several different values.

19. Circuit according to one of claims 12 to 13, characterized in that the clock generator (11) is a func tion synthesis circuit which comprises:

- a highly stable oscillator (31),

a memory element (33) in which a multiplicity of values of the function to be synthesized is stored,

- An address generator (32) which increases or decreases the addresses output to the memory element (33) by a selectable value in a time sequence determined by the oscillator (31), and

- A D / A converter (34) which generates the clock signal (LL) from the function values output by the memory element (33).

20. Circuit according to claim 19, characterized in that the function is a sine function.

21. Circuit according to claim 19 or 20, characterized by a low-pass filter (35) for stabilizing the clock signal output by the D / A converter (34).

22. Circuit according to one of claims 1 to 21, characterized in that the output of a second D / A converter (9), which can receive a data word via the interface (1), with a control input of the ram generator ( 81) is connected to control the slope of the ramp.

23. Circuit according to one of claims 1 to 22, marked by a memory element (6) which is addressed by means of the transmitted data and whose outputs are connected to the inputs of the first D / A converter (7).

24. Circuit according to claim 23, characterized in that the width of the data in the memory element (6) is greater than that of the data used for addressing the memory element (6).

25. The circuit according to claim 24, characterized in that the memory width of the memory element (6) is 10 bits and the address width is 8 bits.

26. Circuit according to one of claims 23 to 24, characterized in that the memory element (6) is a read-write memory, which can also be written and read via the interface.

27. Circuit according to one of claims 23 to 26, characterized in that a data decompression circuit is integrated in the memory element (6).

28. Circuit according to one of claims 1 to 27, characterized in that it is implemented on a plug-in card for connection to the video port (63) of a laser printer (60).

29. Circuit according to one of claims 1 to 28, characterized in that it is integrated on a chip or is constructed as a hybrid circuit.

30. Laser printer with a circuit (50) according to one of claims 1 to 29, characterized in that the interface (1) of the circuit (50) is provided for receiving image data and a second interface

(40) is provided for receiving text data.