Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
  • H05B47/20—Responsive to malfunctions or to light source life; for protection
  • H05B47/21—Responsive to malfunctions or to light source life; for protection of two or more light sources connected in parallel
  • H05B47/22—Responsive to malfunctions or to light source life; for protection of two or more light sources connected in parallel with communication between the lamps and a central unit
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
  • H05B47/10—Controlling the light source
  • H05B47/175—Controlling the light source by remote control
  • H05B47/185—Controlling the light source by remote control via power line carrier transmission

Definitions

• the present invention relates to a device for the remote control and monitoring of a discharge lamp.
• discharge lamps have a certain lifespan. They must therefore be replaced regularly, which poses some problems in the case of public lighting. Indeed, when it comes to monitoring the operation of a large number of candelabras distributed for example, in a city, it is necessary to have a lighting maintenance team which regularly carries out a test campaign consisting of to light the candelabras by day so that you can be sure visually of the proper functioning of the lamps, and possibly to replace the faulty lamps. To ensure good lighting quality with a low rate of faulty lamps, these campaigns must be carried out frequently. In practice, the maintenance team moves to change a reduced number of lamps, resulting in a high maintenance cost.
• the present invention aims to eliminate these drawbacks. To this end, it offers a device for the remote control and monitoring of a discharge lamp supplied by an electrical distribution network.
• This device is characterized in that it is installed near the lamp, and that it comprises means for transmitting and receiving messages conveyed by the intermediary of the electric power supply line of the lamp, by current modulated bidirectional carrier, allowing it to communicate with a central station, said device comprising means for controlling the switching on and off of the lamp, according to instructions issued by the central station, and means for detecting failures of the lamp and notify the central station.
• each candelabrum is controlled and monitored independently of the others, and it is not necessary to provide a telephone link between each electrical distribution cabinet and the central station.
• control and monitoring device comprises means for controlling the light intensity of the lamp as a function of instructions issued by the central station.
• control and monitoring device comprises means for detecting the degradation of the operating state of the lamp.
• the device comprises means for counting the operating time of the lamp.
• the device receives all the messages conveyed by the power line and retransmits messages which are not intended for it.
• the device can therefore play the role of repeater. As each candelabrum is usually found nearby
• FIG. 1 schematically represents the architecture of an electricity distribution network using the control and monitoring device according to the invention
• FIG. 2 shows the connection diagram of the control and monitoring device with a discharge lamp
• Figure 3 shows in detail the electrical diagram of the control and monitoring device
• Figure 4 shows a set of timing diagrams illustrating the operation of the control and monitoring device
• FIG. 5 shows a circuit for transmitting and receiving digital messages on the electrical distribution network.
• Figure 1 shows an electrical substation 1 for transforming the electricity into high voltage it receives, into low voltage (220 V) three-phase, to supply a set of 2.6 electrical distribution cabinets, including the cabinets distribution 6 allocated to public lighting.
• Each distribution cabinet 6 for lighting receives as input the three-phase low-voltage electric current, and supplies a set of electric lines 7 with single-phase low voltage.
• Each of these lines 7 comprises two wires 15, 16 making it possible to supply a plurality of discharge lamps 11 each associated with a control and monitoring device 10 according to the invention.
• the device 10 is designed to transmit and receive information by carrier current, in phase modulation, for example at a frequency of 132 kHz, via the electrical distribution network, to communicate with a central station 3 connected to another distribution cabinet 2.
• the central station is equipped with a computer 5, connected to the electrical network by means of an interface module 4 which exchanges information between the computer 5 and the electrical network.
• the control and surveillance device 10 is connected to the two wires, phase 15 and neutral 16 of an electric line, the neutral being also connected to one of the terminals of the discharge lamp 11.
• ballast 14 With high inductive impedance applying a supply voltage supplied by the device 10 to the lamp 11 and to the ignition circuit 13, the ballast 14 having the purpose of limiting the current passing through the lamp 11 when the latter is on.
• the lamp 11 When the lamp 11 is off, no current flows through it.
• the voltage applied to the input of the ballast 14 is then transferred to the ignition circuit 13 which makes it possible to apply to the terminals of the lamp 11 a voltage pulse (of the order of 2000 V) greater than the ignition threshold of the lamp, causing the lamp 11 to ignite, and therefore the passage of current therein.
• a voltage pulse of the order of 2000 V
• ballast 14 As the impedance of the ballast 14 is strongly self-inductive, it is imperative to have in parallel a capacitor 12 for correcting the cosine phi.
• a starting pulse generator is associated with the lamp 11 and ballast 14 assembly.
• control and surveil ⁇ lance device 10 comprises three stages, namely:
• a first stage ensuring the supply of the device, its coupling to the electricity distribution network, and the generation of a synchronization signal from the voltage Us supplied by the electric network, a second stage ensuring the control and monitoring of the discharge lamp 11, and
• a third stage organized around a microprocessor 23 ensuring the control of the entire device.
• the first floor includes:
• a supply circuit 21 which, from the voltage Us between the phase 15 and the neutral 16, supplies the supply voltages necessary for the various organs of the device 10,
• a coupling circuit 22 connected between phase 15 and neutral 16, designed to exchange information between the microprocessor 23 and the electrical network, and
• a synchronization circuit 22 also connected between phase 15 and neutral 16, designed to generate a logic signal SS synchronous with the electrical voltage Us supplied by the electrical network, this logic signal SS being applied to an input of the microprocessor 23.
• the coupling circuit 22 can be produced using a transformer or a resonant circuit of the LC type calibrated on the frequency of the carrier for transmission of messages by carrier current.
• the second stage, or output stage comprises, in series between phase 15 and ballast 14, an inductance Z1, followed by two switches K1, K2 in series.
• the first switch K1 of the relay or triac type, is controlled by the microprocessor 23, from the synchronization signal SS supplied by the synchronization circuit 27, and is intended to apply the voltage Us supplied by the network to the discharge lamp 11, and in particular to the correction capacitor 12 connected to the junction point between the two switches K1, K2.
• the load then being capaci- tive, the command Kl is applied to the zero crossing of the network voltage Us.
• the second switch K2 of the thyristor or triac type, is intended to supply the lamp 11 via the ballast 14. It is controlled by a logic signal CK2 from a comparator 30. It is also connected to neutral 16 by via a capacitive impedance Z3 intended to establish a current Iz when the lamp 11 is absent or has failed.
• a second synchronization circuit Z2 In parallel with the second switch K2, there is a second synchronization circuit Z2, called the lamp synchronization circuit, which delivers a logic lamp synchronization signal SL at 0 when the switch K2 is open, and at 1 when the latter is closed.
• the mains synchronization circuits 27 and lamp Z2 can be produced on the basis of photo-couplers so as to ensure good electrical insulation between the second and third stages.
• the third stage, or control stage, comprises, around the microprocessor 23:
• an EEPROM memory 24 making it possible to save information, in particular information related to the configuration of the device 10,
• a transmission / reception circuit 25 designed to modulate the information to be transmitted, supplied by the microprocessor 23, and to send the signal thus obtained to the coupling circuit 22, and to demodulate and amplify the information signals transmitted by the coupling circuit 22, and deliver the information thus obtained to the microprocessor 23, a digital / analog converter 29 making it possible to convert an opening angle setpoint supplied by the microprocessor 23 into an analog signal,
• the comparator 30 with two states which compares the setpoint supplied by the converter 29 with the sawtooth signal SI generated by an integrator 28 controlled by the synchronization signal SL coming from the circuit Z2.
• the microprocessor 23 is connected to two indicators, a red indicator 31 for signaling faults, and a green indicator 32 for signaling the operating states. It is also connected to an on / off button 33 and a button 34 which, when the lamp 11 is changed, triggers the transmission of an initialization signal to the central station 3, indicating the effective replacement of the lamp 11, and allowing the reset of a lamp usage time counter 11.
• the microprocessor 23 communicates with the central station 3 by messages transmitted by carrier current, in phase modulation, for example at a frequency of 132 kHz, via the electrical distribution network.
• each lamp 11 controlled by the central station 3 is identified by an identification code which is inserted in each message exchanged with the central station.
• the operation of the command and surveillance device is illustrated by the timing diagrams of FIG. 4.
• Curve C1 shows that the voltage Us between phase 15 and neutral 16, or else the voltage Uc at the junction point between the two switches K1, K2, has a sinusoidal shape.
• Curve C2 shows the shape of the logic sector synchronization signal SS from circuit 27, which changes logic state each time the mains voltage Us is canceled.
• the microprocessor 23 controls the switch Kl when the mains voltage Us crosses zero, thanks to the sector synchronization signal SS shown by the curve C2.
• the detection of a voltage UK2 at the terminals of the switch K2 by the lamp synchronization circuit Z2 leads to the release of the integrator 28.
• the comparator 30 delivers a voltage of command CK2 which allows the ignition of switch K2.
• Switch K2 is in turn controlled with a zero setpoint, implying a zero opening angle 41.
• the load of K2 is inductive, the current IB passing through it is therefore delayed by a certain phase shift 42 with respect to the voltage Uc (curve C4).
• the current IB which flows through the switch K2 determines the alternation. K2 therefore remains on as long as the current IB has not reached a value close to zero.
• the voltage UB (curve C3) at the terminals of the ballast 14 is then practically identical to the mains voltage Us.
• the lamp synchronization circuit Z2 delivers a logic signal SL at 1 each time that the absolute value of the voltage UK2 at the terminals of the switch K2 exceeds the threshold 45, that is to say, during the periods when the switch K2 is located blocked (curve C6).
• This logic signal SL is sent to the microprocessor 23, and is applied at the input of the integrator 28 which delivers a sawtooth signal which remains zero when the lamp synchronization signal SL is at logic level 0 (curve C7).
• the circuit described above makes it possible to reduce the voltage applied to the lamp 11, in order to reduce the intensity of the lighting.
• the microprocessor 23 can impose a setpoint in the form of binary data applied to the input of the analog / digital converter 29.
• this setpoint data is not zero, a logic signal is obtained at the output of the comparator 30 at 1 when the signal at the integrator output exceeds the threshold 46 defined by this setpoint, and at zero otherwise, the signal CK2 coming from the comparator 30 used to control the commutator K2 (curve C8).
• the switch K2 receives control pulses CK2 late with respect to the voltage pulses UK2 at its terminals, which delays the tripping of switch K2.
• the periods during which the current IB (curve C4) and the voltage UB (curve C3) remain zero, corresponding to the opening angle 41, are thus lengthened, which causes a reduction in the effective intensity of the current IB and of the effective voltage applied to the terminals of the lamp 11, and therefore a reduction in the intensity of the lighting produced by the lamp 11.
• Curves C9 to C13 illustrate the detection of lamp stalls.
• the stall or a breakdown of the lamp results in the absence of current IB at the input of the ballast 14.
• the load is then only determined by 1 * impedance Z3 placed between the switch K2 and the neutral 16, this load being insufficient to maintain switch K2 in the on state.
• the capacitive impedance Z3 is then crossed by a current Iz in phase advance 43, and practically in phase quadrature with the voltage Uc at the input of the switch K2 (curve C9).
• the resistive impedance of Z2 and the capacitive impedance of Z3 then form a voltage divider bridge so that the resulting voltage UK2 across the terminals of switch K2 is less than the trigger voltage threshold 45 of the latter (CIO curve ).
• the detection threshold 44 of the lamp synchronization circuit Z2 being much lower than the triggering threshold 45 of the switch K2, the lamp synchronization signal SL is therefore at logic level 1 in the vicinity of each zero crossing of the mains voltage Us (curve Cil ).
• Curve C12 shows the signal SI at the output of the integrator 28, obtained from the lamp synchronization signal SL having the shape of the curve Cil.
• the curve C13 shows the shape of the signal CK2 for controlling the switch K2 ,. which is at logic level 1 when the curve C12 exceeds the setpoint threshold 46.
• the voltage UK2 at the terminals of the switch K2 is. lower than the trigger threshold 45 thereof, it therefore remains blocked regardless of the command applied to it.
• the microprocessor 23 can determine whether the lamp 11 is off or on by comparing the sector synchronization signals SS and lamp SL. If the instants of the rising and / or falling edges of the signal SS correspond to instants when the signal SL is zero (curves 2 and 6), the lamp is detected on. Otherwise (curves 2 and 11) the lamp is detected off.
• the load is self-inductive.
• the switch K2 therefore has a hundred volts at its terminals to be triggered, and when the mains voltage Us crosses zero, the lamp synchronization signal SL is also at zero.
• the load becomes capacitive.
• the switch K2 therefore no longer has enough holding current IB, and the voltage at its terminals UK2 is insufficient to be able to be triggered.
• the lamp synchronization signal SL is at 1.
• each control and monitoring device 10 has variable instructions which can change depending on the state of the lamp it controls. This state is determined during the reduction regime: if the microprocessor 23 realizes that during the reduction in lighting intensity, the lamp goes off, it then decreases the reduction rate expected.
• the microprocessor 23 advantageously has 7 reduction rates, and when it reaches a predetermined alert rate, it alerts the central station 3 of the deterioration of the lamp 11.
• the microprocessor 23 is further designed to declare a faulty lamp 11 which no longer tolerates reduction or which can no longer prime at maximum voltage. In practice, a time delay of a few minutes is left to the ignition circuit 13 before declaring the lamp 11 faulty and notifying the central station 3.
• the operator When changing the lamp 11, the operator actuates the button 34, making it possible on the one hand to warn the central station 3 of the lamp change, and on the other hand to reset the variable parameters such as the reduction rate of the lamp lighting.
• the computer 5 of the central station 3 is connected to a database 8 where information concerning each lamp is stored and in particular:
• the computer 5 of the central station 3 can count the duration of operation of each lamp, and compare this duration to an alert threshold, the crossing of this threshold indicating that the lamp is to be replaced.
• the central station 3 can thus establish a list of lamps to be replaced by grouping together the information for exceeding this alert threshold, for lamp degradation detection, and for lamp in failure, so as to prepare and trigger replacement interventions, when the lamps to be tracked are in sufficient number. We can thus group the interventions in order to reduce the unit cost, the maintenance team being warned of changes in lamps to be provided before they are truly out of service.
• the transmission / reception circuit 25 shown in FIG. 3 is a phase modulation modulator / demodulator, of the synchronized asynchronous type, comprising for example, a first EXCLUSIVE OR gate 53 which combines a carrier F with the signal of the data to be transmitted from the connection terminal T x of the microprocessor 23, and delivers a signal modulated in phase or in phase opposition with the carrier as a function of the logic level 0 or 1 of the data to be transmitted.
• a phase modulation modulator / demodulator of the synchronized asynchronous type, comprising for example, a first EXCLUSIVE OR gate 53 which combines a carrier F with the signal of the data to be transmitted from the connection terminal T x of the microprocessor 23, and delivers a signal modulated in phase or in phase opposition with the carrier as a function of the logic level 0 or 1 of the data to be transmitted.
• the output of gate 53 is connected to coupling circuit 22 which is either positioned in transmission or in reception thanks to a signal T X R X transmitted by the microprocessor 23 and applied to the input E / R of coupling circuit 22.
• the coupling circuit 22 When the coupling circuit 22 is positioned in transmission, it has a low output impedance, of the order of a few Ohms. It also makes it possible to filter the signal emitted to transform it into a sinusoidal signal.
• the carrier Ft is obtained by means of an oscillator 54 controlled in frequency and in phase by a feedback loop applying a control voltage Ug at the input of the oscillator 54.
• This feedback loop comprises:
• an EXCLUSIVE OR gate 52 one input of which is connected to the output of the oscillator 54, a sampler-blocker constituted by a pulse generator 56 which controls a switch 60 whose input is connected to the output of door 52, and which makes it possible to charge a capacitor C ⁇ connected to ground,
• the pulse generator 56 delivers a signal d (Ft) consisting of one pulse at each edge of the input signal F, that is to say, two pulses per period of the signal Ft-
• d (Ft) consisting of one pulse at each edge of the input signal F, that is to say, two pulses per period of the signal Ft-
• the switch 60 is open between two pulses of the signal d (Ft)
• the voltage across the capacitor C ⁇ remains blocked at logic level 0 or 1 of the last value of the voltage sampled by the switch 60 when the latter has been closed during a pulse supplied by the generator 56.
• the signal T X R X also serves to control a switch 57 which makes it possible to select either the data signal F x received by the coupling circuit 22, or a signal F Q generated by an oscillator 58, preferably controlled by a quartz.
• This signal F Q has a periodic rectangular voltage having a constant frequency, equal to that of the carrier.
• the signal F Q OR F X selected by the switch 57 is sent to the input of the EXCLUSIVE OR gate 52.
• the control loop thus makes it possible to calibrate the frequency and the phase of the signal Ft delivered by the oscillator 54, at the emission, on those of the signal F 0 , and on reception, on those of the received signal F x .
• the switch 57 is positioned by the signal T X R X so as to apply the output signal F Q of the oscillator 58 to an input of the gate 52.
• the signal FQ being constant, the signal Ft generated by the oscillator 54 is also constant, as well as the signal d (Ft) generated by the pulse generator 6 and which controls the switch 10.
• the signal passing through the switch 60 charges the capacitor C ⁇ at logic level 0 or 1, which blocks the voltage across the capacitor at logic level 0 or 1 from the last sample taken to the next sample.
• the filter 62 makes it possible to obtain a voltage Ug for controlling the oscillator 54 so that the signal F corresponds in frequency to the signal FQ.
• the signal T x emitted by the microprocessor 23 begins with a start bit to allow the recipient of this signal to remove the uncertainty on the initial phase of the signal. On reception, the value of this start bit can be used to determine whether or not to invert the value of the following bits contained in the received signal.
• the coupling circuit 22 On reception, the coupling circuit 22 is positioned on reception by the signal T X R X , it then has a high input impedance, of the order of a few hundred Ohms, so as to transmit the data signal F X of the electrical network to an amplifier 59 which also performs filtering of the parasitic frequencies circulating on the electrical distribution network.
• the switch 7 is positioned by the signal T X R X so as to apply the signal F x to the input of the gate 52.
• the EXCLUSIVE OR gate 52 then combines the carrier with the received signal F x , to obtain a signal Ft + F x at logic level 0 or 1 depending on whether the received signal F x is in phase or in phase opposition with the carrier Ft, the signal Ft + F x being introduced into the control loop described above.
• the sampler-blocker constituted by the generator 56 which controls the switch 60, as well as the capacitor C ⁇ makes it possible to reset the received signal F x at constant phase with respect to the frequency Ft, and supplies the microprocessor 23 with the signal demodulated Uj available across the capacitor Cj.
• This demodulated signal is applied via an inverter 63, on the one hand to the input R x of the data received from the microprocessor 23, and on the other hand to the input P for detecting the carrier of the microprocessor 23 , through a pulse generator 64 and a time constant circuit 65.
• the microprocessor 23 can determine whether it should wait for reception of a message in the event of detection of the carrier on its R x input, and if it can send a message in the absence of a carrier.
• this circuit can transmit and receive a digital signal at the speed of 90 kilo-bits per second.
• the microprocessor 23 receives all the messages detected by the coupling 22 and reception 25 circuits, and commands the re-transmission of the messages which are not given to it. not intended. This solution makes it possible to order and monitor a large number of candelabras, thanks to the demodulation principle which makes it possible to achieve high transmission speeds.

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• Circuit Arrangement For Electric Light Sources In General (AREA)
• Remote Monitoring And Control Of Power-Distribution Networks (AREA)

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Citations (5)

• 1995
  • 1995-05-12 FR FR9505748A patent/FR2734118B1/fr not_active Expired - Lifetime
• 1996
  • 1996-05-10 ES ES96919886T patent/ES2160251T3/es not_active Expired - Lifetime
  • 1996-05-10 DE DE69613445T patent/DE69613445T2/de not_active Expired - Lifetime
  • 1996-05-10 EP EP96919886A patent/EP0766905B1/de not_active Expired - Lifetime
  • 1996-05-10 WO PCT/FR1996/000701 patent/WO1996036202A1/fr active IP Right Grant

Patent Citations (5)

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