WO1996021282B1 - D/a converter with constant gate voltage - Google Patents
D/a converter with constant gate voltageInfo
- Publication number
- WO1996021282B1 WO1996021282B1 PCT/US1995/016402 US9516402W WO9621282B1 WO 1996021282 B1 WO1996021282 B1 WO 1996021282B1 US 9516402 W US9516402 W US 9516402W WO 9621282 B1 WO9621282 B1 WO 9621282B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- fets
- digital
- voltage
- input
- analog converter
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 claims abstract 5
- 230000000875 corresponding Effects 0.000 claims 5
- 239000003990 capacitor Substances 0.000 claims 2
- 230000000051 modifying Effects 0.000 claims 2
- 230000004044 response Effects 0.000 claims 1
Abstract
A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage. The bias circuit comprises an amplifier (V1) and a p-type FET (X9), where the drain of the p-type FET is fed back to a non-inverting (NINV) input of the amplifier, and a reference voltage (VREF) is applied to an inverting input (INV) of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor (R1) is connected to the drain of the p-type FET.
Claims
1. A Digital to Analog converter, comprising: a bias FET having a gate, a source and a drain, said bias FET having a predetermined channel width and length and said source connected to a high DC voltage terminal; an amplifier having an output terminal, an inverting input terminal and a non-inverting input terminal, said output terminal directly connected to said gate of said bias FET, said inverting input connected to a reference voltage, and said non-inverting input connected to said drain of said bias FET, wherein said amplifier acts as a negative feedback amplifier; a resistor having a first end connected to said drain of said bias FET and having a second end connected to a low DC voltage terminal; and a weighted current source having n input ports each receiving one bit of an n-bit digital word, having n FETs each respectively connected to one of said n input ports, having a gate input connected to said output terminal of said amplifier, and having respective drains of each of said n FETs coupled together at an output port, wherein said gate input is connected to respective gates of said n FETs and wherein each of said n FETs has said predetermined channel width and length, and wherein said amplifier supplies a compensated gate voltage on said output terminal of said amplifier to each of said n FETs to compensate for changes in operating characteristics in said Digital to Analog converter.
2. A Digital to Analog converter according to claim l, further comprising a second resistor having a first end connected to said output port of said weighted current source and having a second end connected to said low DC voltage terminal, wherein an analog voltage corresponding to said n-bit digital word is formed across said second resistor.
3. A Digital to Analog converter according to claim 1, wherein said n FETs of said weighted current source have respective binary weightings in increasing powers of two to form a binary weighted current source.
4. A Digital to Analog converter according to claim 1, wherein said weighted current source further comprises: n on/off switches respectively connected to said n input ports, each of said n on/off switches having an on/off control port that receives a respective bit of said n-bit digital word, an input port receiving said compensated gate voltage from said amplifier, and an output port; n on/off not-switches each having an input port respectively connected to a high reference potential, said n on/off not- switches each having an on/off control port that receives a respective bit of said n-bit digital word, and an output port respectively connected to said output port of a respective one of said n on/off switches, wherein said n FETs each having a gate terminal respectively connected to an output port of a respective one of said n on/off switches and said n on/off not-switches, having a source terminal connected to said high reference potential, and having a drain terminal connected to said output port of said weighted current source, and wherein a current output from said output port of said weighted current source is supplied to a load.
5. The apparatus as recited in claim 4, wherein said current output is supplied to a second resistcr, and wherein said analog voltage corresponding to said n-bit digital word is read across said second resistor.
6. A Digital to Analog converter according to claim 1, wherein said n FETs and said bias FET are p-type devices.
7. A Digital to Analog converter according to claim 1, wherein said predetermined channel length is chosen to reduce channel length modulation associated with said bias FET and said n FETs.
8. The Digital to Analog converter according to claim 7, wherein said predetermined channel length is εipproximately equal to 10 microns. -25-
9. A Digital to Analog converter according to claim 1, further comprising: an Enable signal input for receiving an enable signal for said Digital to Analog converter; an invertor having an input end connected to said Enable signal input and having an output end; and a sleep FET having a source connected to said high DC voltage terminal, a gate connected to said output end of said inverter, and a drain connected to said output terminal of said amplifier, wherein when said Enable signal received on said Enable signal input is in a not enable state, said sleep FET is enabled, causing said gate input of said weighted current source to a high voltage level, and causing said n FETs in said weighted current source to be disabled.
10. A Digital to Analog converter according to claim 2, wherein said first resistor has a first resistance value and said second resistor has a second resistance value, wherein said first and second resistors are integrated circuits that are manufactured from a same wafer lot, wherein any changes in said first resistance value also occurs in said second resistance value due to common manufacture of said first and second resistors, and wherein a substantially constant ratio between the first and second resistance values is maintained as a result of the common manufacture.
11. A Digital to Analog converter according to claim 2, wherein said reference voltage is a voltage of VI volts, said first resistor has a resistance value of Rl ohms, and said second resistor has a resistance value of R2 ohms, and wherein an analog voltage read across said second resistor is determined by (Vref / Rl) * (Count / 64) * R2 = Count * 9.375 millivolts, wherein said Count corresponds to a base ten value of said n-bit digital word. -26-
12. A Digital to Analog converter, comprising: a bias FET having a gate, a source and a drain, said bias FET having a predetermined channel width and length and said source connected to a high DC voltage terminal; an amplifier having an output terminal, an inverting input terminal and a non-inverting input terminal, said output terminal directly connected to said gate of said bias FET, said inverting input connected to a reference voltage, and said non-inverting input connected to said drain of said bias FET, wherein said amplifier acts as a negative feedback amplifier; a first resistor having a first end connected to said drain of said bias FET and having a second end connected to a low DC voltage terminal; and a weighted current source having n input ports each receiving one bit of an n-bit digital word, having n FETs each respectively connected to one of said n input ports, having a gate input connected to said output terminal of said amplifier, and having respective drains of each of said n FETs coupled together at a output port, wherein said gate input is connected to respective gates of said n FETs and wherein each of said n FETs has said predetermined channel width and length; and a plurality of resistors connected in series and having a first one of said plurality of resistors connected to said output port of said weighted current source and ει last one of said plurality of resistors connected to said low DC voltage terminal, wherein said amplifier supplies a compensated gate voltage to each of said n FETs, and wherein a respective analog voltage is read across each of said plurality of resistors corresponding to a different analog voltage range.
13. A Digital to Analog converter according to claim 12, wherein said n FETs of said weighted current source have respective binary weightings in increasing powers of two to form a binary weighted current source. -27-
14. A Digital to Analog converter according to claim 12, wherein said weighted current source further comprises: n input ports for receiving an n-bit digital word to be converted to an analog signal, wherein n is an integer greater than one; n on/off switches respectively connected to said n input ports, said n on/off switches having an on/off control port that receives a respective bit of said n-bit digital word, an input port receiving said compensated gate voltage from said amplifier, and an output port; n on/off not-switches each having an input port respectively connected to a high reference potential, said n on/off not- switches each having an on/off control port that receives a respective one of said n-bit digital word, and an output port respectively connected to said output port of a respective one of said n on/off switches, wherein said n FETs each having a gate terminal respectively connected to an output port of a respective one of said n on/off switches and said n on/off not-switches, having a source terminal connected to said high reference potential, and having a drain terminal connected to said output port of said weighted current source, and wherein a current output from said output port of said weighted current source is supplied to one of said plurality of resistors, and an analog voltage based on said n-bit digital word is read across said last one of said plurality of resistors.
15. A Digital to Analog converter according to claim 12, wherein said n FETs and said bias FET are p-type devices.
16. A Digital to Analog converter according to claim 12, wherein said predetermined channel length chosen in order to reduce channel length modulation associated with said bias FET and said n FETs.
17. A Digital to Analog converter according to claim 16, wherein said predetermined channel length is approximately equal to 10 microns. -28-
18. A Digital to Analog converter according to claim 12, further comprising: an Enable signal input; an invertor having an input end connected to said Enable signal and having an output end; a sleep FET having a source connected to said high DC voltage terminal, a gate connected to said output end of said inverter, and a drain connected said output terminal of said amplifier, wherein when an Enable signal received on said Enable signal input is in a not enable state, said sleep FET is enabled, causing said weighted current source to a high voltage level, and causing said n FETs in said weighted current source to be disabled.
19. A Digital to Analog converter according to claim 12, wherein said plurality of resistors and said first resistor are integrated circuits that are manufactured from a same wafer lot, wherein any changes in resistance in one of said plurality of resistors also occurs in all others of said plurality of resistors, and wherein substantially constant ratios between resistances of said first resistor and each of said plurality of resistors is maintained as a result thereof.
20. A Digital to Analog converter according to claim l, wherein said bias FET and said n FETs are integrated circuits that are manufactured from a same wafer lot, wherein any changes in transistor characteristics in one of said n FETs also occurs in all others of s»aid n FETs due to common manufacture of said n FETs, and wherein the respective transistor characteristics in said n FETs and said bias FET are kept substantially similar as a result thereof.
21. A Digital to Analog converter according to claim 12, wherein said bias FET and said n FETs are integrated circuits that are manufactured from a same wafer lot, -29-
wherein any changes in transistor characteristics in one of said n FETs also occurs in all others of said n FETs due to common manufacture of said n FETs, and wherein the respective transistor characteristics in said n FETs and said bias FET are kept substantially similar as a result thereof.
22. A Digital to Analog converter according to claim 22, wherein a gain of the bias FET is equal to a gain of one of the n FETs, wherein each of the n FETs has a different gain, the gains being proportional to an amount of drain current for an amount of gain voltage.
23. A Digital to Analog converter according to claim 11, wherein said Digital to Analog converter is also operable as a voltage multiplier by varying the reference voltage as an input voltage to be multiplied, and by setting the n-bit digital word to a predetermined value corresponding to a logic one value for a particular bit of said n-bit digital word and a logic zero value for all other n-1 bits of said n-bit digital word, wherein said bias FET has a gain set to a gain of one of said n FETs which corresponds to said particular bit of said n- bit digital word, and wherein the reference voltage is multiplied by a value corresponding to a ratio of the second and first resistances in order to obtain a multiplied voltage that is read across the second resistor as a result thereof.
-30-
STATEMENT UNDER ARTICLE 19
In response to the International Search Report, mailed on 02 May 1996, the applicant has amended the claims by replacing present pages 17 through 22 with substitute pages 17 through 23 submitted herewith. The Abstract should be renumbered as page 24.
Applicant has reviewed the International Search Report, and the documents cited therein. Each document is discussed briefly below.
The document of Kakubo involves an A/D converter with a broad dynamic range input (see Abstract) . The broad dynamic range is accomplished in part by a variable gain amplifier in a first input path to the A/D converter and a second input path to the A/D converter that does not have any amplifier.
The document of Kanayama involves a successive approximation A/D converter which includes first, second and third comparator circuits (see Abstract) . The second and third comparators output warning signals when the input signal is outside the responsible input voltage range (see Figure 5) .
The document of Brooks involves a successive approximation register for use with either D/A converters or A/D converters. The register comprises an array of stages equal in number to the number of digital bits (see Abstract) .
The document of Naylor et al. involves a dual successive approximation A/D converter, which includes an 18-bit capacitor D/A converter. Details of the D/A converter are given in Figure 2, as well as col. 5, line 32 to col. 6, line 36. The D/A converter uses 18 binary weighted capacitors.
Applicant submits that the claims contained in substitute pages 17 through 23 possess novelty and inventive step over each of the above-*discussed documents.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8521030A JPH10511827A (en) | 1994-12-30 | 1995-12-29 | D / A converter with constant gate voltage |
| EP95943839A EP0804832A4 (en) | 1994-12-30 | 1995-12-29 | D/a converter with constant gate voltage |
| AU45212/96A AU4521296A (en) | 1994-12-30 | 1995-12-29 | D/a converter with constant gate voltage |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/366,566 | 1994-12-30 | ||
| US08/366,566 US5594441A (en) | 1994-12-30 | 1994-12-30 | D/A converter with constant gate voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1996021282A1 WO1996021282A1 (en) | 1996-07-11 |
| WO1996021282B1 true WO1996021282B1 (en) | 1996-08-22 |
Family
ID=23443566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1995/016402 WO1996021282A1 (en) | 1994-12-30 | 1995-12-29 | D/a converter with constant gate voltage |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5594441A (en) |
| EP (1) | EP0804832A4 (en) |
| JP (1) | JPH10511827A (en) |
| AU (1) | AU4521296A (en) |
| WO (1) | WO1996021282A1 (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3428380B2 (en) * | 1997-07-11 | 2003-07-22 | 株式会社東芝 | Semiconductor device for drive control of liquid crystal display device and liquid crystal display device |
| JP3164149B2 (en) * | 1997-08-21 | 2001-05-08 | 日本電気株式会社 | Variable current source circuit |
| JP3497708B2 (en) * | 1997-10-09 | 2004-02-16 | 株式会社東芝 | Semiconductor integrated circuit |
| US6226324B1 (en) | 1997-12-17 | 2001-05-01 | The Foxboro Company | Methods and systems for trimming a PWM signal |
| US6040737A (en) * | 1998-01-09 | 2000-03-21 | S3 Incorporated | Output buffer circuit and method that compensate for operating conditions and manufacturing processes |
| GB2349229B (en) * | 1998-05-15 | 2002-02-27 | Varma Trafag Ltd | Multipoint digital temperature controller |
| US6225929B1 (en) * | 1998-12-02 | 2001-05-01 | Hewlett-Packard Company | Digital-to-analog converter having switchable current sources and resistor string |
| AU5063999A (en) * | 1999-07-05 | 2001-01-22 | Vasu Tech Limited | Digital electronic control unit for domestic and commercial appliances |
| US8176296B2 (en) | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
| US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
| US8149048B1 (en) * | 2000-10-26 | 2012-04-03 | Cypress Semiconductor Corporation | Apparatus and method for programmable power management in a programmable analog circuit block |
| US8001052B2 (en) * | 2001-12-10 | 2011-08-16 | Dunkeld Bryan C | System and method for unique digital asset identification and transaction management |
| US6730953B2 (en) * | 2002-09-13 | 2004-05-04 | Mia-Com, Inc. | Apparatus, methods and articles of manufacture for a low control voltage switch |
| US6803680B2 (en) * | 2002-09-13 | 2004-10-12 | Mia-Com, Inc. | Apparatus, methods, and articles of manufacture for a switch having sharpened control voltage |
| US6759975B1 (en) * | 2003-06-19 | 2004-07-06 | National Semiconductor Corporation | Digital-to-analog converter with a shifted output and an increased range |
| US7864157B1 (en) | 2003-06-27 | 2011-01-04 | Cypress Semiconductor Corporation | Method and apparatus for sensing movement of a human interface device |
| US20110068765A1 (en) * | 2009-09-22 | 2011-03-24 | Qualcomm Incorporated | System and method for power calibrating a pulse generator |
| US8582374B2 (en) * | 2009-12-15 | 2013-11-12 | Intel Corporation | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56118362A (en) * | 1980-02-22 | 1981-09-17 | Toshiba Corp | Semiconductor integrated circuit device |
| US4431986A (en) * | 1981-10-09 | 1984-02-14 | American Microsystems, Incorporated | Digital to analog and analog to digital converters with bipolar output signals |
| US4546275A (en) * | 1983-06-02 | 1985-10-08 | Georgia Tech Research Institute | Quarter-square analog four-quadrant multiplier using MOS integrated circuit technology |
| JPH0646709B2 (en) * | 1985-02-28 | 1994-06-15 | キヤノン株式会社 | Digital / Analog converter |
| EP0217223B1 (en) * | 1985-09-30 | 1990-05-23 | Siemens Aktiengesellschaft | Digital-to-analog converter with temperature compensation |
| NL8600306A (en) * | 1986-02-10 | 1987-09-01 | Philips Nv | CIRCUIT FOR SUPPLYING A CONTROL VOLTAGE TO A POWER SOURCE CIRCUIT. |
| US4899152A (en) * | 1986-12-23 | 1990-02-06 | Analog Devices, Inc. | Method and apparatus for temperature compensating a digital to analog converter |
| JPH0810832B2 (en) * | 1987-03-04 | 1996-01-31 | 株式会社東芝 | Digital-to-analog converter |
| US4800365A (en) * | 1987-06-15 | 1989-01-24 | Burr-Brown Corporation | CMOS digital-to-analog converter circuitry |
| US4980836A (en) * | 1988-10-14 | 1990-12-25 | Compaq Computer Corporation | Apparatus for reducing computer system power consumption |
| US5023614A (en) * | 1989-09-13 | 1991-06-11 | Advanced Micro Devices, Inc. | Switchable DAC with current surge protection |
| JPH0775322B2 (en) * | 1990-02-22 | 1995-08-09 | 富士通株式会社 | Semiconductor integrated circuit device |
| DE69115088T2 (en) * | 1990-03-20 | 1996-05-09 | Fujitsu Ltd | Digital-to-analog converter with a circuit for compensating for output changes that depend on temperature changes. |
| US5221890A (en) * | 1992-03-16 | 1993-06-22 | Sierra Semiconductor Corporation | Reference generator |
| US5293166A (en) * | 1992-03-31 | 1994-03-08 | Vlsi Technology, Inc. | Digital-to-analog converter and bias compensator therefor |
| US5483150A (en) * | 1993-02-05 | 1996-01-09 | Hughes Aircraft Company | Transistor current switch array for digital-to-analog converter (DAC) including bias current compensation for individual transistor current gain and thermally induced base-emitter voltage drop variation |
| US5446457A (en) * | 1994-02-16 | 1995-08-29 | Sgs-Thomson Microelectronics, Inc. | Current-summing digital-to-analog converter with binarily weighted current sources |
-
1994
- 1994-12-30 US US08/366,566 patent/US5594441A/en not_active Expired - Fee Related
-
1995
- 1995-12-29 EP EP95943839A patent/EP0804832A4/en not_active Withdrawn
- 1995-12-29 JP JP8521030A patent/JPH10511827A/en active Pending
- 1995-12-29 AU AU45212/96A patent/AU4521296A/en not_active Abandoned
- 1995-12-29 WO PCT/US1995/016402 patent/WO1996021282A1/en not_active Application Discontinuation
-
1996
- 1996-01-04 US US08/582,946 patent/US5668550A/en not_active Expired - Fee Related
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