WO1996019885A1

WO1996019885A1 - Timed packet transmission method

Info

Publication number: WO1996019885A1
Application number: PCT/GB1995/002968
Authority: WO
Inventors: David Pritty
Original assignee: Galaxy Lans Ltd.
Priority date: 1994-12-21
Filing date: 1995-12-19
Publication date: 1996-06-27
Also published as: GB9425860D0

Abstract

An improved timed packet transmission method and system is described which can be used with both bidirectional and unidirectional linear bus structures. The method minimises the time delays between transmission of successive data packets by ensuring that active stations transmit in a collision free environment, where stations follow each other in transmission of their data packets in the order of their physical location on the bus. The method employs a timing reference signal transmitted from one end of the bus and a series of ascending predetermined time delays in each station reckoned either from receipt of the timing reference signal or from the end of the last data packet. Alternatively the method allows for the addition of a second timing reference signal generated from the other end of the bus, and associated time delays, to provide further improved performance.

Description

TTMED PACKET TRANSMISSION METHOD

The present invention relates to a timed packet transmission method which is appropriate where a number of stations (or nodes) wish to communicate with each other in a data communications network, and where the stations are interconnected using a bus topology, and said stations are located at a distance, for example more than 5 metres apart from each other. In particular, but not exclusively, the invention relates to the field of Local Area Networks (or LANs).

Any system which allows one or more transmitting stations to communicate with one or more receiving stations over a shared single communications channel configured as a bus structure, requires some form of demand adaptive time division multiplexing system to allocate the capacity of the shared channel to active stations. A common method of providing such (statistical) time division multiplex¬ ing is by sub-dividing the messages in the nodes into packets of data (of a fixed maximum size) and then providing a mechanism, normally called a medium access control mechanism, which allows each station in turn to transmit its data packet onto the shared communication medium. In systems where the stations are located close to each other (e.g. less than 5 metres apart) some centralised arbitration system can be used e.g. a central controller. However, in more physically distributed systems the normal approach is to use the same shared communications channel for access control signals and data signals.

Where the access mechanism has to operate over a bus, constraints imposed on the speed of the access mechanism by the basic nature of a bus can be particularly severe (especially with short packet transmission times and physically long buses). These constraints are firstly that any signal transmitted on a bus whether it be implemented by cabling, fibre optics or radiated energy (eg radio and infra-red) is broadcast so that it is received by all stations connected to it and secondly, that the maximum time between a station sending a signal and another station receiving the signal is the end-to-end propagation time of the bus.

The performance of one widely used method of bus access, Collision Sense Multiple Access /Collision Detect (CSMA/CD) is limited mainly by the second consideration; because here the lower limit of the contention slot time which defines the basis of the CSMA/CD back-off algorithims, is fixed by the fact that twice the end-to-end propagation time of the bus has to elapse after start of transmission before a station can be sure that it is the only station transmitting over the bus.

The performance of another widely used method of access, token passing, is limited chiefly by the first consideration because here the token has to be directed to one node at a time by the addition of adequate address information to the token. The time to transmit the token from one node to the next node (in the logical ring) plus the time for internal node processing and node to node propagation times generally yields fairly lengthy times to pass the token from one node to the next.

This time penalty has to be incurred even if the node does not have a data packet to transmit and thus the time for the token to circulate completely round the logical ring of such a network is therefore the node to node polling time multiplied by the number of network nodes. For networks with many nodes this causes significant delays at light loadings and also deteriorates the performance under heavier loadings.

Less widely used deterministic methods of bus access are bit map protocols such as (Multi Level Multi Access (MLMA). In each of these cases the total time taken bv the deterministic methods is based on the fact that the duration of each bit of information in the access method must equal or exceed the end-to-end propagation time of the bus. (e.g. 5 microseconds for a lKm. bus) so that all stations are aware of when each particular bit in the access protocol has been set.

It will be appreciated that the efficiency of an access protocol is limited by the ratio of packet transmission time to access time. This is of particular importance as increased data rates result in decreased transmission times for the same length of packet.

U.S. Patent No. 4,464,749, granted to Ulug, describes a bi-directional token flow system based on the use of virtual tokens. Each packet contains a source address, a destination address, a cyclic redundancy check and frame delimiters in the normal way. The right of a Bus Interface Unit - i.e. a BIU (or node) to transmit a data packet onto the bus is transferred from BIU to BIU by the passage of a virtual token. Ulug's invention uses a system of time delays, to ensure that no two BIUs receive a token at the same time and thus only one BIU will have the right to place its information on the bus at any given instant, i.e. when it receives the virtual token. These time delays are calculated dynamically as the network operates and are based on the value of the station's address for data packets. All BIUs listen to the bus and are only deemed to have received the virtual token if the bus is silent when their time delays expire.

European Patent No. 0456701 (Application No. 90902662.7) entitled DETER¬ MINISTIC TIMED BUS ACCESS METHOD and SYSTEM describes another system for providing collision free and deterministic access of nodes to a bus structure. In this system a timing reference signal or slot pulse is transmitted onto the bus from a master polling node which is located at a suitable point on the bus, conveniently at one end. The slot pulse is then used by all nodes connected to the bus as a unique time reference, at which all nodes start their internal delay timers. Nodes can only transmit a data packet when their delay timers have expired and the bus is silent at the expiry time for that particular node. If the increment between the delay times assigned to each node is made greater than twice the end to end propagation delay of the bus then collision free access to the bus is provided and the delay times can be allocated to nodes independent of their physical location and the polling node can be sited anywhere on the bus.

However, higher performance, collision free access to the bus can also be provided, if the polling node is located at one end and time delays are assigned to nodes which increase in value according to the order of the location of the node from the polling node. The arrangement being such that the value of the time delay at each node increases as one moves downstream - ie away from the polling node and the increase in time delays being such that any downstream node with a packet to transmit will detect that the bus is busy at the expiry of its (longer) time delay and will be unable to transmit.

This arrangement clearly results in nodes, with a queue of packets to transmit, which are located closest to the polling node being able to prevent transmission from downstream nodes, which also have packets to transmit. To overcome this bias European Patent No. 0456701 (Application No. 90902662.7) therefore describes an arrangement which ensures that once a node (say node "A") has transmitted one packet all other nodes with packets to transmit get a chance to transmit a packet each before node A can transmit another packet.

The problem with this approach is that nodes have to wait a significant time before they can be sure that all other nodes have transmitted their queued packets. This waiting time which can be defined as the "free slot time" has to be greater than the sum of twice the end to end propagation delay of the bus plus a time x, where time x is the time delay of the most downstream node and is therefore the largest value of any node delay timer.

The requirement for free slots to determine whether there are any nodes still waiting to transmit, obviously increases at high loadings where several packets can be queued at some nodes. This mechanism therefore wastes time under those specific conditions where it is particularly important to have efficient operation and results in the above protocol exhibiting bistable behaviour - that is exhibiting a higher average time delay in servicing queued packets at high loads than at lower loadings where there is no necessity for free slots. The improved performance at low loads arises because at low loads the average inter-packet gap is such that a free slot occurs naturally because no packets have arrived to be serviced whereas at high loads these free slots have to be artificially introduced by the protocol.

It will be appreciated that the efficency of any access protocol is limited by the ratio of the time the protocol takes to transfer the access opportunity from one node to the next, to the transmission time of a packet -where the access opportunity is defined here as the time at which a node may access the shared bus. The need to minimise the time the access method takes to transfer the access oportunity to the next queued packet transmission becomes particularly important for modern data communications networks which can employ long bus lengths and can operate at high data rates (e.g. from lOOMegabits/sec. to 1 Gigabits/sec. and above) giving short packet transmission times.

The object of this invention is to obviate or mitigate the disadvantges of the access method summarised above and previously disclosed in European Patent No. 0456701 (Application No. 90902662.7) This is achieved by providing a method whereby all nodes with data packets awaiting transmission when they detect a slot pulse are transmitted in a collision free round robin fashion, within the same slot pulse cycle, thus removing the basic bias in favour of nodes closest to the polling node exhibited by the system disclosed in European Patent No. 0456701 (Application No. 90902662.7). Transmission of several packets within the one slot pulse cycle is in contrast to the method disclosed in European Patent No. 0456701 (Application No. 90902662.7), where only the packet from the one active node closest to the polling node is transmited in any one slot pulse cycle and free slots have to be introduced to provide round robin service. A slot pulse cycle is here defined as the time between one slot pulse and the next.

According to one aspect of the present invention there is provided a method of providing deterministic access to a bus structure having two or more nodes connected thereto, in a data communications network, each node being capable of transmitting and receiving data packets to and from said bus structure and each node having a physical node address defined as the address for data packets, said method employing a polling or monitor node located at one end of the bus, capable of transmitting a series of timing reference signals or slot pulses, which are distinct and separate from the data packets, said slot pulses being used to provide a common time reference to all nodes such that, following each slot pulse by using a unique predetermined time delay in each node all active nodes may transmit data packets in a collision free manner, within the one slot pulse cycle, said method providing for round robin access for all nodes and said method further comprising the steps of:

a) arranging that the transmission state of each node is set to active if said node has a data packet to transmuit when it receives a said slot pulse, alternatively if said node does not have a packet ready to transmit at the time it receives the slot pulse it sets its transmission state to inactive, said node then maintaining said inactive transmission state until said node receives the next slot pulse, and each of said nodes which has set its transmission state to active being defined as an active node, and each of said nodes which has set its transmission state to inactive being defined as an inactive node;

b) arranging for each of said active nodes to transmit one data packet each at the expiry of a unique predetermined time, defined as the station time delay, said station time delay being predetermined at network configuration time, providing that each of said nodes detects silence on the bus at the station time delay expiry time, according to the following collision avoidance signal conditions:

i) arranging that once transmision of said data packet has started each node returns its said transmission state to inactive so that transmission of only one data packet is permitted at this time, ii) arranging that said station time delay in each of said nodes starts immediately after detection of a slot pulse, iii) arranging that the value of said station time delay in each adjacent downstream node is greater than the said station time delay in its immediate upstream neighbour, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the upstream neighbouring node transmits a data packet then the immediate downstream neighbouring node and all nodes further downstream will detect that the bus is busy at the expiry of their station time delays, where a node closer to the said monitor node is defined as an upstream node and a node further away from the monitor node is defined as a downstream node, iv) arranging that said station time delays in each of said nodes as well as starting immediately after detection of a slot pulse are also permitted to start immediately after the end of any data packet transmitted from another said active node is detected, such that all said active nodes transmit one data packet each subsequent to receipt of a single slot pulse;

c) supporting all data communications for said data packets and said slot pulses over a bus structure such that said data packets follow said slot pulses in the same shared data communications channel.

Conveniently, said monitor node generates the next slot pulse after it detects that a sufficient period of silence has elapsed to guarantee that there will not be a collision with any data packet about to be transmitted subsequent to the last slot pulse, said period of silence being defined as the next slot pulse wait time, and said next slot pulse wait time occuring either in the case where one or more nodes has transmited a data packet subsequent to the last slot pulse, or in the case when no data packets have been tranmitted subsequent to the last slot pulse, the value of said next slot pulse wait time being greater than the sum of twice the maximum end to end propagation delay time of the bus, plus the station time delay of the most downstream node on the bus, plus a safety time sufficient to cater for all tolerances in these times.

Alternatively in another embodiment of the invention, where the said shared data communications medium is a bidirectional linear bus, improved performance can be gained by arranging that the monitor node transmits the next slot pulse after it receives a uniquely identifiable signal pattern -called the monitor trigger signal from the most downstream node rather than waiting for the full said next slot pulse wait time to expire, the most downstream node transmitting said monitor trigger signal either shortly after: i) the expiry of the said station time delay in the most downstream node, if said node has been in the inactive state following on detection of the last slot pulse or ii) the end of the data packet being transmitted from the most downstream node.

Conveniently, where the said shared data communications medium is a linear bus, and the said nodes are assigned integer numbers 1 to N in order of their physical location on the said linear bus, starting with number 1 at the monitor node, the said delay times assigned to each node is given by the formula n.tj where n is the number of the node and t_d is a small fixed time delay designed to cope with the timing tolerances in electronic detection of signals on the bus and variations in relative propagation times between a slot pulse and a following data packet.

Preferably the method includes the step of equipping a number of nodes with monitor facilities when upon failure of the monitor node the next downstream node automatically assumes the monitor function.

Alternatively in another embodiment of the invention, additional performance over the previous embodiments may be achieved by the additional steps of providing a second monitor at the other - ie right hand - end of the bus structure such that separately detectable slot pulse signals are released in turn from the left hand and right hand monitors and said nodes become either left active or right active if they have a data packet to transmit when they receive a slot pulse signal from the left or right monitor respectively, said data packets being transmitted in a collision free manner using either left hand station delay times or right hand station delay times respectively, said method further comprising the steps of:

a) generating a uniquely identifiable signal defined as a left hand slot pulse - or SPL - from the monitor node which is located at the left hand end of the bus structure and generating another uniquely identifiable signal defined as a right hand slot pulse - or SPR - from the monitor node which is located at the right hand end of the bus structure;

b) arranging that when each of said nodes receives a said SPL it sets its transmission state to left active if it has a data packet ready to transmit at that time, and also arranging that when each of said nodes receives a said SPR it sets its transmission state to right active if it has a data packet ready to transmit at that time, alternatively if said node does not have a packet ready to transmit either at the time it receives an SPL or an SPR it sets its transmission state to inactive, said inactive transmission state persisting until said node receives the next (opposite hand) slot pulse;

c) arranging that after transmission of an SPL each of said left active nodes is permitted to transmit one data packet at the expiry of a unique predetermined time, defined as the left hand station time delay, providing that each of said nodes detects silence on the bus structure at the station time delay expiry time according to the following collision avoidance signal conditions: i) arranging that once transmision of said data packet has started each node returns its said left active transmission state to inactive so that transmission of only one data packet is permitted at this time, ii) arranging for said left hand station time delay in each of said nodes to start immediatelv after detection of an SPL, iii) arranging that the value of said left hand station time delay in each adjacent node which is further from the left hand monitor is greater than the said station time delay in its immediate neighbour which is closer to the left hand node, the increase in the value of said left hand station time delay being sufficient to ensure that if a neighbouring node closer to the left hand monitor transmits a data packet then its immediate neighbouring node and all other nodes further away from the left hand monitor will detect that the bus structure is busy at the expiry of their station time delays, iv) arranging that said left hand station time delays in each of said left active nodes as well as starting immediately after detection of an SPL may also start immediately after the end of any data packet transmitted from another node is detected, such that all left active nodes transmit one data packet each subsequent to detection of a single SPL;

d) arranging that if said right hand monitor is in the left active state when its left hand station delay time expires and the bus structure is silent it transmits one data packet and then shortly after the end of the data packet transmits an SPR, alternatively if the right hand monitor is in the inactive state and it detects that the bus structure is silent when its left hand station delay time expires it transmits an SPR at that time;

e) arranging that after transmission of an SPR each of said right active nodes is permitted to transmit one data packet at the expiry of a unique predetermined time, defined as the right hand station time delay, said right hand station time delay being predetermined at network configuration time, providing that each of said nodes detects silence on the bus structure at the station time delay expiry time according to the following collision avoidance signal conditions: i) arranging that once transmision of said data packet has started each node returns its said right active transmission state to inactive so that transmis¬ sion of only one data packet is permitted at this time, ii) arranging for said right hand station time delay in each of said nodes to start immediately after detection of an SPR, iii) arranging that the value of said right hand station time delay in each adjacent node which is further from the right hand monitor is greater than the said station time delay in its immediate neighbour which is closer to the right hand node, the increase in the value of said right hand station time delay being sufficient to ensure that if a neighbouring node closer to the right hand monitor transmits a data packet then its immediate neighbouring node and all other nodes further away from the right hand monitor will detect that the bus structure is busy at the expiry of their station time delays, iv) arranging that said right hand station time delays in each of said right active nodes as well as starting immediately after receipt of an SPR may also start immediately after the end of any data packet transmitted from another node is detected, such that all right active nodes transmit one data packet each subsequent to receipt of a single SPR;

0 arranging that if said left hand monitor is in the right active state when its right hand station delay time expires and the bus structure is silent it transmits one data packet and then shortly after the end of the data packet transmits an SPL, alternatively if the left hand monitor is in the inactive state and it detects that the bus structure is silent when its right hand station delay time expires it transmits an SPL at that time.

g) supporting all data communications for said data packets and said slot pulses over a bus structure such that said data packets follow said slot pulses in the same shared data communications channel.

Conveniently where the said shared data communications medium is a linear bus structure, and the said nodes are assigned integer numbers 1 to N in order of their physical location on the said linear bus structure, starting with number 1 at the most left hand node, the said left hand station delay time assigned to each node is given by the formula n.t_d where n is the number of the node and t_d is a small fixed time delay designed to cope with the timing tolerances in electronic detection of signals on the bus and variations in relative propagation times between a slot pulse and following data packets and further the said right hand station delay time assigned to each node is given by the formula (N+l-n).t_<j .

Preferably in the above embodiements the method includes the step of equipping all of the nodes with left and right monitor facilities when upon failure of the either monitor node the adjacent downstream node (to the failed monitor) automatically assumes the monitor function.

According to another aspect of the present invention there is provided a system for providing deterministic timed packet transmission access to a bus structure having two or more nodes connected thereto, in a data communications network, each node being capable of transmitting and receiving data packets to and from said bus structure and each node having a physical node address defined as the address for data packets, said system including a polling or monitor node located at one end of the bus capable of transmitting timing reference signals or slot pulses, which are distinct and separate from the data packets, said slot pulses being used to provide a common time reference to all nodes such that, following a slot pulse by using a unique predetermined time delay in each node all nodes may transmit data packets in a collision free manner, said system being equipped with control logic in each node to implement the timed packet transmission of the present invention comprising:

a) means for detecting said slot pulses within the control logic of each node, said means being defined as the slot pulse detector;

b) transmit state control logic means within each of said nodes which sets the transmission state of said node to active that when said node has a data packet ready to transmit when it detects a said slot pulse, alternatively if said node does not have a packet ready to transmit at the time it detects the slot pulse said transmit state control logic means within each of said nodes sets its transmission state to inactive, said transmit state control logic means within each of said nodes then maintaining said inactive transmission state until said node detects the next slot pulse, and each of said nodes whose transmit state control logic means has set its transmission state to active being defined as an active node, and each of said nodes which has set its transmission state to inactive being defined as an inactive node; c) means for detecting the presence and the end of a data packet on the bus, said packet detecting means being defined as the data packet detector;

d) means for generating a unique predetermined time delay within each node, said means being defined as the station delay timer, and the value of said station delay timer being predetermined ie set at network configuration time, said station delay timer being started from zero either immediately after detection of a slot pulse or immediately after detection of an end of packet signal from the data packet detector;

e) means for detecting whether the bus is busy or silent at any particular instant of time, said silence detecting means being defined as the bus silence detector;

0 means for controlling the transmission of one data packet from the node, said means being defined as the packet transmit control logic, and said packet transmit control logic initiating the transmission of a said data packet at the expiry of said station timer delay at each node according to the following collision avoidance signal conditions: i) the said node is in the active transmit state ii) the silence detector in said node detects that the bus is silent at the expiry of said station timer delay iii) the packet transmit control logic resets the transmit state control logic to the inactive state once transmision of said data packet has started so that transmission of only one data packet is permitted at this time iii) unique predetermined values have been assigned to the the station delay timers in each of the nodes, such that the value of said station time delay in each adjacent downstream node is greater than the said station time delay in its immediate upstream neighbour, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the upstream neighbouring node transmits a data packet then the immediate downstream neighbouring node and all nodes further downstream will detect that the bus is busy at the expiry of their station time delays, where "downstream" indicates that the downstream node is further from the monitor node and "upstream" indicates that the upstream node is nearer the monitor node;

g) bus structure means for supporting all data communications for said data packets and said slot pulses such that said data packets follow said slot pulses in the same shared data communications channel.

Conveniently, the monitor node contains timing delay means, defined as the next slot pulse timer, said next slot pulse timer ensuring that said monitor node waits for a sufficient period of silence to elapse to guarantee that there will not be a collision with any data packet about to be transmitted subsequent to the last slot pulse, before generating said next slot pulse, said period of silence being defined as the next slot pulse wait time, and said next slot pulse wait time occuring both in the case where one or more nodes has transmitted a data packet subsequent to the last slot pulse and in the case when no data packets have been transmitted subsequent to the last slot pulse, the value of said next slot pulse wait time being greater than the sum of twice the maximum end to end propagation delay time of the bus, plus the station time delay of the most downstream node on the bus, plus a safety time sufficient to cater for all tolerances in these times.

Conveniently all nodes include a next slot pulse timer and means for generating slot pulses, defined as the slot pulse generator, and these functions are activated by the monitor state logic, such that on failure of the monitor node the monitor state logic can activate these functions in the next downstream node so that it assumes the monitor function.

Alternatively in another embodiment of the invention, which provides higher performance and where the said shared data communications medium is a bidirectional linear bus, the system contains the additional capability wherein there is additionally provided a means of transmitting a uniquely identifiable signal pattern -called the trigger signal, from the most downstream node, said means being defined as a trigger pulse generator and means of detecting the trigger signal in the monitor node, said means being defined as the trigger pulse detector, and arranging for the trigger pulse detector to initiate transmission of the next slot pulse from the monitor node when the trigger pulse detector detects the trigger pulse signal from the most downstream node, this additional capability having the advantage of shortening the period of time that the monitor has to wait before it can safely release the next slot pulse, the time when said trigger pulse is transmitted being either shortly after:

i) at the expiry of the said station delay timer in the most downstream node, if said node has been in the inactive state following on detection of the last slot pulse or, ii) the end of the data packet being transmitted from the most downstream node;

Conveniently all nodes in the above embodiement additionally include means for generating slot pulses, together with a trigger pulse generator and a trigger pulse detector, and these functions are activated by the monitor/ trigger pulse state logic, such that on failure of the most downstream node the monitor/ trigger pulse state logic can activate the trigger pulse generator function in the next upstream node so that it assumes the trigger pulse function.

Alternatively in another embodiement of the invention, additional performance over the previous embodiments may be achieved by an alternative system which provides deterministic access to a bus structure having two or more nodes connected thereto, in a data communications network, each node being capable of transmitting and receiving data packets to and from said bus structure and each node having a physical node address defined as the address for data packets, said system additionally including a second monitor or polling node at the other - or right hand - end of the bus structure such that separately detectable slot pulse signals are released in turn from the left hand and right hand monitors and said nodes become either left active or right active if they have a data packet to transmit when they receive a slot pulse signal from the left or right monitor respectively said data packets being transmitted in a collision free manner using either left hand station delay timers or right hand station delay timers respectively, said system further comprising:

a) means for generating a uniquely identifiable signal defined as a left hand slot pulse - or SPL - from the monitor node which is located at the left hand end of the bus structure, said means being defined as slot pulse left generator, and means for generating another uniquely identifiable signal defined as a right hand slot pulse - or SPR - from the monitor node which is located at the right hand end of the bus structure, said means being defined as slot pulse right generator;

b) means for detecting slot pulse signals defined as a slot pulse detector, said slot pulse detector producing an SPL output signal on detection of an SPL and an SPR output signal on detection of an SPR;

c) means, defined as the transmit state control logic, for setting the transmission state to left active if it has a data packet ready to transmit when each of said nodes receives a said SPL and for setting the transmission state to right active if it has a data packet ready to transmit when each of said nodes receives a said SPR, alternatively if said node does not have a packet ready to transmit either at the time it detects an SPL or an SPR the transmit state control logic sets its transmission state to inactive, said inactive transmission state persisting until said node receives the next (opposite hand) slot pulse;

d) means for detecting the presence and the end of a data packet on the bus structure, said packet detecting means being defined as the data packet detector;

e) means for generating a unique predetermined time delay within each node, said means being defined as the SPL delay timer, and the value of said SPL delay timer being predetermined - ie set at network configuration time, said SPL delay timer being started from zero either immediately after detection of a left slot pulse or in the case of a left active station, immediately after detection of an end of packet signal from the data packet detector;

f) means for detecting whether the bus structure is busy or silent at any particular instant of time, said silence detecting means being defined as the bus silence detector;

g) means for controlling the transmission of one data packet from the node, said means being defined as the packet transmit control logic, and said packet transmit control logic initiating the transmission of a said data packet at the expiry of said SPL delay timer delay at each node according to the following collision avoidance signal conditions: i) the said node is in the left active transmit state, ii) the silence detector in said node detects that the bus structure is silent at the expiry of said SPL delay timer, iii) once transmision of said data packet has started the packet transmit control logic resets the transmit state control logic to the inactive state so that transmission of only one data packet is permitted at this time, iv) unique predetermined values have been assigned to the the SPL delay timers in each of the nodes, such that the value of said SPL delay timer in each adjacent node more distant from the left hand monitor is greater than the said station time delay in its immediate neighbour closer to the left hand monitor, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the neighbouring node closer to the left hand monitor transmits a data packet then the immediate neighbouring more distant node and all nodes further from the left hand monitor will detect that the bus structure is busy at the expiry of their SPL delay timers;

h) slot pulse generating means, included within the right hand monitor, for generating the next right slot pulse or SPR from said right hand monitor under the following two collision avoidance conditions: i) when its left hand station delay time expires provided the node has been in the inactive state and the bus structure is silent at that time, ii) shortly after the end of its data packet is the right hand monitor has been in the left active state; iii) means for generating a unique predetermined time delay within each node, said means being defined as the SPR delay timer, and the value of said SPR delay timer being predetermined - ie set at network configuration time, said SPR delay timer being started from zero either immediately after detection of a right slot pulse or in the case of a right active station, immediately after detection of an end of packet signal from the data packet detector; j) means for controlling the transmission of one data packet from the node, said means being defined as the packet transmit control logic, and said packet transmit control logic initiating the transmission of a said data packet at the expiry of said SPR delay timer delay at each node according to the following collision avoidance signal conditions: i) the said node is in the right active transmit state, ii) the silence detector in said node detects that the bus structure is silent at the expiry of said SPR delay timer, iii) once transmision of said data packet has started, the packet transmit control logic resets the transmit state control logic to the inactive state so that transmission of only one data packet is permitted at this time, iv) unique predetermined values are assigned to the the SPR delay timers in each of the nodes, such that the value of said SPR delay timer in each adjacent node more distant from the right hand monitor is greater than the said station time delay in its immediate neighbour closer to the right hand monitor, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the neighbouring node closer to the right hand monitor transmits a data packet then the im¬ mediate neighbouring more distant node and all nodes further from the right hand monitor will detect that the bus structure is busy at the expiry of their SPR delay timers;

k) slot pulse generating means, included within the left hand monitor, for generating the next left slot pulse or SPL from said left hand monitor under the following two collision avoidance conditions: i) when its right hand station delay time expires provided the node has been in the inactive state and the bus structureis silent at that time, ii) shortly after the end of its data packet if the left hand monitor has been in the right active state;

1) bus structure means for supporting all data communications for said data packets and said slot pulses such that said data packets follow said slot pulses in the same shared data communications channel. Conveniently, all nodes include both a slot pulse left generator and a slot pulse right generator, either of which can be activated by the monitor state control logic at the expiry of the node's station delay timer, so that upon failure of a left monitor or a right monitor an adjacent replacement node can take over the appropriate left or right hand monitor functions.

It will be appreciated that the timed packet transmission method and system can be implemented over a variety of types of bus structure without departing from the scope of the invention. For instance in the method and system which employs a single monitor the bus structure can be either a single linear bidirectional bus or a single folded unidirectional bus and in the method and system which employs two monitors the bus structure can be either a single linear bidirectional bus or dual opposing unidirectional buses where the left hand monitor is located at the left hand end of one of the unidirectional buses and the right hand monitor is located at the right hand end of the other unidirectional bus.

These and other aspects of the invention will become apparent from the following description when taken in combination with the accompanying drawings in which:

Fig. 1 is a block diagram of a data communications network, having several nodes inter-connected over a bi-directional linear bus, and provided with a timing reference signal or slot pulse generated from a monitor node located at one end in accordance with an embodiment of the invention to provide deterministic timed packet trasmission access of the nodes to the bus;

Fig. la is a two dimensional diagram which depicts the propagation of signals along the bidirectional bus shown in Figure 1. Its purpose is to show the propagation of the envelope of signals on the bus - that is the time between their start and finish - so that the progress of a signal (eg a data packet) can be clearly seen as it propagates over the bus - together with whether it will collide with another signal or not. In the diagram the horizontal axis represents distance along the bus and the vertical axis represents time. The diagram shows the direct correlation between the physical position of the node on the bus and where, on the distance axis, the signal starts to propagate from;

Fig. 2 is a schematic block diagram of the control logic within each node of the network of Fig. 1 for implementing the timed deterministic access protocol of the invention;

Fig. 3 is a two dimensional diagram which depicts the propagation of slot pulses and data packets on the bidirectional bus shown in Figure 1. The vertical axis of the diagram is not to any fixed scale - particularly the time to transmit packets is much shortened;

Fig. 4 is a block diagram of a data communications network, having several nodes inter-connected over a bi-directional linear bus, and provided with a timing reference signal or slot pulse generated from a monitor node located at one end and a monitor trigger node at the other end in accordance with a second embodiment of the invention to provide deterministic timed packet trasmission access of the nodes to the bus;

Fig. 5 is a schematic block diagram of the control logic within each node of the network of Fig. 4 for implementing the timed deterministic access protocol of the invention;

Fig. 6 is a two dimensional diagram which depicts the propagation of slot pulses and data packets on the bi-directional bus shown in Figure 4. The vertical axis of the diagram is not to any fixed scale - particularly the time to transmit packets is much shortened; Fig. 7 is a block diagram of a data communications network, having several nodes inter-connected over bi-directional linear bus, and provided with two separately identifiable timing reference signals or slot pulses generated from a left hand and a right hand monitor node each located one at each end of the bus in accordance with a third embodiment of the invention to provide deterministic timed packet trasmission access of the nodes to the bus;

Fig. 8 is a schematic block diagram of the control logic within each node of the network of Fig. 7 for implementing the timed packet trasmission access protocol of the invention;

Fig. 9 is a two dimensional diagram which depicts the propagation of slot pulses and data packets on the bi-directional bus shown in Figure 7. The vertical axis of the diagram is not to any fixed scale - particularly the time to transmit packets is much shortened;

Fig. 10 is a block diagram of a data communications network, having several nodes inter-connected over a single unidirectional linear folded bus, and provided with a timing reference signal or slot pulse generated from a monitor node located at one end in accordance with a fourth embodiment of the invention to provide deterministic timed packet trasmission access of the nodes to the bus;

Fig. 11 is a schematic block diagram of the control logic within each node of the network of Fig. 10 for implementing the timed deterministic access protocol of the invention;

Fig. 12 is a two dimensional diagram which depicts the propagation of slot pulses and data packets on the unidirectional linear folded bus shown in Figure 10. The vertical axis of the diagram is not to any fixed scale - particularly the time to transmit packets is much shortened. Reference is first made to Fig. 1 of the drawings which illustrates a data communications network comprised of a monitor node (node 1) and three other nodes numbered 2 to 4 connected to a common data communications path implemented using a bi-directional linear bus. The nodes 14 and the monitor or polling node 12 are connected to the bus 10 through a bus transceiver circuit 16. It will be appreciated that a plurality of nodes are connected to the bus but only four nodes 1 to 4 are shown in the interest of clarity.

Fig. 1 illustrates a data communications network wherein node 12, which is located at one end of the bi-directional linear bus 10, performs the monitor or polling function to control the access of all nodes to the bus. It will be appreciated that although only the monitor function will be described, node 12 is also capable of transmitting and receiving data packets to and from the bus 10 to support normal data communications with the other nodes 14. It will be further appreciated that other nodes also contain the polling function such that on failure of node 12 the next adjacent node (i.e. Node 2) can take over the monitor function as is well known in the art.

Each node will typically consist of a host computer, such as a personal computer or workstation, and circuitry which may be contained on a separate adapter board or communications controller board. In common with the approach normally used in the art, this communications circuitry will typically comprise three distinct components namely: i) all the logic and communications hardware to handle the transfer of the blocks of data, which make up the data packets, between the host computer's memory (where data is held in parallel) and the shared medium of the network (which uses a serial data stream), ii) control logic to implement the the medium access control protocol i.e. the deterministic timed packet transmission access protocol of this invention, iii) transceiver logic which provides the conversion between the logic signal levels employed in the packet handling and medium access control logic - e.g. TTL- and the signal levels used on the shared medium of the network -i.e the interconnecting bus. This transceveiver logic also contains any encoding/ decoding required to produce the signal format used on the bus together with any electronic isolation required between the bus cabling and the adapter board circuitry.

Typically the data communications and control circuitry is implemented in a large scale integrated microprogrammed control chip. One example of such a large scale microprogrammed chip, which is of course specific to the case of the Ethernet IEEE 802.3 network is the AMD Ethernet Local Area Network Controller. This chip performs the first two functions described above, and therefore as well as containing the packet handling logic it contains the medium access control circuitry to implement the CSMA/CD bus access algorithm of Ethernet. Typically also, the data packet control chip is supplemented by either a microprocessor system or other dedicated large scale integration logic devices e.g. to provide DMA transfers of the blocks of data to and from the host computer's memory.

Typically, as in the case of the IEEE 802.3 Ethernet network, the third function referred to above, is be performed by an AMD Serial Interface Adapter chip (or SI A). The SI A converts the TTL compatible signal levels used by the packet handling and CSMA/CD medium access control logic into the signal levels specified for the Ethernet bus. The SIA also Manchester encodes the separate clock and data signal outputs produced by the packet transmit logic. The chip also reeives the incoming Manchester encoded signal from the bus and decodes it to recover a separate clock and data stream. Transformers provide the required isolation.

It will be appreciated that different types of networks at operating at higher data rates use different access protocols and encoding methods and faster logic. For instance the lOOMegabits/sec. Fibre Distributed Data Interface (or FDDI) uses an AMD chip set called the Taxi chipset to performs the same three basic functions described above - although FDDI uses an early token medium access method and NRZI 4B/5B encoding scheme to the physical layer (which can be either fibre or copper).

Referring now to Fig. 2, this depicts the functional blocks required to implement the deterministic timed packet transmission access protocol of one embodiment of the invention, wherein all nodes 14 also contains the logic to become a Monitor Node 12. However, for the sake of clarity, with the exception of the data packet transmit buffer 30 and the bus transceiver 16, Fig. 2 omits all the circuitry necessary to transmit and receive data packets and to transfer them to (and from) the memory of the host as this circuitry is well known in the art - as described above. Also omitted from Fig.2 for the sake of clarity are the means of setting initial states /values into the logic - for instance into the timers and the monitor state logic.

Each node is equipped with the following components to implement the deterministic timed packet trasmission access protocol of the invention:

transmit state control logic 20, a slot pulse detector 22, a bus silence detector 26, a station delay timer 24, a data packet detector 32, packet transmit control logic 28, a packet transmit buffer 30. In addition in order to fulfill the monitor function, the nodes are equipped with a next slot pulse timer 34, a slot pulse generator 36, and monitor state logic 38. The operation of these elements will be later described.

The operation of the system will now be described with reference to Figs. 1, 2 & 3. [Operation of the system for a medium speed data rate i.e. (10 Mbps) will be described although it will be understood that much higher and lower data rates can be used.

Referring to Fig. 2 the transceiver 16 transmits and receives serial data signals and slot pulses to and from the bus and converts out going signals from the logic signal levels used within the node (e.g. TTL) to the signal levels used on the bus 10 - and performs the inverse process for incoming signals. Additionally the transceiver performs the encoding and decoding functions between the separate clock and data signals of the node and the self-clocking signals transmitted over the bus using Manchester encoding/ decoding or other forms of encoding and decoding as is well known in the art.

Considering now the operation of the logic within the node as shown in Fig. 2, the monitor state logic 38 in the monitor node 12 sets the monitor state to active and the monitor state logic 38 in the other nodes 14 sets the monitor state to inactive - so that only node 12 can trasmit slot pulses from its slot pulse generator 36 at appropriate times determined by the next slot pulse timer 34. The transmit state control logic 20, contained within all nodes 14 and 12, maintains the nodes in the inactive state for transmission of data packets unless the node has a data packet ready to transmit when it receives a slot pulse signal.

Referring now also to Fig. 3 all nodes 14 (and 12) therefore remain silent until the slot pulse 40 is transmitted from the monitor node 12. This signal 40 propagates uni-directionally along the bus and is received by each node 14 after its release at a time corresponding to the product of the physical distance of the particular node from the monitor node 14 and the propagation rate of the medium - as shown in Fig. 3 - e.g. Node 2 receives the slot pulse at time instant 43.

When the slot pulse detector 22 in each node detects a slot pulse 40, the transmit state control logic 20 either maintains the node in the inactive state if it does not have a data packet ready to transmit at that time or the transmit state control logic 20 sets the node's transmit state to active, via the packet transmit control logic 28, if it has a data packet ready to transmit when it receives the slot pulse 40. Also on detection of a slot pulse 40 all nodes start their station delay timers 24 from zero.

All active nodes have a chance to transmit onto the bus 10 if it is silent when their station delay timers expire but only the active node nearest to the monitor, will find the bus silent when its station timer delay expires and therefore only that node will be able to transmit its data packet as is explained below.

Each node is equipped with a station delay timer 24 which contains a unique predetermined time delay which is predetermined at network set up or configuration time rather than at normal run time. The values of the station delay timers are chosen such that the time delay in a node closer to the monitor node always has a lower value of time delay, ie the value of the station time delay in node n is always less than the delay in node n+1, where the nodes are numbered 1 to N in order of their physical location on the bus starting with node 1 as the monitor node.

Conveniently the station delay timers 24 are set to a value n.t_d where n is the number of the node according to its physical position from node 12, and t_d is a small delay, which is greater than the maximum timing tolerances for detection of slot pulses and data packets (for example 10 data bits or 1 microsecond per node for a lOMegabits/sec. data rate or lOnanoseconds for a 1 Gigabits /sec. data rate) and thus the station delay timer in the most downstream node (ie the one furthest from the polling node) has the value N.t_d.

Referring to Fig. 3 it can be seen that the time gap between the slot pulse 40 and a data packet e.g. the packet 46 from Node 2 remains constant downstream of the node position and thus all nodes downstream of node 2 which have larger values in their station timers will find that the bus is busy when their delay timers expire as explained in detail for the illustrative case shown in Fig. 3, where both Nodes 2 and 3 have packets ready to transmit but Node 1 does not. The transmit state control logic 20 in Nodes 1 and 4 sets the transmision state of both nodes to the inactive state when the slot pulse detectors 22 in these nodes detect the slot pulse 40.

The transmission state control logic 20 in nodes 2 and 3 sets the transmision state of these nodes to active when the slot pulse detectors 22 in these nodes detect the slot pulse 40 - at time instants 43 and 47 respectively. [Fig. 3 shows the time instant 42 at which Node 1 would have started to transmit its data packet had it been in the active state.]

Node 2 is in the active transmit state and its bus silence detector 26, which continuously monitors the state of the bus to determine whether it is silent or busy with a data packet or slot pulse, detects that the bus is silent when its station delay timer 24 expires at a time 2.t_d after the end of the slot pulse - time instant 44 in Fig. 3. These two logical conditions are fed to the packet transmit control logic 28 which initiates transmission of a data packet 46 onto the bus 10 through transceiver 16 from the packet transmit buffer 30 and the host computer's memory. Once transmision of the packet has started, the transmit state reset signal from the packet transmit control logic 28 resets the transmit state control logic 20 to the inactive transmission state.

Node 3 is also in the active transmit state but its bus silence detector 26 detects that the bus is busy when its station delay timer 24 expires at time 3.t_d after the end of the slot pulse - time instant 48 in Fig.3, thus not satisfying the logical conditions required by the packet transmit control logic 28 in Node 3 to initiate the transmission of a data packet onto the bus.

Since node 3 has not yet transmitted its packet its transmit state remains active and when its data packet detector 32 detects the end of the data packet (transmitted from Node 2), Node 3 restarts its station delay timer 24 from zero when it detects bus silence at the end of the data packet - ie at time instant 50. The bus silence detector 26 in Node 3 now detects that the bus is silent when the station delay timer 24 expires at time 3.t_d after the end of the slot pulse - time instant 52 in Fig.3, and these two logical conditions cause the packet transmit control logic 28 to initiate transmission of a data packet 51 onto the bus 10 from the packet data buffer 30 and the host computer's memory. The transmit state reset signal from the packet transmit control logic 28 then resets the transmit state control logic 20 in Node 3 to the inactive transmission state.

From the above desccription it can be seen that if any nodes downstream of Node 3 were in the active state then they would be able to transmit a data packet each onto the bus, with the first active downstream node, node n say, starting to transmit its data packet at a time n.t_d after it detects the end of the data packet 46 from Node 3, and nodes further downstream starting in order of their physical location on the bus.

By using the above protocol all nodes which have packets to transmit when they detect the slot pulse 40 get a chance to transmit their data packets, subsequent to receipt of a single slot pulse, in order of their physical location on the bus and without the packets colliding with each other.

Since by now all nodes are in the inactive transmit state, either since receipt of the last slot pulse or subsequent to transmission of a data packet another slot pulse has to be transmitted to allow nodes with further packets waiting be transmitted to enter the transmit active state. Using the bus silence detector 26 and the next slot pulse timer 34, which is reset to zero when any signal is detected on the bus 10, the monitor node 12 therefore now waits a sufficient period of time to be sure that silence has persisted on the bus after the time the most downstream node would have transmitted a data packet and there are therefore no packets about to be transmitted which could collide with the next slot pulse. This sufficient period of silence, is defined as the next slot wait time.

In the case when nodes 1 to N have been assigned station delay times n.t_d the largest station time delay at the most downstream node, node N, is N.t_d and the longest station delay time before a packet to be released is therefore N.td after the end of the last packet - ie the station delay time lasts from time instant 53 to time instant 54 in Fig. 3. Referring again to Fig.3 it can be seen that the monitor could release its next slot pulse any time after time 56 instant on Fig. 3 - since a packet from node N would reach the monitor by then.

However since the monitor is unaware of the physical position of the last node to transmit the next slot pulse timer 34 in the monitor node 12 is set to a value which allows for the worst case - namely that the last node to transmit was located physically close to the monitor node. Under these conditions the next slot pulse timer 34 in the monitor node 12 must wait for a period of silence, indicated by the bus silence detector 26, sufficiently greater than 2.T_p + N.t to allow for all end to end propagation delay and electronic timing tolerances before initiating transmis¬ sion of another slot pulse 59 from the slot pulse generator 36, where T_p is the maximum end to end propagation delay of the bus - i.e from time instant 55 to time instant 58 in Fig. 3. The safety time margin in the next slot pulse wait time is omitted from Fig. 3 for the sake of clarity.

It will be appreciated that when no nodes transmit a data packet following a slot pulse, the monitor node waits for the same period of silence - the next slot wait time - and then transmits a slot pulse.

With the release of slot pulse 59 any packets waiting can be transmitted according to the deterministic timed packet transmission protocol of this invention and the cycle of events described above is repeated. The above describes the operation of the invention with a bi-directional linear bus. In all arrangements it will be understood that compared to existing methods of bus access such as token passing the method provides rapid access to a bus for a waiting packet and thus minimises access time delays. This feature is of particular importance for short packet transmit times which occur with high data rates and with short packet lengths.

Various modifications may be made to the timing reference arrangements which control the timed packet transmission protocol hereinbefore described without departing from the scope of the invention. The first modification according to another embodiment of the invention is to inform the monitor node as early as possible that it is safe to release the next slot pulse (eg at time instant 56 in Fig.3). In this modification the most downstream node is equipped with the additional capability wherein it transmits a uniquely identifiable signal pattern -called the monitor trigger signal which is used to initiate the transmission of the next slot pulse from the monitor node.

Operation of the system is now described with reference to Fig. 4 of the drawings which is a block diagram showing a data communications network implemented over a bi-directional linear bus. Nodes 2 and 3 (numbered 62 in Fig. 4) operate exactly as described for the system shown in Fig.l but there is now added to Node 4, the most downstream node 64, means for generating a trigger pulse signal and the Monitor Node 60 is further equipped with means for detecting said trigger pulse signal. It will be appreciated that it is convenient to include the monitor function and the trigger pulse function in all nodes so that on failure of a Monitor or a Monitor Trigger node other nodes can take over these functions - but only to activate the monitor function in node 60 and the trigger pulse function in the most downstream node ie node 64.

Referring now to Fig. 5, this depicts the functional blocks required to implement the deterministic timed packet trasmission access protocol in this embodiment of the invention, such that any node contains the logic to become a monitor node or a monitor trigger node. It can be seen that the nodes contain the same components as shown in Fig.2 but with additional components to implement earlier release of the next slot pulse - namely a trigger pulse generator 66 and a trigger pulse detector 68 and expansion of the monitor state logic function 69 to include logic to activate/ deactivate the trigger pulse generator, where node 60 is activated as a monitor node and node 64 is activated as the monitor trigger node and nodes 62 have both the monitor and the trigger pulse functions deactivated.

It will be appreciated that since nodes 2 and 3 (nodes 62) have exactly the same functional blocks active as nodes 12 in Fig. 1 they will respond exactly as herinbefore described and the differences in operation of the system are restricted to transmission of a trigger pulse by node 64 and detection of the trigger pulse by the monitor node 60. Therefore only these aspects will be described in any detail.Refering now to Figs. 4 & 5 as well as Fig. 6 it will be appreciated that nodes 2 and 3 which both have packets ready to transmit when they detect the slot pulse 70 start transmission of their packets 73 and 75 respectively at time instants 72 and 74 respectively according to the deterministic timed packet transmission protocol of this invention all as hereinbefore described.

It will further be appreciated that in the previous embodiement of the invention the monitor node 12 had to wait for a period of silence sufficiently greater than 2.T_p + N.t_d to allow for all end to end propagation delay and electronic timing tolerances before initiating transmission of another slot pulse from the slot pulse generator 36 - ie from time instant 79 to time instant 82 in Fig. 6. However, as described above, it is quite safe for the monitor node 60 to transmit the next slot pulse earlier than time instant 82.

There are two cases which govern the exact period of silence the monitor has to wait before transmitting the next slot pulse. The first case is where the most downstream node 64 is in the inactive state after receipt of slot pulse 70 and the second case is where the most downstream node 64 is in the active state after receipt of slot pulse 83 and transmits a data packet. Fig. 6 shows the operation of this embodiment of the invention for these two cases.

In the first case the node 64 does not know whether another upstream node e.g. node 3 wishes to transmit a data packet and it thus has to wait until its station delay timer 24 has expired, which is time N.t_d - i.e. until time instant 76 after it detects the end of the data packet 75 before it can transmit a trigger pulse 78 from its trigger pulse generator 66 under control of its monitor/ trigger state logic 69. [The links between the station delay timer 24, the transmit state control logic 20 and the monitor trigger pulse control logic 69 which controls the trigger pulse generator 66 are omitted from Fig. 5 for the sake of clarity.] This trigger pulse 78 will be received by the monitor 60 at time instant 80 allowing it to transmit a slot pulse 83, from its slot pulse generator 36 at that time, rather than waiting until time instant 82 - which is N.t_d + 2.T_p after the monitor 60 detects the end of data packet 75, at time instant 79.

In the second case the most downstream node 64 is in the active state after receipt of slot pulse 83 and transmits its data packet 84, starting at time instant 85 when its station delay timer 24 expires, and since it knows (from its monitor/ trigger pulse state logic 69) that it is the most downstream node (and no further packets can be transmitted) it transmits a trigger pulse 86 from its trigger pulse generator 66, under control of its monitor/ trigger state logic 69 and the data packet detector 32, shortly after the end of its data packet 84. [The links between the data packet detector 32, the transmit state control logic 20 and the monitor trigger pulse control logic 69 which controls the trigger pulse generator 66 are ommitted from Fig. 5 for the sake of clarity.] The trigger pulse 86 is then received by the monitor node 60 at time instant 88 allowing the monitor node to transmit the slot pulse 90 immediately - rather than waiting a further time interval N.t_d + 2.T_p after the end of data packet 84.

Conveniently when either the monitor node or the monitor triggger node fails then an adjacent node is activated by its monitor/ trigger state logic to assume the appropriate function.

Another embodiment of the invention to provide deterministic timed packet release employs a polling or monitor nodes located at both ends of the bus. In this embodiment the monitor node located at the left hand end of the bus transmits a slot pulse which is separately identifiable from the slot pulse transmitted by the monitor located at the right hand end of the bus.

Operation of the system will now be described by reference first to Fig.7 of the drawings which shows a left monitor 100 located at the left hand end of the bi-directional linear bus 10 and a right monitor 104 located at the right hand end of the bi-directional linear bus 10 and nodes 102 located in between the monitors. It will be appreciated that description of the operation of nodes 102 for the purpose of transmison of data packets also applies equally to monitor nodes 100 and 104. All nodes are connected to the bus 10 through a transceiver 16, as is well known in the art.

Referring now to Fig. 8, this depicts the functional blocks required to implement the deterministic timed packet transmission access protocol in this embodiment of the invention, such that all nodes contain the logic to become a a left hand monitor node or a right hand monitor node, but that only node 100 is activated to become the left hand monitor by its monitor state logic 139 and only one other node 104 is activated to become the right hand monitor by its monitor state logic 139.

Each node is equpped with:

transmit state control logic 120, a slot pulse detector 122, which provides and SPL output when it detects a left slot pulse and an SPR output when it detects a right slot pulse, a bus silence detector 126, a left hand station delay timer or SPL delay timer 124, which applies a station delay time to left slot pulses, a right hand station delay timer or SPR delay timer 134, whch applies a station delay time to right slot pulses, a data packet detector 132, packet transmit control logic 128 and a packet transmit buffer 130. In addition in order to fulfil the monitor function all nodes are equipped with a left slot pulse generator 136 and a right slot pulse generator 138, and these functions are activated by the monitor state logic 139 so that node 100 is activated to become the left hand monitor and node 104 is activated to become the right hand monitor node. The operation of these elements will be later described.

Considering now the operation of the logic within the node as shown in Fig. 8 - the monitor state logic 139 in the left monitor node 100 sets the left monitor state to active and the monitor state logic 139 in the right monitor node 104 sets the right monitor state to active -and the monitor state logic 139 in the other nodes 102 sets the monitor state to inactive - so that only node 100 can transmit left slot pulses and only node 104 can transmit right slot pulses. It will be appreciated that the means of setting initial states/values into the logic - for instance into the timers and the monitor state logic is ommitted from Fig. 8 for the sake of clarity. The transmit state control logic 120, contained within all nodes 102, 100 and 104, maintains the node in the inactive state for transmission of data packets unless the node has a data packet ready to transmit when it receives either a left or a right slot pulse signal.

Referring now to Fig. 9 all nodes 102 therefore remain silent until the left slot pulse 140 is transmitted from the monitor node 100. This signal 140 propagates uni-directionally along the bus and is received by each node 102 after its release at a time corresponding to the product of the physical distance of the particular node from the left monitor node 100 and the propagation rate of the medium - as shown in Fig. 9 - e.g. Node 2 receives the slot pulse at time instant 141.

When the slot pulse detector 122, in each node detects the left slot pulse 140, its transmit state control logic 120 either maintains the node in the inactive state if it does not have a data packet ready to transmit at that time or the transmit state control logic 120 sets the node's transmit state to left active if it has a data packet ready to transmit when it receives the left slot pulse 140.

Also on detection of a left slot pulse 140 all nodes start their left station delay timers 124 from zero.

All left active nodes have a chance to transmit onto the bus 10 if it is silent when their SPL delay timers 124 expire but only the node, in the active transmit state, nearest to the left monitor 100 will find the bus silent when its SPL delay timer 124 expires and therefore only that node will be able to transmit its data packet as is explained below.

Each node is equipped with a left hand station, or SPL delay timer 124, which contains a unique predetermined delay time which is predetermined at network set up or configuration time rather than at normal run time. The values of the SPL delay timers are chosen such that the time delay in a node closer to the left monitor node 100 always has a lower value of time delay, i.e. the value of the SPL delay timer in node n is always less than the delay in node n+1, where the nodes are numbered 1 to N in order of their physical location on the bus starting with node 1 as the left monitor node 100. Conveniently the SPL delay timers can be set to a value

where n is the number of the node according to its physical position from node 100, and t_d is a small delay, which is greater than the maximum timing tolerances for detection of slot pulses and data packets (for example 10 data bits or 1 microsecond per node for a 10 Megabits/sec. data rate or 10 nanoseconds for a 1 Gigabits/sec. data rate) and thus the SPL delay timer in the most downstream node (ie the one furthest from the left hand polling node) has the value N.t_d.

Referring again to Fig. 9 it can be seen that the time gap between the slot pulse 140 and a data packet eg data packet 146 from Node 2 remains constant downstream of the node position and thus all nodes downstream of node 2 which have larger values in their station timers will find that the bus is busy when their SPL delay timers expire as explained in detail below for the illustrative case shown in Fig. 9 where following the left slot pulse both Nodes 2 and 3 have packets ready to transmit but Nodes 1 and 4 do not.

The transmit state control logic 120 in Node 1 sets the transmision state of Node 1 to the inactive state when the slot pulse detector 122 in the node detects the left slot pulse 140. The transmit state control logic 120 in nodes 2 and 3 sets the transmission state of these nodes to left active when the slot pulse detectors 122 in these nodes detect the left slot pulse 140. Fig. 9 also shows the time instant 142 at which Node 1 would have started to transmit its data packet had it been in the left active state.

Node 2 is in the left active transmit state and its bus silence detector 126, which continuously monitors the state of the bus to determine whether it is silent or busy with a data packet or a slot pulse, detects that the bus is silent when its SPL delay timer 124 expires at a time 2.^ after the end of the slot pulse - time instant 144 in Fig. 9. These two logical conditions are fed to the packet transmit control logic 128 which causes this logic to initiate transmission of a data packet 146 onto the bus from the packet transmit buffer 130 and the host computer's memory. Once transmission of the packet has started the transmit state reset signal from the packet transmit control logic 128 resets the transmit state control logic 120 to the inactive transmission state. Node 3 is also in the left active transmit state but its bus silence detector 126 detects that the bus is busy when its SPL delay timer 124 expires at time 3.^ after the end of the slot pulse - time instant 148 in Fig.9, thus not satisfying the logical conditions required by the packet transmit control logic 128 to initiate the transmission of a data packet onto the bus.

Since node 3 has not yet transmitted its packet its transmit state remains left active and when its data packet detector 132 detects the end of the data packet (transmitted from Node 2), Node 3 restarts its SPL delay timer 124 from zero when it detects bus silence at the end of the data packet - ie at time instant 150. The bus silence detector 126 in Node 3 now detects that the bus is silent when the SPL delay timer 124 expires at time 3.t_d after the end of the slot pulse - time instant 152 in Fig.9, and these two logical conditions cause the packet transmit control logic 128 to initiate transmission of a data packet onto the bus from the packet data buffer 130 and the host computer's memory. The transmit state reset signal from the packet transmit control logic 128 then resets the transmit state control logic 120 in Node 3 to the inactive transmission state.

From the above description it can be seen that if any nodes downstream of Node 3 were in the left active state then they would be able to transmit a data packet each onto the bus, with the first active downstream node, node n say, starting to transmit its data packet at a time n.t_d after it detects the end of the data packet from Node 3, and nodes further downstream starting in order of their physical location on the bus.

By using the above protocol, all nodes which have packets to transmit when they detect the slot pulse 140, get a chance to transmit their data packets, subsequent to receipt of a single left slot pulse, in order of their physical location on the bus and without the packets colliding with each other.

Since by now all nodes are in the inactive transmit state, either since they have transmissitted their data packet or because they no data packets waiting when they received the last left slot pulse. Therefore another slot pulse has to be transmitted to allow nodes, with further packets waiting be transmitted, to enter the transmit active state. It will be appreciated that in the arrangement shown in Fig. 4, there is a period of dead time, when no packets can be transmitted, as the trigger signal propagates back to the single monitor located at the left hand end of the bus. To enhance performance the system described here incorporates an additional right monitor node 104 which releases a right slot pulse, either immediately if the right monitor is active (a case not illustrated in Fig. 9), or if the right monitor is inactive after a sufficient period of silence has persisted on the bus for the right monitor node 104 to be sure there are no data packets still to be transmitted subsequent to left slot pulse 140 which could collide with the right slot pulse.

In the case when nodes 1 to N have been assigned left station delay times n.t_d the largest left station time delay at the most left downstream node i.e. the right monitor node 104, node N, is N.t_d and the longest left station delay time (stored in the SPL delay timer 124) before a packet to be released is therefore N.t_d after the end of the last packet - time instant 154 in Fig. 9.

Referring again to Fig.9 it can be seen that the right monitor node 104 releases its right slot pulse 160 at that time. It will be appreciated that the links between the monitor state logic 139, the SPL delay timer 124 and the slot pulse right generator 138 have been ommited from Fig. 8 for the sake of clarity.

All nodes 102 are in the inactive transmit state and they remain silent until the right slot pulse 160 is transmitted from the monitor node 104. This signal 160 propagates uni-directionally along the bus and is received by each node 102 after its release at a time corresponding to the product of the physical distance of the particular node from the right monitor node 104 and the propagation rate of the medium - as shown in Fig. 9 - e.g. Node 3 receives the slot pulse at time instant 165.

When the slot pulse detector 122 in each node detects the right slot pulse 160, the transmit state control logic 120 either maintains the node in the inactive state if it does not have a data packet ready to transmit at that time or the transmit state control logic 120 sets the node's transmit state to right active if it has a data packet ready to transmit when it receives the right slot pulse 160.

Also on detection of a right slot pulse 160 all nodes, whose transmit state is active, start their SPR delay timers 134. All right active nodes have a chance to transmit onto the bus 10 if it is silent when their SPR delay timers 134 expire but only the node, in the active transmit state, nearest to the right monitor 104 will find the bus silent when its SPR delay timer 134 expires and therefore only that node will be able to transmit its data packet as is explained below.

Each node is equipped with a right hand station or SPR delay timer 134 which contains a unique predetermined delay time which is predetermined at network set up or configuration time rather than at normal run time. The values of the SPR delay timers are chosen such that the time delay in a node closer to the right monitor node 104 always has a lower value of time delay, ie the value of the SPR delay timer in node n+1 is always less than the delay in node n, where the nodes are numbered 1 to N in order of their physical location on the bus starting with node 1 as the left monitor node 100.

Conveniently the SPR delay timers can be set to a value (N+l-n).t_d and thus the SPR delay timer in the most right downstream node (ie the one furthest from the right hand polling node) has the value N.t_d.

Referring again to Fig. 9 it can be seen that the time gap between the slot pulse 160 and a data packet e.g. data packet 166 from Node 2 remains constant downstream of the node position (i.e. further from node 104) and thus all nodes downstream of node 2 which have larger values in their station timers, will find that the bus is busy when their SPR delay timers expire as explained in detail below for the illustrative case shown in Fig. 9 where the only node wishing to transmit following the right slot pulse is Node 2.

The transmit state control logic 120 in Node 4 sets the transmit state of Node 4, 3 and 1 to the inactive state when the slot pulse detector 122 in each of these nodes detects the right slot pulse 160. The transmission state control logic 120 in node 2 sets the transmision state of this node to right active when the slot pulse detector 122 in this node detects the right slot pulse 160. Fig. 9 also shows the time instants 161, and 162 at which Node 4 and 3 would have started to transmit data packets had they been in the right active state. Node 2 is in the right active transmit state and its bus silence detector 126, which continuously monitors the state of the bus to determine whether it is silent or busy with a data packet or a slot pulse, detects that the bus is silent when its SPR delay timer 134 expires at a time 3.1^ after the end of the slot pulse - time instant 164 in Fig. 9. These two logical conditions are fed to the packet transmit control logic 128 which causes this logic to initiate transmission of a data packet 166 onto the bus from the packet transmit buffer 130 and the host computer's memory. Once transmision of the packet has started the transmit state reset signal from the packet transmit control logic 128 resets the transmit state control logic 120 to the inactive transmission state.

From the above desccription and making a comparison with the operation described for left slot pulses above it can be seen that if any other downstream nodes which had not yet transmitted a packet would remain right active and when their data packet detectors 132 detected the end of the data packet (transmitted from Node 2), these Nodes would restart their SPR delay timer 134 from zero when they detected bus silence at the end of the data packet 166 and would be able to transmit a data packet each onto the bus, with the first active downstream node, node n say, starting to transmit its data packet at a time (N+l-n).t_d after it detects the end of the data packet from Node 2, and nodes further downstream (ie further from node 104) starting in order of their physical location on the bus.

By using the above protocol all nodes which have packets to transmit when they detect the slot pulse 160, get a chance to transmit their data packets, subsequent to receipt of a single right slot pulse, in order of their physical location on the bus reckoned from the right hand monitor node 104 and without the packets colliding with each other.

Since by now all nodes are in the inactive transmit state, either since they have transmissitted their data packet or because they no data packets waiting when they received the last right slot pulse. Therefore another left slot pulse has to be transmitted to allow nodes, with further packets waiting be transmitted, to enter the transmit active state. [It will be appreciated that the links between the montor state logic 139, the SPR delay timer 134 and the slot pulse left generator 136 have been ommitted from Fig. 8 for the sake of clarity.] A further left slot pulse is then released either immediately from left monitor node 100, if the left monitor node was the last to transmit a packet subsequent to release of right slot pulse 156 (not the case illustrated in Fig. 9). In the alternative case where the left monitor is inactive following release of the right slot pulse, after a sufficient period of silence has persisted on the bus for the left monitor node 100 to be sure there are no data packets still to be transmitted subsequent to left slot pulse 160 which could collide with the right slot pulse.

In the case when nodes 1 to N have been assigned right hand station delay times (N+l-n).t_d the largest station time delay at the most right downstream node ie the left monitor node 100, node 1, is N.td and the longest station delay time before a packet to be released is therefore N.t after the end of the last packet - time instant 168 in Fig. 9. Refering to Fig.9 the left monitor releases its left slot pulse 170 at that time and the cycle of events is repeated. Fig. 9 shows the case where there are no waiting packets subsequent to release of left slot pulse 170 and the next right slot pulse 174 is released at time instant 172.

It will be appreciated from the foregoing detailed descriptions that the timed packet transmission method and system relies for its correct operation on each node, with a packet to transmit, determining that the upstream state of the bus structure will allow it to transmit a data packet without collision - a fact which is determined by each node at the expiry of its station's time delay. The foregoing detailed descriptions have described this for the case where the interconnecting bus structure is a bidirectional linear bus. It will be appreciated that when a unidirectional bus structure is employed, then the upstream state of the bus can be determined by equipping each of the connected nodes with an upstream read tap on the write section of the bus capable of detecting the upstream activity on the bus - as described below. This upstream input is of course in addition to the normal transmit output on the transmit section of the bus and the read input on the read section.

A very well known example of a unidirectional bus structure which uses an upstream read tap and a transmit output on the same unidirectional bus is the 155.52Mbps. single mode optical fibre bus used in the ANSI SONET (CCITT SDH) standatrd which has been adopted as one of the physical layers for the IEEE 802.6 MAN standard. [Since IEEE 802.6 uses two opposing unidirectional buses these input and output connections are duplicated on the second opposing bus.] An example of a system operating at data rates of greater than 1 Gigabits /sec. and using a single folded unidirectional bus with upstream read taps and a transmit output on the write section and a read input on the read section is found in Hewlett Packard's HANGMAN prototype network. From the above it will be understood that methods of receiving data from and transmitting data onto a unidirectional folded bus at data rates exceeding 1 Gigabits/sec. are well known in the art. The following detailed descriptions are therefore restricted to description of the timed packet transmission medium access method at the medium access layer rather than operation of the electronics and optical devices required to implement the physical layer of a unidirectional bus structure.

Referring now to Fig. 10 of the drawings which illustrates a data communications network comprised of a monitor node (node 1) and three other nodes numbered 2 to 4 connected to a common data communications path implemented using a folded unidirectional linear bus according to a fourth embodiement of the invention. The nodes 202 and the monitor node 200, are equipped with upstream read taps 203 and transmit outputs 204 to the write section of the bus 206, and read inputs 205 from the read section 207. It will be appreciated that a plurality of nodes are connected to the bus but only four nodes 1 to 4 are shown in the interest of clarity.

As described above for the case where the interconnecting bus structure is bi-directional linear bus the single monitor node 200 performs the monitor function to control the access of all nodes to the bus according to the invention.

It will be appreciated that although only the monitor function will be described, node 200 is also capable of transmitting and receiving data packets to and from the bus to support normal data communications with the other nodes 202. It will be further appreciated that other nodes also contain the polling function such that on failure of node 200 the next adjacent node (i.e. Node 2) can take over the monitor function as is well known in the art.

Reference is now made to Fig. 11 which depicts the functional blocks required to implement the timed packet transmission method of the emodiement of the invention which uses a single unidirectional folded bus structure. However, for the sake of clarity, with the exception of the data packet transmit buffer 230, Fig. 11 omits all the circuitry necessary to transmit and receive data packets and to transfer them to (and from) the memory of the host as this circuitry is well known in the art - as described above.

transmit state control logic 220, a slot pulse detector 222, a bus silence detector 226, a station delay timer 224, a data packet detector 232, packet transmit control logic 228, a packet transmit buffer 230. In addition in order to fulfill the monitor function, the nodes are equipped with a bus silence detector 239, a next slot pulse timer 234, a slot pulse generator 236, and monitor state logic 238.

Referring now to Fig. 2 it will be appreciated that the functional blocks shown in Fig. 11 correspond exactly to those shown in Fig.2 except for the following differences:

a) the transceiver 16 is replaced by: i) an upstream receive tap connected to the bus through signal receiving circuits 210, ii) a transmit data output 211 to the write section of the bus 206, and iii) read input signal receiving circuits 212 connected to the read section 207 of the bus;

b) the upstream tap input feeds the slot pulse detector 222, the bus silence detector 226 and the data packet detector 232;

c) the read input 212 feeds a second bus silence detector 239 which provides signals to the next slot pulse timer 234;

d) there is no connection between the bus silence detector 226 and the next slot pulse timer 234.

Referring now to Fig. 12 we consider the case where nodes 2 and 3 have a data packet to send on receipt of the slot pulse 240. Subsequent to release of a slot pulse 240, nodes determine the upstream state of the bus using their slot pulse detector 222, the bus silence detector 226 and their data packet 232 connected to the upstream tap through signal receiving circuits 210 in exactly the same way as the corresponding components of Nodes 14 shown in Fig. 2. From the foregoing description it will therefore be apparent that there is exact correspondence between the operation of the system described in Figs. 1, 2 and 3 (subsequent to release of a slot pulse) and the present embodiement operating over a unidirectional bus and therefore a repitition of the detailed description will be omitted in the interests of brevity.

Referring again to Fig. 12 it can be seen that Nodes 2 and 3 transmit data packets 246 and 251 respectively following transmission of the slot pulse 240.

It will be appreciated that data packets 246 and packet 251 also propagate down the read section of the unidirectional bus. In particular packet 251 reaches the downstream end of the write section of the bus 206 at time instant 260 and starts to propagate down the read section at the same time instant. The read section of the bus then becomes silent at the monitor node's read input at time instant 270. This event is detected by the bus silence detector 239 in the monitor node which then waits for a period of silence greater than that of the station delay timer in the most downstream node before releasing the next slot pulse 280, under the timing control of the bus silence detector 239 and the next slot pulse timer 234.

It will be appreciated that when no nodes transmit a data packet following a slot pulse, the monitor node waits for a same period of silence greater than that of the station delay timer in most downstream node before releasing the next slot pulse.

With the release of the next slot pulse 280 any packets waiting can be transmitted according to the deterministic timed packet transmission protocol of this invention - whereupon the sequence of events described above repeats.

The above describes the operation of the invention with a bi-directional linear bus and with a single folded unidirectional bus. In all arrangements it will be understood that compared to existing methods of bus access such as token passing the method provides rapid access to a bus for a waiting packet and thus minimises access time delays. This feature is of particular importance for short packet transmit times which occur with high data rates and with short packet lengths. Various modifications may be made to the embodiments hereinbefore described without departing from the scope of the invention. For example, the foregoing descriptions conveniently depict the slot pulse, as a single short envelope and the monitor trigger pulse as a shorter envelope. It will be appreciated that this is merely a diagrammatic representation of these signals. Thus any signal pattern, suitable for transmission over a bi-directional bus and which, when received, can provide a unique time reference is included within the scope of the invention. For instance it will be appreciated that a sequence of bits (possibly preceded by a preamble) suitably encoded for transmission over a bus (e.g. by Manchester or other forms of encoding - as is well known in the art) can be used.

In the case of an Ethernet compatible bus this sequence of bits may conform or not to the standard Ethernet bus signal levels and timings and may conveniently be decoded into a sequence of bits with separate clock and data signals. Thus one sequence of bits, which can be uniquely interpreted by the receiving nodes, may be used as the only slot pulse or as the left slot pulse and another different sequence of bits, which is separately identifiable, may be used as the right slot pulse or the trigger pulse signal.

It will be further appreciated that at the time of initial network configuration (set-up) a number of parameters in the nodes have to be set up. These parameters include the status of the node - ie monitor node, monitor trigger node, left hand monitor node, right hand monitor node or normal data communications node. Further the value of the station delay, next slot and other timers in the nodes have to be set up - some according to the order of the physical location of the node on the bus. These parameters can be programmed into the nodes from the host computer or manual dip switches could be used.

Advantages of the invention are that there is provided a method of providing collision free deterministic timed packet transmission access to a bus for a plurality of connected nodes which is relatively inexpensive and straightforward to implement. The method provides orderly deterministic access for data packets without the need to maintain a logical ring (map) in all nodes.

Nodes can thus leave and rejoin the network without the need for a lengthy reconfiguration process - also nodes which are not associated with the monitor or trigger functtion can fail or be disconnected without upsetting the normal operation of the network - in contrast to other deterministic access methods such as token passing. The method offers substantially reduced access time per node when compared with existing methods, when the interconnecting shared medium is a linear bus. When this interconnection topology is used the timed packet transmission access method of this invention offers considerable advantages in performance over the widely used shared bus access methods such as CSMA/CD, central polling and token passing.

The timed packet transmission method described here can be industrially exploited as a medium access method for use in fields such as Local Area Networks or LANs, which are used to interconnect a number of computers. The method is suitable for use as a medium access method for LANs operating at a wide variety of data rates from e.g. 10 Megabits /sec. to above 1 Gigabit/sec.

Claims

1. A method of providing deterministic access to a bus structure having two or more nodes connected thereto, in a data communications network, each node being capable of transmitting and receiving data packets to and from said bus structure and each node having a physical node address defined as the address for data packets, said method employing a polling or monitor node located at one end of the bus, capable of transmitting a series of timing reference signals or slot pulses, which are distinct and separate from the data packets, said slot pulses being used to provide a common time reference to all nodes such that, following each slot pulse by using a unique predetermined time delay in each node all active nodes may transmit data packets in a collision free manner, within the one slot pulse cycle, said method providing for round robin access for all nodes and said method further comprising the steps of:

b) arranging for each of said active nodes to transmit one data packet each at the expiry of a unique predetermined time, defined as the station time delay, said station time delay being predetermined at network configuration time, providing that each of said nodes detects silence on the bus at the station time delay expiry time according to the following colision avoidance signal conditions: i) arranging that once transmision of said data packet has started each node returns its said transmission state to inactive so that transmission of only one data packet is permitted at this time ii) arranging that said station time delay in each of said nodes starts immediately after detection of a slot pulse iii) arranging that the value of said station time delay in each adjacent downstream node is greater than the said station time delay in its immediate upstream neighbour, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the upstream neighbouring node transmits a data packet then the immediate downstream neighbouring node and all nodes further downstream will detect that the bus is busy at the expiry of their station time delays, where a node closer to the said monitor node is defined as an upstream node and a node further away from the monitor node is defined as a downstream node iv) arranging that said station time delays in each of said nodes as well as starting immediately after detection of a slot pulse are also permitted to start immediately after the end of any data packet transmitted from another said active node is detected, such that all said active nodes transmit one data packet each subsequent to receipt of a single slot pulse;

2. A method as claimed in Claim 1 wherein, the method includes the step of arranging that said monitor node generates the next slot pulse after it detects that a sufficient period of silence has elapsed to guarantee that there will not be a collision with any data packet about to be transmitted subsequent to the last slot pulse, said period of silence being defined as the next slot pulse wait time, and said next slot pulse wait time occuring either in the case where one or more nodes has transmited a data packet subsequent to the last slot pulse or in in the case when no data packets have been tranmitted subsequent to the last slot pulse, the value of said next slot pulse wait time being greater than the sum of twice the maximum end to end propagation delay time of the bus, plus the station time delay of the most downstream node on the bus, plus a safety time sufficient to cater for all tolerances in these times.

3. A method as claimed in Claim 1 wherein, when said shared data communications medium is a single bidirectional linear bus, the method includes the step of arranging that the monitor node transmits the next slot pulse after it receives a uniquely identifiable signal pattern -called the monitor trigger signal from the most downstream node, the most downstream node transmitting said monitor trigger signal either shortly after: i) the expiry of the said station time delay in the most downstream node, if said node has been in the inactive state following on detection of the last slot pulse or ii) the end of the data packet being transmitted from the most downstream node.

4. A method as claimed in Claim 1 and Claims 2 or 3 wherein the said nodes are assigned integer numbers 1 to N in order of their physical location on the said linear bus, starting with number 1 at the monitor node, and the method includes the step of assigning delay times to each node according to the formula n.t where n is the number of the node and t_d is a small fixed time delay designed to cope with the timing tolerances in electronic detection of signals on the bus and variations in relative propagation times between a slot pulse and a following data packet.

5. A method as claimed in any of the Claims 1 to 4 wherein the method includes the step of equipping a number of nodes with monitor facilities when upon failure of the monitor node the next downstream node automatically assumes the monitor function.

6. A method as claimed in Claim 1 wherein the method includes the additional steps of providing a second monitor at the other - ie right hand - end of the bus such that separately detectable slot pulse signals are released in turn from the left hand and right hand monitors and said nodes become either left active or right active if they have a data packet to transmit when they receive a slot pulse signal from the left or right monitor respectively said data packets being transmitted in a collision free manner using either left hand station delay times or right hand station delay times respectively, said method further comprising the steps of:

c) arranging that after transmission of an SPL each of said left active nodes is permitted to transmit one data packet at the expiry of a unique predetermined time, defined as the left hand station time delay, providing that each of said nodes detects silence on the bus structure at the station time delay expiry time according to the following collision avoidance signal conditions: i) arranging that once transmision of said data packet has started each node returns its said left active transmission state to inactive so that transmission of only one data packet is permitted at this time, ii) arranging for said left hand station time delay in each of said nodes to start immediately after detection of an SPL, iii) arranging that the value of said left hand station time delay in each adjacent node which is further from the left hand monitor is greater than the said station time delay in its immediate neighbour which is closer to the left hand node, the increase in the value of said left hand station time delay being sufficient to ensure that if a neighbouring node closer to the left hand monitor transmits a data packet then its immediate neighbouring node and all other nodes further away from the left hand monitor will detect that the bus structure is busy at the expiry of their station time delays, iv) arranging that said left hand station time delays in each of said left active nodes as well as starting immediately after detection of an SPL may also start immediately after the end of any data packet transmitted from another node is detected, such that all left active nodes transmit one data packet each subsequent to detection of a single SPL;

d) arranging that if said right hand monitor is in the left active state when its left hand station delay time expires and the bus structure is silent it transmits one data packet and then shortly after the end of the data packet transmits an SPR, alternatively if the right hand monitor is in the inactive state and it detects that the bus structure is silent when its left hand station delay time expires it transmits an SPR shortly after that time;

f) arranging that if said left hand monitor is in the right active state when its right hand station delay time expires and the bus structure is silent it transmits one data packet and then shortly after the end of the data packet transmits an SPL, alternatively if the left hand monitor is in the inactive state and it detects that the bus structure is silent when its right hand station delay time expires it transmits an SPL at that time.

7. A method as claimed in Claim 6, wherein, said nodes are assigned integer numbers 1 to N in order of their physical location on the bus structure, starting with number 1 at the most left hand node, the method includes the step of assigning to each node a said left hand station delay time given by the formula n.t_d, where n is the number of the node and t_d is a small fixed time delay designed to cope with the timing tolerances in electronic detection of signals on the bus and variations in relative propagation times between a slot pulse and following data packets and further assigning a right hand station delay time assigned to each node given by the formula (N+l-n).t_d .

8. A method as claimed in Claim 6 wherein the method includes the step of equipping all of the nodes with left and right monitor facilities so that upon failure of the either monitor node the adjacent downstream node (to the failed monitor) automatically assumes the monitor function.

9. A method as claimed in any one of the Claims 1 to 8 wherein said interconnecting bus structure is a single bidirectional linear bus.

10. A method as claimed in Claims 1, 4 and 5, wherein the said interconnecting bus structure is a single unidirectional folded bus and the nodes are equipped with upstream taps.

11. A method as claimed in Claims 1 and 10 wherein the method includes the step of arranging that the next slot pulse is generated by the monitor node shortly after the monitor node's read input tap (located on the read section of the bus), detects that a period of silence lasting longer than the maximum station time delay has elapsed, said period of silence persisting after the end of the last data packet or after the previous slot pulse.

12. A system for providing deterministic timed packet transmission access to a bus structure having two or more nodes connected thereto, in a data communications network, each node being capable of transmitting and receiving data packets to and from said bus structure and each node having a physical node address defined as the address for data packets, said system including a polling or monitor node located at one end of the bus capable of transmitting timing reference signals or slot pulses, which are distinct and separate from the data packets, said slot pulses being used to provide a common time reference to all nodes such that, following a slot pulse by using a unique predetermined time delay in each node all nodes may transmit data packets in a collision free manner, said system being equipped with control logic in each node to implement the timed packet transmission of the present invention comprising:

f) means for controlling the transmission of one data packet from the node, said means being defined as the packet transmit control logic, and said packet transmit control logic initiating the transmission of a said data packet at the expiry of said station timer delay at each node according to the following collision avoidance signal conditions: i) the said node is in the active transmit state ii) the silence detector in said node detects that the bus is silent at the expiry of said station timer delay iii) the packet transmit control logic resets the transmit state control logic to the inactive state once transmision of said data packet has started so that transmission of only one data packet is permitted at this time iii) unique predetermined values have been assigned to the the station delay timers in each of the nodes, such that the value of said station time delay in each adjacent downstream node is greater than the said station time delay in its immediate upstream neighbour, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the upstream neighbouring node transmits a data packet then the immediate downstream neighbouring node and all nodes further downstream will detect that the bus is busy at the expiry of their station time delays, where "downstream" indicates that the downstream node is further from the monitor node and "upstream" indicates that the upstream node is nearer the monitor node; g) bus structure means for supporting all data communications for said data packets and said slot pulses such that said data packets follow said slot pulses in the same shared data communications channel.

13. A system as claimed in Claim 12 wherein the monitor node contains timing delay means, defined as the next slot pulse timer, said next slot pulse timer ensuring that said monitor node waits for a sufficient period of silence to elapse to guarantee that there will not be a collision with any data packet about to be transmitted subsequent to the last slot pulse, before generating said next slot pulse, said period of silence being defined as the next slot pulse wait time, and said next slot pulse wait time occuring both in the case where one or more nodes has transmitted a data packet subsequent to the last slot pulse and in the case when no data packets have been transmitted subsequent to the last slot pulse, the value of said next slot pulse wait time being greater than the sum of twice the maximum end to end propagation delay time of the bus, plus the station time delay of the most downstream node on the bus, plus a safety time sufficient to cater for all tolerances in these times.

14. A system as claimed in Claims 12 and 13 wherein all nodes include a next slot pulse timer and means for generating slot pulses, defined as the slot pulse generator, and these functions are activated by the monitor state logic, such that on failure of the monitor node the monitor state logic can activate these functions in the next downstream node so that it assumes the monitor function.

15. A system as claimed in Claim 12 wherein, when the said shared data communications medium is a bidirectional linear bus, there is additionally provided a means of transmitting a uniquely identifiable signal pattern -called the trigger signal, from the most downstream node, said means being defined as a trigger pulse generator and means of detecting the trigger signal in the monitor node, said means being defined as the trigger pulse detector, and arranging for the trigger pulse detector to initiate transmission of the next slot pulse from the monitor node when the trigger pulse detector detects the trigger pulse signal from the most downstream node, this additional capability having the advantage of shortening the period of time that the monitor has to wait before it can safely release the next slot pulse, the time when said trigger pulse is transmitted being either shortly after: i) the expiry of the said station delay timer in the most downstream node, if said node has been in the inactive state following on detection of the last slot pulse or, ii) the end of the data packet being transmitted from the most downstream node.

16. A system as claimed in Claims 12 and 15 wherein all nodes additionally include a trigger pulse generator and a trigger pulse detector, and these functions are activated by the monitor/ trigger pulse state logic, such that on failure of the most downstream node the monitor/ trigger pulse state logic can activate the trigger pulse generator function in the next upstream node so that it assumes the trigger pulse function.

17. A system as claimed in Claim 12 wherein deterministic access to a bus structure having two or more nodes connected thereto, in a data communications network, each node being capable of transmitting and receiving data packets to and from said bus structure and each node having a physical node address defined as the address for data packets, is provided, said system additionally including a second monitor or polling node at the other - or right hand - end of the bus such that separately detectable slot pulse signals are released in turn from the left hand and right hand monitors and said nodes become either left active or right active if they have a data packet to transmit when they receive a slot pulse signal from the left or right monitor respectively said data packets being transmitted in a collision free manner using either left hand station delay timers or right hand station delay timers respectively, said system further comprising:

a) means for generating a uniquely identifiable signal defined as a left hand slot pulse - or SPL - from the monitor node which is located at the left hand end of the bus, said means being defined as slot pulse left generator, and means for generating another uniquely identifiable signal defined as a right hand slot pulse - or SPR - from the monitor node which is located at the right hand end of the bus, said means being defined as slot pulse right generator; b) means for detecting slot pulse signals defined as a slot pulse detector, said slot pulse detector producing an SPL output signal on detection of an SPL and an SPR output signal on detection of an SPR;

d) means for detecting the presence and the end of a data packet on the bus, said packet detecting means being defined as the data packet detector;

0 means for detecting whether the bus is busy or silent at any particular instant of time, said silence detecting means being defined as the bus silence detector;

g) means for controlling the transmission of one data packet from the node, said means being defined as the packet transmit control logic, and said packet transmit control logic initiating the transmission of a said data packet at the expiry of said SPL delay timer delay at each node according to the following collision avoidance signal conditions: i) the said node is in the left active transmit state, ii) the silence detector in said node detects that the bus is silent at the expiry of said SPL delay timer, iii) once transmision of said data packet has started the packet transmit control logic resets the transmit state control logic to the inactive state so that transmission of only one data packet is permitted at this time, iv) unique predetermined values have been assigned to the the SPL delay timers in each of the nodes, such that the value of said SPL delay timer in each adjacent node more distant from the left hand monitor is greater than the said station time delay in its immediate neighbour closer to the left hand monitor, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the neighbouring node closer to the left hand monitor transmits a data packet then the immediate neighbouring more distant node and all nodes further from the left hand monitor will detect that the bus is busy at the expiry of their SPL delay timers;

h) slot pulse generating means, included within the right hand monitor, for generating the next right slot pulse or SPR from said right hand monitor under the following two collision avoidance conditions: i) when its left hand station delay time expires provided the node has been in the inactive state and the bus is silent at that time, ii) shortly after the end of its data packet is the right hand monitor has been in the left active state;

i) means for generating a unique predetermined time delay within each node, said means being defined as the SPR delay timer, and the value of said SPR delay timer being predetermined - ie set at network configuration time, said SPR delay timer being started from zero either immediately after detection of a right slot pulse or in the case of a right active station, immediately after detection of an end of packet signal from the data packet detector;

j) means for controlling the transmission of one data packet from the node, said means being defined as the packet transmit control logic, and said packet transmit control logic initiating the transmission of a said data packet at the expiry of said SPR delay timer delay at each node according to the following collision avoidance signal conditions: i) the said node is in the right active transmit state, ii) the silence detector in said node detects that the bus is silent at the expiry of said SPR delay timer, iii) once transmision of said data packet has started, the packet transmit control logic resets the transmit state control logic to the inactive state so that transmission of only one data packet is permitted at this time, iv) unique predetermined values are assigned to the the SPR delay timers in each of the nodes, such that the value of said SPR delay timer in each adjacent node more distant from the right hand monitor is greater than the said station time delay in its immediate neighbour closer to the right hand monitor, the increase in the value of the station time delay between adjacent nodes being sufficient to ensure that if the neighbouring node closer to the right hand monitor transmits a data packet then the im¬ mediate neighbouring more distant node and all nodes further from the right hand monitor will detect that the bus is busy at the expiry of their SPR delay timers;

k) slot pulse generating means, included within the left hand monitor, for generating the next left slot pulse or SPL from said left hand monitor under the following two collision avoidance conditions: i) when its right hand station delay time expires provided the node has been in the inactive state and the bus is silent at that time, ii) shortly after the end of its data packet if the left hand monitor has been in the right active state;

1) bus structure means for supporting all data communications for said data packets and said slot pulses such that said data packets follow said slot pulses in the same shared data communications channel.

18. A system as claimed in Claim 17 wherein all nodes include both a slot pulse left generator and a slot pulse right generator, either of which can be activated by the monitor state control logic at the expiry of the node's station delay timer, so that upon failure of a left monitor or a right monitor an adjacent replacement node can take over the appropriate left or right hand monitor functions.

19. A system as claimed in Claim 12 wherein, said shared data communica¬ tions means is provided by a single bidirectional linear bus.

20. A system as claimed in Claim 12 wherein, said shared data communica¬ tions means is provided by a single folded unidirectional bus.