WO1996017389A1 - Temperature compensation circuit for ic chip - Google Patents
Temperature compensation circuit for ic chip Download PDFInfo
- Publication number
- WO1996017389A1 WO1996017389A1 PCT/US1994/013402 US9413402W WO9617389A1 WO 1996017389 A1 WO1996017389 A1 WO 1996017389A1 US 9413402 W US9413402 W US 9413402W WO 9617389 A1 WO9617389 A1 WO 9617389A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- signal
- clock
- chip
- heater
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
Definitions
- the present invention relates to a temperature compensation circuit to be used in a semiconductor IC, and more particularly, a temperature compensating circuit of a variable delay circuit in a digital integrated circuit (IC) which can compensate a signal transmission delay time by temperature.
- IC digital integrated circuit
- each delay time per each channel has to be adjusted to be same delay time and such adjusted delay time should be maintained for a long period of time.
- IC circuits are employed to form each channel to decrease the size of the test apparatus, there arises a problem in that, in such IC circuits, delay times for propagation of signals vary depending on temperature changes.
- CMOS complementary metal-oxide semiconductor
- the conventional device has employed ICs having temperature compensatory function for a circuit aiming to maintain the delay times in a certain period.
- FIG. 9 shows a structure of the conventional IC having a temperature compensatory function therein.
- reference numeral 10 is a chip forming an IC.
- the chip 10 consists of a target circuit 11 to form a channel of the IC test apparatus and its delay time is to be maintained in a certain period, a temperature sensor 12 formed in a vicinity of the target circuit 11, a plurality of heater elements H dispersed in a vicinity of the target circuit 11, and a plurality of switch elements 13 for turning on/off a current applied to the heater elements H.
- detecting signals from the temperature sensor 12 are given to a heater control device 20, control output signals from the heater control device 20 are given to the switch elements 13 wherein the current applied to the heater H is turned on/off so as to consistently maintain the temperature inside the chip 10.
- the heater elements H is heated by a current (which is the same current as consumed in the target circuit 11) applied thereto. Then, an operation of the target circuit 11 begins so as to turn off the current applied to the heater elements H when a surrounding temperature of the target circuit 11 increases.
- the currents are applied to both of the target circuit 11 and heater elements H.
- an electric power source receives about twice as large current as the current consumed in the target circuit 11. Therefore, material used for the electric power source should endure at least twice as large current as the current consumed by the target circuit 11.
- the number of the electric power sources correspond to the number of the circuits 11. For example, in an IC test device, 100 electric power sources may be needed to match the number of the IC pins, that is 100 IC pins, resulting the increase of the manufacturing costs.
- Another conventional method contains a circuit which controls the propagation delay time in an IC by controlling a heater in the IC and the amount of heat given to the IC by the heater. Namely, the conventional method realizes a control circuit for adjusting the signal propagation delay time in substantially constant time by controlling the temperature of the IC.
- the propagation delay time of a signal which passes at least one part of the IC can be measured and compared with a standard delay time. If the measured delay time is shorter than the standard delay time, it is controlled to increase the heat generation of the heater. On the other hand, if the measured delay time is longer than the standard delay time, it is controlled to decrease the heat generation from the heater.
- Figure 10 is a block diagram showing a conventional structure disclosed in the Japanese Patent Laying-Open No. 1-114067. Since a delay measuring circuit 30 is included in an IC chip 32, a delay time in the delay measuring circuit 30 is affected by the temperature as substantially the same as other circuit in the chip IC 32.
- a heater 34 thermally connected to the IC chip adjusts the signal transmission delay time by selectively heating the IC chip 32.
- the heater 34 is preferably an integrated heating element which is mounted on the IC chip 32 with other circuit components.
- the heater 34 is usually provided relatively near the delay measuring circuit 30. Thus, it is able to minimize the time delay until the delay measuring circuit 30 is heated by the heater 34.
- a typical IC chip using a metallic lead frame has a good thermal conductivity. Thus, it is able to transmit the heat generated by the heater 34 to each circuit inside the chip.
- a plastic or ceramic package 36 having a relatively good thermal insurability surrounds the chip 32. With the package 36, the inside of the IC chip can keep a higher temperature than an ambient temperature.
- all circuits in the IC chip 32 are arranged to be in a vicinity each other and made of materials having high thermal conductivity. Therefore, all of the circuits inside the IC chip 32 are maintained in the uniform temperature. Further, factors changing the delay time in one circuit in the chip, such as the temperature and the voltage, are set to substantially equal in every circuit within the same IC chip. Therefore, it is possible to adjust the delay time of all circuits in the chip by measuring either one of the circuits, such as the delay measuring circuit 30, and adjusting the temperature in the chip based on its information.
- a control means 40 controls the heater 34 based on the measured result of the delay time received from the delay measuring circuit 30. Namely, if a measured value of the delay time is shorter than a desired time, the control means 40 controls the heater 34 to increase the heat generation. In contrast, if a measured value of the delay time is longer than the desired time, the control means 40 controls the heater 34 to decrease the heat generation. Accordingly, the delay time is precisely controlled by this procedure.
- a standard delay circuit 42 in Figure 10 generates standard delay signals corresponding to a desired transmission delay time.
- a delay comparison circuit 44 compares a standard delay signal from the standard delay circuit 42 and a measured delay signal from the delay measuring circuit 30. The output of the delay comparison circuit 44 is indicative of a time difference between the desired delay time and the delay time which is actually measured. Then, the heater 34 is controlled by a heater control signal so as to decide whether the generated heat is maintained or adjusted, based on a relationship between the standard delay signal and the measured delay signal.
- a standard delay time setting circuit 50 including a micro processor sets up a desired standard delay time. Further, the delay measuring circuit 30 measures the transmission delay time in response to a test signal received from a test signal source 52.
- the temperature inside the IC chip can be substantially maintained.
- the first aspect of the present invention is characterized in that a signal detecting circuit is provided on a signal supply path which gives logical signals to the target circuit.
- the present invention is further characterized to include the switch elements which turn on/off the current applied to the heater elements provided in the ICs every time when the signal detecting circuit detects the supplies of signals to the target circuit.
- the present invention allows to stop an application of the current to the heater elements every time when signals are supplied to the target circuit.
- the electric power source used in the present invention only needs to endure the same amount of current applied to the target circuit. This allows a remarkable reduction in electric consumption and associated costs.
- the second aspect of the temperature compensation circuit of the present invention includes two variable delay circuits, one of which performs as an actual delay circuit for a channel, for example, for a test signal in an IC test apparatus while the other performs as a heater.
- the two delay circuits are formed in close proximity one another in an IC chip so that the temperature environment is identical for the two circuits.
- a selector is provided with two clock signals having different frequencies.
- the temperature compensation circuit further includes a logical delay circuit, a mask circuit and a clock number adjusting circuit. The selector is controlled to select one of the clock signals to form, in cooperation with the logical delay circuit, a mask signal which prohibits for a certain period of time from passage of the clock signal having lower frequency.
- the output of the mask circuit is provided to the delay circuit and is used to form, for example, an actual test signal in the IC test apparatus.
- the masked output is also provided to the clock number adjusting circuit the output signal of which is provided to the other variable delay circuit (heater circuit) .
- the clock number adjusting circuit so functions that the number of clock signals to be provided to the heater circuit is controlled depending on the number of clock signals supplied to the variable delay circuit.
- the clock number adjusting circuit controls the number of clock signals supplied to the heater circuit so that the sum of the number of clock signals supplied to the variable delay circuit and the clock signals supplied to the heater circuit is equal to the original clock signal of higher frequency. Therefore, the total number of clock signals in the two delay circuits (one of them is a heater circuit) is controlled to be constant, which makes the temperature of the IC chip also constant.
- the temperature in the IC chip can be maintained to be constant, and accordingly, the signal propagation delay times for signals passing through the IC chip can also be maintained to be constant.
- Figure 1 is a circuit diagram showing a structure of temperature compensation in IC circuit of the present invention.
- Figure 2 is a timing chart showing an operation of the circuit of Figure 1.
- Figure 3 is a circuit diagram showing another embodiment of the present invention.
- Figure 4 is a circuit diagram showing an temperature compensation circuit of the second aspect of the present invention to be incorporated in an IC chip.
- Figure 5 is a timing chart showing a timing relationship in the temperature compensation circuit of Figure 4.
- Figure 6 is a timing chart showing a timing relationship in the temperature compensation circuit of Figure 4.
- Figure 7 is a timing chart showing a timing relationship in the temperature compensation circuit of Figure 4.
- Figure 8 is a timing chart showing a timing relationship in the temperature compensation circuit of Figure 4.
- Figure 9 shows a structure of the conventional IC having a temperature compensatory function therein.
- Figure 10 shows another example of conventional structure of a temperature compensation circuit of an IC chip. Detailed Description of the Invention
- Figure 1 shows one embodiment of the present invention.
- a reference numeral 10 is an IC chip.
- Reference numeral 11 is a target circuit.
- Reference H shows heater elements.
- Reference numeral 13 shows switch elements.
- a signal detecting circuit 15 is provided on a signal supplying path 14 which supplies signals to the target circuit 11.
- the signal detecting circuit is comprised of D-type flip flop 15A and a logical operator 15B which detects mismatched signals between an input and output sides of the D-type flip flop 15A.
- the logical operator 15B is an exclusive OR circuit.
- a clock signal CP Figure 2 having a constant cycle is given from a clock 16 to a clock input terminal of the D- type flip flop 15A.
- the clock 16 can be positioned either inside or outside of the chip 10.
- the drive signal S 1 is read in the flip flop 15A due to the rise of the clock CP. Then, the drive signal S x is transferred to the output side of the flip flop 15A with a delay of one cycle of the clock CP. Namely, the D-type flip flop 15A operates as a synchronizing circuit by giving the drive signal which is synchronized with the clock CP to the target circuit 11.
- Figure 2C shows a waveform of a signal S 2 which is an output of the D-type flip flop 15A.
- the logical operator 15B compares logical signals between the input and output sides of the flip flop 15A. If the logical operator 15B founds that there is a mismatch between the two logical signals, it outputs, for example, a H-logic signal.
- Figure 2D shows an output of the logical operator 15B.
- a H-logic signal S 3 is input to the switch element 13, as a result of the mismatch between the logic signals Si and S 2 .
- a P-channel FET field effect transistor
- the P-channel FET is controlled to turn off when the H-logic signal is given to a gate and turn on when the L- logic signal is given thereto.
- the signal detecting circuit 15 outputs the H-logic signal while the driving signal S x is given to the target circuit 11 and turns off the current applied to the heater elements H. During this period, the target circuit 11 generate self-heat because of the operation driven by the drive signal S 1 .
- the signal detecting circuit 15 outputs the L-logic and turns on the switch elements 13 so as to apply the current to the heater elements H.
- the heater elements H are energized to generate heat instead of the self-heat of the target circuit 11, and the temperature inside the chip 10 is maintained at the same degree.
- FIG 3 shows another embodiment of the present invention.
- a plurality of target circuits 11A and 11B are provided in series in the chip 10. Between the target circuits 11A and 11B, an additional D-type flip-flop 15A is connected in the same manner as the flip-flop 15A in the embodiment of Figure 1.
- the total amount of the current consumed in the heater elements H is arranged to be same as the total amount of the current consumed in the circuits 11A and 11B, as described in the foregoing embodiment.
- the supply of the current to the heater elements H stops in real time when the supply of the signal to the target circuits 11A and 11B begins. On the other hand, if the supply of the signal to the target circuits 11A and 11B stops, the heater elements H are turned on to generate heat .
- FIG. 4 is a circuit diagram showing an temperature compensation circuit of the second aspect of the present invention to be incorporated in an IC chip.
- a selector 60 is provided with two kinds of clock signals CLKA and CLKB.
- the output of the selector 60 is connected to an input of a logical delay circuit 62 and to a series of flip-flops 63-66.
- the clock CLKA is also supplied to a variable delay circuit 72 through an AND gate 61.
- the output of the AND gate 61 is also provided to the data input of the flip-flop 63.
- the output of the flip-flop 66 is connected to an AND gate 69 though an Exclusive NOR gate 67 which also receives an output from the flip-flop 65 in a manner shown in Figure 4.
- variable delay circuit 74 The output of the AND gate 69 is connected to a variable delay circuit 74.
- the variable delay circuits 72 and 74 respectively include a plurality of sets of buffers serially connected to achieve delay times based on the propagation time delay in the buffers B ⁇ B,,.
- Each of the variable delay circuits 72 and 74 include means for changing a signal path with buffers B ⁇ B-, and without buffers.
- the variable delay circuit 74 works as a heater for generating heat to raise the temperature of the IC chip.
- a selector signal S is provided to the input of the selector 60 to select either one of the clocks CLKA or CLKB.
- the temperature compensation circuit basically performs in two situations.
- the first situation arises when the clock CLKA is selected by the selector 60.
- the clock CLKA is masked for a certain period determined by the output of the logical delay circuit 62 which opens or closes the AND gate 61.
- the clock CLKA through the AND gate 61 is supplied to the variable delay circuit 72, and the variable delay circuit 74 through the series of flip-flops 63-66.
- the sum of clock pulses per unit time provided in the variable delay circuits 72 and 74 becomes the same as that of the clock CLKA. Therefore, the overall heat generated by the variable delay circuits 72 and 74, which are closely positioned one another in the IC chip, becomes constant and uniform. Thus, there is no fluctuation in the heat generation.due to the differences of the clock generation.
- the clock CLKB has a higher frequency than the clock CLKA.
- the variable delay circuit 72 receives the clock CLKA through the AND gate 61 since the clock CLKA is directly supplied to the AND gate 61.
- the variable delay circuit 74 receives the difference between the clock CLKA and the clock CLKB by the logic circuits formed by the flip-flops 63-66, the Exclusive NOR gate 67 and the AND gate 69.
- FIG. 5 shows a timing diagram of the signals in the first situation above.
- the select signal S ( Figure 5A) of the selector 60 is at L-level, the clock CLKA is selected as a signal a ( Figure 5D) in the first situation.
- a frequency f x is set in the clock CLKA.
- an output c of the logic delay circuit 62 is fixed to the L-level, wherein the output c is synchronized with the signal a
- an output 0UT1 remains the L-level ( Figure 50) .
- outputs e, f, g of the flip-flops 64-66 are all in the L-level ( Figures 5H, 51 and 5J) , wherein .the signal a is input therein as a clock.
- an output h of the Exclusive NOR 17 becomes H-level (figure 5K) .
- the signal a having the. frequency f x is inverted by the inverter 68 (signal i) and passes through the AND gate 69 ( Figure 5L) .
- an output signal j ( Figure 5M) of the AND gate 69 is generated at an output 0UT2 through the variable delay circuit 74 ( Figure 5P) .
- variable delay circuit 72 having the output 0UT1 and the variable delay circuit 74 having the output 0UT2 are identical one another. Further, since the physical circuit patterns of the variable delay circuits 72 and 74 are arranged in close proximity with each other in the IC chip, both variable delay circuits 72 and 74 can be considered as one set of circuit in terms of internal temperature. Namely, the variable delay circuits 72 and
- variable delay circuit 72 since the total numbers of pulses passing the variable delay circuit 72 and the variable delay circuit 74 is always the same as the number of pulses of the signal a (frequency f x in this case) , overall heat dissipation by the operation of both delay circuits 72 and 74 is constant and stable.
- the variable delay circuit 72 is used to provide an actual delay time to a test signal in a channel while the variable delay circuit 74 is used as a heat generator.
- Figure 6 is a timing diagram when a signal S is in the L-level and the signal frequency in the variable delay circuit 72 is changed by the logical delay circuit
- the flip-flop 63 changes its state (signal d shown in Figure 6G) every time when the signal k ( Figure 6N) which is the gated clock CLKA is provided thereto.
- the output signal d is delayed by the further flip- flops 64-66 by the signal a with the clock frequency f x ( Figures 6H, 61 and 6J) .
- the signal h ( Figure 6K) which is an output of the Exclusive NOR 67 and determined by the signals f and g the outputs of the flip-flops 65 and 66 respectively.
- a signal i which is the inverted the signal a having the frequency f x is output from the AND gate 19 and thus becomes the OUT2 output.
- the sum of the pulses passing through the variable delay circuits 72 and 74 is the same as the frequency f x .
- the overall heat generation by the variable delay circuits 72 and 74 is always constant, and thus, the temperature surrounding the variable delay circuits 72 and 74 is also constant.
- the signal S is in the H-level by which the clock CLKB is selected as the signal a by the selector 60.
- the clock CLKB is set to the frequency f 1 and the clock CLKA is set to the frequency £_/2 , although the frequency relationship therebetween is arbitrary.
- the output of the logical delay circuit 62 is in the H-level and does not affect the other logic operations.
- the clock CLKA having the frequency f x /2 is output at the AND gate 61 as the signal k ( Figure 7N) and then passes through the variable delay circuit 72 and to the output terminal OUT1 ( Figure 70) .
- the signal d at the output of the flip-flop 63 is - 15 - inverted ( Figure 7G) at every pulse of the signal k .
- the signal d is synchronized with the signal a and shifted at the flip-flops 64-66 so as to output intervals to the signal h ( Figure 7K) from the Exclusive NOR gate 67 to control the AND gate 67.
- the signal i ( Figure 7L) which is the inverted signal a having the frequency f x is supplied to the AND gate 69.
- the signal j ( Figure 7M) is obtained at the output of the AND gate 69 which opens when the signal h is in the H-level.
- the signal j passes through the variable delay circuit 74 which functions as a heater and outputs at the output terminal OUT2 ( Figure 7P) .
- the frequency of signal j is f x /2 as shown in Figure 7M. Therefore the sum of the pulses pass through both the variable delay circuits 72 and 74 is equal to the frequency f_ .
- Figure 8 shows a timing diagram when the signal S is in the H-level.
- the CLKA is set.to 166 MHz (period 6ns, i.e., 6 pulses in 30 nanosecond) and the CLKB is 200 MHz (period 5ns, i.e., 6 pulses in 30 nanosecond) .
- the logical delay circuit 62 is set to the H-level.
- the variable delay circuit 72 receives the signal k ( Figure 8N) having the same frequency as the clock CLKA, i.e., 166 MHz and outputs the same to the output terminal 0UT1 ( Figure 80) .
- the signal j (figure 8M) from the AND gate 69 passes through the variable delay circuit 74 OUT2 and outputs at the output terminal OUT2 ( Figure 8P) .
- the frequency of the signal j is determined by the circuit arrangement formed of the flip-flops 63-66 and the Exclusive NOR gate 67 so that the sum of the pulses in the signals k and j is equal to the frequency of the clock CLKB.
- 5 pulses are provided as the clock CLKA and 6 pulses are provided as the clock CLKB.
- 5 pulses passes through the variable delay circuit 72 in 30ns and one pulse passes through the variable delay circuit 74 in 30ns.
- variable delay circuits 72 and 74 which is equivalent to the frequency of clock CLKB.
- the total amount of heat generation by the delay circuits 72 and 74 are always constant which is determined by the number of pulses in the clock CLKB.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/817,762 US5886564A (en) | 1994-11-29 | 1994-11-29 | Temperature compensation circuit for IC chip |
PCT/US1994/013402 WO1996017389A1 (en) | 1994-11-29 | 1994-11-29 | Temperature compensation circuit for ic chip |
DE4481362T DE4481362T1 (en) | 1994-11-29 | 1994-11-29 | Temperature compensation circuit for IC module |
DE4481362A DE4481362B4 (en) | 1994-11-29 | 1994-11-29 | Temperature compensation circuit for IC component |
KR1019970703606A KR100307683B1 (en) | 1994-11-29 | 1994-11-29 | Temperature Compensation Circuit for IC Chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US1994/013402 WO1996017389A1 (en) | 1994-11-29 | 1994-11-29 | Temperature compensation circuit for ic chip |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996017389A1 true WO1996017389A1 (en) | 1996-06-06 |
Family
ID=22243303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1994/013402 WO1996017389A1 (en) | 1994-11-29 | 1994-11-29 | Temperature compensation circuit for ic chip |
Country Status (4)
Country | Link |
---|---|
US (1) | US5886564A (en) |
KR (1) | KR100307683B1 (en) |
DE (2) | DE4481362B4 (en) |
WO (1) | WO1996017389A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0831587A2 (en) * | 1996-09-20 | 1998-03-25 | Konica Corporation | Signal delay apparatus |
EP0998788A1 (en) * | 1997-07-31 | 2000-05-10 | Credence Systems Corporation | Pulse stuffing circuit for programmable delay line |
EP1914880A1 (en) * | 2006-10-16 | 2008-04-23 | SiTel Semiconductor B.V. | Integrated circuit, comprising a voltage controlled oscillator and a method for controlling a temperature of a voltage controlled oscillator |
CN102859373A (en) * | 2010-05-06 | 2013-01-02 | 德州仪器公司 | Circuit for controlling temperature and enabling testing of a semiconductor chip |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5955907A (en) * | 1995-03-03 | 1999-09-21 | Advantest Corp. | Temperature compensation circuit and method for providing a constant delay |
US6513103B1 (en) * | 1997-10-10 | 2003-01-28 | Rambus Inc. | Method and apparatus for adjusting the performance of a synchronous memory system |
US6590405B2 (en) * | 1999-04-21 | 2003-07-08 | Advantest, Corp | CMOS integrated circuit and timing signal generator using same |
US6433567B1 (en) * | 1999-04-21 | 2002-08-13 | Advantest Corp. | CMOS integrated circuit and timing signal generator using same |
KR100314933B1 (en) * | 1999-12-17 | 2001-12-24 | 최동환 | TEC control circuit |
DE19963813A1 (en) * | 1999-12-30 | 2001-07-19 | Infineon Technologies Ag | Circuit arrangement for regulating the power consumption of an integrated circuit |
US6559667B1 (en) * | 2000-06-28 | 2003-05-06 | Advanced Micro Devices, Inc. | Programming thermal test chip arrays |
US6847010B1 (en) * | 2002-12-04 | 2005-01-25 | Xilinx, Inc. | Methods and circuits for measuring the thermal resistance of a packaged IC |
US6974252B2 (en) * | 2003-03-11 | 2005-12-13 | Intel Corporation | Failsafe mechanism for preventing an integrated circuit from overheating |
DE112005002247T5 (en) * | 2004-09-27 | 2007-08-09 | Advantest Corp. | Consumption current compensation circuit, method for adjusting a compensation current amount, timer and semiconductor test device |
US7855849B2 (en) * | 2007-03-30 | 2010-12-21 | Texas Instruments Incorporated | Methods and apparatus for temperature compensation for hard disk drive write overshoot current |
US20140035603A1 (en) * | 2012-08-03 | 2014-02-06 | Xerox Corporation | Printed Stretch Sensor |
CN107121212A (en) * | 2017-07-06 | 2017-09-01 | 厦门安斯通微电子技术有限公司 | A kind of positive temperature coefficient adjustable temperature sensing chip |
CN110828397B (en) * | 2019-10-28 | 2023-01-10 | 科华数据股份有限公司 | Chip heat dissipation auxiliary circuit and data processing chip |
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US3703651A (en) * | 1971-07-12 | 1972-11-21 | Kollmorgen Corp | Temperature-controlled integrated circuits |
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US4196361A (en) * | 1977-08-08 | 1980-04-01 | Mitsubishi Denki Kabushiki Kaisha | Temperature change detector |
US4980586A (en) * | 1987-10-07 | 1990-12-25 | Tektronix, Inc. | Digital integrated circuit propagation delay regulator |
DE4135853A1 (en) * | 1991-10-31 | 1993-05-06 | Alcatel Sel Aktiengesellschaft, 7000 Stuttgart, De | Active semiconductor element coupled to controllable heat source - which may be external heating element with thermal bridge, or resistive layer monolithically integrated into semiconductor |
US5336939A (en) * | 1992-05-08 | 1994-08-09 | Cyrix Corporation | Stable internal clock generation for an integrated circuit |
US5300968A (en) * | 1992-09-10 | 1994-04-05 | Xerox Corporation | Apparatus for stabilizing thermal ink jet printer spot size |
-
1994
- 1994-11-29 US US08/817,762 patent/US5886564A/en not_active Expired - Fee Related
- 1994-11-29 DE DE4481362A patent/DE4481362B4/en not_active Expired - Fee Related
- 1994-11-29 WO PCT/US1994/013402 patent/WO1996017389A1/en active IP Right Grant
- 1994-11-29 DE DE4481362T patent/DE4481362T1/en active Pending
- 1994-11-29 KR KR1019970703606A patent/KR100307683B1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3703651A (en) * | 1971-07-12 | 1972-11-21 | Kollmorgen Corp | Temperature-controlled integrated circuits |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0831587A2 (en) * | 1996-09-20 | 1998-03-25 | Konica Corporation | Signal delay apparatus |
EP0831587A3 (en) * | 1996-09-20 | 1999-02-03 | Konica Corporation | Signal delay apparatus |
US6060929A (en) * | 1996-09-20 | 2000-05-09 | Konica Corporation | Signal delay apparatus |
EP0998788A1 (en) * | 1997-07-31 | 2000-05-10 | Credence Systems Corporation | Pulse stuffing circuit for programmable delay line |
EP0998788A4 (en) * | 1997-07-31 | 2000-10-11 | Credence Systems Corp | Pulse stuffing circuit for programmable delay line |
EP1914880A1 (en) * | 2006-10-16 | 2008-04-23 | SiTel Semiconductor B.V. | Integrated circuit, comprising a voltage controlled oscillator and a method for controlling a temperature of a voltage controlled oscillator |
WO2008048093A2 (en) | 2006-10-16 | 2008-04-24 | Sitel Semiconductor B.V. | Integrated circuit, comprising a voltage controlled oscillator and a method for controling a temperature of a voltage controlled oscillator |
WO2008048093A3 (en) * | 2006-10-16 | 2008-06-05 | Sitel Semiconductor B V | Integrated circuit, comprising a voltage controlled oscillator and a method for controling a temperature of a voltage controlled oscillator |
CN102859373A (en) * | 2010-05-06 | 2013-01-02 | 德州仪器公司 | Circuit for controlling temperature and enabling testing of a semiconductor chip |
Also Published As
Publication number | Publication date |
---|---|
DE4481362B4 (en) | 2009-01-08 |
KR987000694A (en) | 1998-03-30 |
DE4481362T1 (en) | 1997-10-16 |
US5886564A (en) | 1999-03-23 |
KR100307683B1 (en) | 2001-12-17 |
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