WO1996014684A1

WO1996014684A1 - Solid state, resettable overcurrent protection device

Info

Publication number: WO1996014684A1
Application number: PCT/US1995/013893
Authority: WO
Inventors: David C. Bliven
Original assignee: Raychem Corporation
Priority date: 1994-11-02
Filing date: 1995-10-31
Publication date: 1996-05-17
Also published as: ZA959257B; IL115797A0

Abstract

A circuit protection arrangement (16) which, when series connected in a line (14) of an electrical circuit, will allow normal currents to pass under normal operating conditions and will switch to produce an open state in the line (14) when subjected to an overcurrent, and which comprises: a) a current sensing circuit (30), which, in use, senses a current level on the line; b) a first field effect transistor (FET) (22) which comprises a source, a drain and a gate, and which, in use, has its source and drain connected in series in the line (14); c) a second FET (26), which comprises a source, a drain and a gate, and which, in use, has its source and drain connected in series in the line (14); and d) a control circuit (34) which is coupled to the current sensing circuit and to the gates of the first and second FETs (22, 26), and which, in use, switches the first and second FETs (22, 26) OFF when the current level sensed by the current sensing circuit (30) is above a predetermined current level, thereby producing an open state in the line (14). The arrangement (16) provides resettable overcurrent and overvoltage protection in electrical circuits, and is particularly useful in cable television (CATV) circuits.

Description

SOLID STATE, RESETTABLE OVERCURRENT PROTECTION DEVICE

This invention relates to the protection of electrical circuits against overcurrents.

Cable television (CATV) circuits carry both ac signals and ac power, and include repeater circuits. In such CATV circuits, overcurrent conditions can be caused by a variety of factors such as power surges, equipment faults, lightning, and physical damage to the cable. The repeater circuits are conventionally protected against overcurrents by fiises or resettable bimetallic elements. However, fuses must be replaced after they blow open, and bimetallic elements may be damaged by arcing and may also require replacement. Similar problems arise in other electrical circuits protected by fuses or bimetallic devices.

We have discovered an arrangement of solid state devices which provides resettable overcurrent and overvoltage protection arrangements in electrical circuits, and which is particularly useful in CATV circuits.

In a first aspect, the invention provides a circuit protection arrangement which, when series connected in a line of an electrical circuit, will allow normal circuit currents to pass under normal operating conditions and will switch to produce an open state in the line when subjected to an overcurrent, and which comprises: a. a current sensing circuit which, in use, senses a current level on the line; b. a first field effect transistor (FET) which comprises a source, a drain and a gate, and which, in use, has its source and drain connected in series with the line; c. a second FET which comprises a source, a drain and a gate, and which, in use has its source and drain connected in series with the line; and d. a control circuit which is coupled to the current sensing circuit and to the gates of the first and second FETs, and which, in use, switches the first and second FETs OFF when the current level sensed by the current sensing circuit is above a predetermined level, thereby, in use, producing an open state in the line.

In a second aspect, the invention provides an electrical circuit, preferably a CATV circuit, which comprises a power supply, an electrical load, a line connecting the power supply and the load, and a circuit protection arrangement as defined in the first aspect of the invention which is connected in series with the line.

In various embodiments, preferred features of the invention include:

(1 ) The current sensing circuit comprises (i) means for converting an ac current to a dc current and (ii) an RC filter which senses the dc current level.

(2) The current sensing circuit comprises a power supply control circuit which provides an output voltage level irrespective of whether the first and second FETs are ON or OFF.

(3) The control circuit comprises (i) a comparator which compares the sensed current level with a predetermined current level and outputs a first signal indicative of the comparison, and (ii) FET control means which is coupled to the comparator and which switches the first and second FETs OFF in response to the first signal when the sensed current level exceed the predetermined current level.

(4) The transistor control means comprises a pulse circuit which outputs a pulse of a predetermined duration to switch the first and second FETs OFF in response to the first signal. The predetermined duration may be selectable, typically in increments, and may be, for example, between 8 milliseconds and

2-3 seconds.

(5) The control circuit comprises resetting means for switching the first and second FETs ON after the predetermined duration, and preferably, for switching the first and second FETs ON at the zero-crossing point of the ac current.

(6) The invention comprises (i) voltage sensing means for sensing a voltage level across the circuit protection arrangement, and (ii) voltage protection means, coupled to the voltage sensing means, for shorting power across the arrangement to an absolute ground reference if the sensed voltage level is above a predetermined voltage level.

(7) One or more additional FETs are connected in parallel with one or both of the first and second FETs to reduce the resistance of the arrangement in the line and thus reduce power consumption.

(8) The FETs are medium voltage, high speed power FETs.

(9) The arrangement is implemented in two- wire or three- wire configurations.

(10) The arrangement is capable of handling current levels up to or above six or seven amps.

(11) The arrangement is capable of operating on power levels between 100 milliwatts and 10 watts.

The invention is illustrated in the accompanying drawings in which like components are given the same reference numerals in each Fig. in which they appear.

Fig. 1 is a schematic diagram of a part of a CATV system, namely a single closed loop 10 which serves a single subscriber 20 and includes a power supply 12, a transmission line 14, a circuit protection arrangement of the invention 16 and an amplifier 18, all connected in series. The arrangement 16 lies between points PPl and PP2, which are referred to in other figures. The complete CATV system would include many such loops, formed by splitting the line 14, and then by successively splitting subsequent transmission lines.

Power supply 12 is typically a harmonic, balanced transformer which places a 60 volt, 60 hertz ac power signal on a CATV signal. The 60 volt, 60 hertz ac power signal has very quick rise and fall times and is essentially a square wave. The CATV program signal is an ac signal having a bandwidth sufficient to carry multiple channels. The combined CATV program/power signal (usually referred to simply as the CATV signal) is transmitted from the CATV service company to individual subscribers over transmission line 14. The amplifier 18 uses the power signal to amplify the CATV signal so that signal quality is not deteriorated when the signal is split and or repeated. The circuit protection arrangement 16 also uses the power signal.

Fig. 2 is a schematic diagram of one embodiment of the arrangement 16 shown in Fig. 1. The arrangement device 16 is connected in the transmission line 14 between a point after power supply 12 (shown as point PPl) and a point before subscriber 20 and absolute ground (shown as point PP2). The arrangement 16 includes a first pair of field effect transistors (FETs) 22, 24; a second pair of FETs 26, 28; a current sensing circuit 30 for sensing the current level on transmission line 14; a comparator 32 for comparing the sensed current level to a predetermined current level; a reference level circuit 33 for setting a predetermined voltage level; a control circuit 34 for switching FETs 22, 24, 26, and 28 OFF when the sensed current level is above the predetermined current level; and a timing circuit 36 for switching FETs 22, 24, 26, and 28 ON after a predetermined period of time.

FETs 22 and 24 are coupled in parallel between point PPl and current sensing circuit 30. The sources of FETs 22 and 24 are connected to point PPl , the drains are connected to current sensing circuit 30 at node A, and the gates are connected to control circuit 34. FETs 26 and 28 are also connected in parallel. The sources of FETs 26 and 28 are connected to point PP2, the drains are connected to current sensing circuit 30 at node B, which is at virtual ground, and the gates are connected to control circuit 34. The FETs are paired together in parallel arrangements to reduce the resistance of the arrangement 16 in the line, and thus reduce power consumption. Additional FETs may be added in parallel to further reduce the power consumption.

Current sensing circuit 30 is coupled at an output to an input (current sense) of comparator 32. A second input (trip reference) of comparator 32 is coupled to reference level circuit 33, which outputs a voltage representing a current at which the arrangement will trip open and go into a high impedance mode. Reference level circuit 33 can be implemented, for example, with a voltage divider. The output of comparator 32 is input to control circuit 34, which also receives an input from timing circuit 36. In normal operation, the arrangement 16 operates in a low impedance mode consuming a minimum amount of power. FETs 22, 24, 26, and 28, which are medium voltage, high speed power FETs (e.g., MTP12N20 manufactured by Motorola), are biased by the output of control circuit 34, to conduct current between points PPl and PP2. Each FET has a "built-in" parasitic diode so that the ac current on transmission line 14 is always blocked in one direction by either FET pair 22, 24 or FET pair 26, 28. That is, each pair of FETs conducts current during opposite half-cycles of the ac power signal. Thus, a continuous ac current passes through current sensing circuit 30. Current sensing circuit 30 generates a dc signal from the ac current and filters the dc signal. The filtered dc signal is output to comparator 32 where it is compared to the trip reference.

When the output of current sensing circuit 30 is lower than the trip reference level, an overcurrent condition does not exist. The output of comparator 32 is deasserted and control circuit 34 biases FETs 22, 24, 26, and 28 ON. The arrangement 16 continues to function in a low impedance mode. When the output of current sensing circuit 30 rises above the trip reference level, indicating an overcurrent on the transmission line 14, comparator 32 asserts an output signal which triggers control circuit 34 to bias FETs 22, 24, 26, and 28 OFF by providing a low voltage level at the gate of each FET.

Control circuit 34 biases FETs 22, 24, 26, and 28 OFF for a period of time determined by timing circuit 36. Typically, the OFF time is between 8 milliseconds (one cycle) and 2-3 seconds. When the time period set by timing circuit 36 expires, control circuit 34 biases FETs 22, 24, 26, and 28 ON, and the arrangement 16 begins to conduct current. If the overcurrent condition is still present, however, the input to comparator 32 from current sensing circuit 30 will still be greater than the trip reference level, and comparator 32 will signal control circuit 34 to switch the FETs OFF. This cycle continues until the overcurrent condition passes. The control circuit 34 and timing circuit 36 may be implemented, for example, with a standard R/C one-shot chip, or they may be combined with the comparator 32 to be implemented with a microcontroller chip.

Fig. 3 is a schematic diagram of one embodiment of a two-wire version of current sensing circuit 30 shown in Fig. 2. Current sensing circuit 30 includes a transformer 40, a rectifier 42 to convert an ac voltage signal into a dc voltage signal, a filter 44 for detecting the rectified voltage level, and a power supply control circuit 46 for providing power to overcurrent protection device 16 even when FETs 22, 24, 26, and 28 are switched OFF and no current is flowing from PPl to PP2.

Transformer 40 is connected between nodes A and B in the arrangement 16 and is coupled at outputs to rectifier 42. Rectifier 42 is coupled at node D to filter 44 and power supply control circuit 46.

When the arrangement 16 is in the low impedance mode, current flowing between nodes A and B passes through the primary of transformer 40, and the current in the secondary passes through bridge rectifier 42. Transformer 40 is a single-turn transformer for current and power. Rectifier 42 converts the received ac voltage signal into a dc voltage signal which is fed into filter 44. Filter 44 includes a resistor 47 and a capacitor 48 and produces a voltage proportional to current flowing from node A to node B. The current across resistor 47 is provided as an input to comparator 32.

Power supply control circuit 46 includes a pair of diodes 50 and 51, resistors 53, 54, and 55, capacitors 56 and 57, and zener diode 58, and provides a voltage level at output 59. Power supply control circuit 46 ensures that the voltage level at output 59 is available whether the arrangement 16 is in the low impedance mode or the high impedance mode. The voltage at output 59 is used to power circuitry such as control circuit 34 and timing circuit 36.

Diodes 50 and 51 are connected at their anodes to points PPl and PP2, respectively, and at their cathodes to a first terminal of resistor 54. A second terminal of resistor 54 is coupled to a first terminal of resistor 53 and a first terminal of resistor 55 at node C. A second terminal of resistor 55 is coupled to rectifier 42. Capacitor 56 is coupled between node C and virtual ground, and zener diode 58 and capacitor 57 are coupled between the second terminal of resistor 53 and virtual ground. Output 59 is from the second terminal of resistor 53. Without power supply control circuit 46, a voltage level would be available at output 59 only for when current flows between points PPl and PP2 (low impedance mode). Thus, once tripped into the high impedance mode (open circuit), the arrangement 16 could not be automatically switched back to the low impedance mode as there would not be any current from which to derive a voltage level, and thus power would not be available to control circuit 34 and timing circuit 36.

In operation, power supply control circuit 46 provides the voltage at output 59 from current flowing across resistor 54 when FETs 22, 24, 26, and 28 are conducting current and the circuit is in the low impedance mode. AC current flows across resistor 54 from points PPl and PP2 through diodes 52 and 53, respectively, depending on which half cycle the current is in. In the high impedance mode, there is no current flowing between points PPl and PP2. There is, however, essentially 60 volts across points PPl and PP2. Thus, power control supply circuit is able to provide a voltage level at output 59 from the current flowing from diodes 50 and 51 over resistor 54.

Fig. 4(a) is a schematic diagram of one embodiment of a three-wire version of current sensing circuit 30 shown in Fig. 2. Current sensing circuit 30 includes a transformer 40, a rectifier 42, a filter 44, and a resistor 59, the operation of which is similar to that of their counterparts described in Fig. 3, and therefore, is not described in detail here.

Fig. 4(b) is a schematic diagram of one embodiment of a power supply control circuit 60 used in conjunction with the three- wire version of current sensing circuit 30 shown in Fig. 4(a). In a three-wire version, a voltage level at an output 68 is derived from the third wire, which is connected to absolute ground as shown in Fig. 1 by point PP3. Power supply control circuit 60 shown in Fig. 4(b) is connected to current sensing circuit 30 shown in Fig. 4(a) through the same virtual ground reference indicated by point B.

Power supply control circuit 60 includes a diode 62, a resistor 63, a zener diode 64, and capacitors 65 and 66 and provides an output voltage level at an output 68. Diode 62 is coupled at its anode to absolute ground point PP3 and at its cathode to a first terminal of resistor 63. Capacitor 65 is coupled between the cathode of diode 60 and virtual ground (point B), while zener diode 64 and capacitor 68 are coupled between the 5 second terminal of resistor 63 and virtual ground. The voltage level at output 68 is taken from the second terminal of resistor 63.

During the negative half cycle of the ac signal, the voltage at virtual ground is lower than the voltage at absolute ground. Accordingly, for one half of each cycle, diode

10 62 conducts current which charges capacitor 65 and flows across resistor 63. During the positive half cycle, current does not flow across diode 62, but instead flows from the discharging capacitor 65 across resistor 63. Thus, a constant voltage level, as regulated by zener diode 64, is provided at output 68, and is used to power circuitry in the same manner as the voltage level at output 59.

15

Fig. 5 is a schematic diagram of a second embodiment of a three- wire version of current sensing circuit 30 shown in Fig. 2. Current sensing circuit 30 shown in Fig. 5 includes a resistor 70, an amplifier 72 for amplifying the voltage signal across resistor 70, a rectifier 74 for rectifying the ac current across resistor 70 into dc current, a resistor 76,

20 and a filter 44. Power is supplied in the three-wire resistor system in the identical manner power is supplied in the three-wire transformer system of Fig. 4(b). Therefore, only the construction and operation of current sensing circuit 30 is described below.

Resistor 70 is a low value resistor, approximately one quarter ohm, which

25 consumes little power and is connected between nodes A and B. Amplifier 72 is connected across resistor 70 and amplifies the voltage drop across the resistor, which voltage drop is proportional to the current flowing through the resistor. The output of amplifier 72 is rectified by rectifier 74 so that a dc voltage signal is input to filter 44.

30 Rectifier 74 includes an inverter 77 and a diode 78 connected in parallel with a diode 79. During the positive half-cycle of the ac voltage signal, current flows through diode 79 while the inverted current is blocked by diode 78. During the negative half- cycle of the ac voltage signal, current is blocked by diode 79 while the inverted current flows through diode 78. The output of rectifier 74 is input to filter 44, which is identical to filter 44 described with respect to Fig. 2.

Figs. 6(a)-(c) are a schematic diagram of the preferred embodiment of the arrangement 16 incorporating the three- wire resistor system shown in Fig. 5. Connections in the diagrammed circuit between Figs. 6(a) and 6(b) are shown by points D, E, F, and G. The components of overcurrent protection device 16 in Figs. 6(a)-(c) include a low-pass filter 80, a voltage protection circuit 82, an amplifying circuit 84, an R/C one-shot circuit 86, a voltage divider 88, FETs 22, 24, 26, and 28, comparator 32, filter 44, resistor 70, and power supply circuit 60.

Inputs of low-pass filter 80 are coupled to transmission line 14 at points PPl and PP2, and outputs of low-pass filter 80 are coupled to inputs of voltage protection circuit 82. Voltage protection circuit 82 is coupled to the sources of FETs 22 and 24 at a first output and to the sources of FETs 26 and 28 at a second output. The drains of FETs 22 and 24 are coupled to node A. The drains of FETs 26 and 28 are coupled to node B (virtual ground).

The gates of FETs 22, 24, 26, and 28 are all coupled to an output of R/C one-shot circuit 86. Inputs to R/C one-shot circuit 86 are connected to the output of comparator 32 and the output of power supply control circuit 60. The input of power supply control circuit 60 is connected to absolute ground at point PP3.

Resistor 70 is coupled between nodes A and B, and the inputs of amplifying circuit 84 are connected across resistor 70. The output of amplifying circuit 84 is connected to the input of filter 44, and the output of filter 44 is connected to comparator

32.

In operation, the CATV signal on transmission line 14 is input to low-pass filter

80, which filters out the high frequency CATV program signal coexistent with the 60 hertz ac power signal. This prevents noise from the arrangement 16 from degrading the CATV program signal. The filtered output of low-pass filter 80 is input to voltage protection circuit 82, which protects the system from overvoltage conditions.

When the voltage level between PPl and PP3 rises above a predetermined voltage level (e.g., 130 volts), triacs Q4 and Q5 are switched ON by voltage protection devices Q7 and Q6, respectively, shorting power to absolute ground. Similarly, when the voltage level between PP2 and PP3 increases above the predetermined voltage level, triacs Q4 and Q3 are switched ON by voltage protection devices Q7 and Q8, respectively, shorting power to absolute ground. If, on the other hand, the voltage between PPl and PP2 rises above a second predetermined voltage level (e.g., 140 volts), triacs Q3 and Q5 are switched ON by voltage protection devices Q8 and Q6, respectively, shorting power across FET devices 22, 24, 26, and 28. Voltage protection devices Q6, Q7, and Q8 may be bilateral switches or other devices which provide overvoltage protection.

Resistor 70 is of very small resistance (e.g., 0.005 ohms) so that as little power as possible is consumed by the arrangement 16. Amplifying circuit 84 amplifies and rectifies the signal across resistor 70 providing the functionality of amplifier 72 and rectifier 74 of Fig. 5. Rectification and amplification are simultaneously provided because the current across resistor 70 is input to the noninverting input of amplifier A and the inverting input of amplifier B.

The output of amplifying circuit 84 is input to filter 44, and the output of filter 44 is input to comparator 32. Filter 44 and comparator 32 function in a manner identical to their counterparts described with respect to Fig. 2. Also, as described in Fig. 2, a second input to comparator 32 (the output of voltage divider 88) sets the current trip reference level.

R/C one-shot circuit 86 controls the gates of FETs 22, 24, 26, and 28 to shut the flow of current OFF when comparator 32 determines that the current level rose above the trip reference level set by voltage divider 88. After the FETs are switched OFF, R/C one- shot circuit 86 waits a predetermined amount of time before attempting to switch the circuit back ON. The duration of delay is set through five inputs on the R C one-shot chip allowing up to 24 different time delays to be selected using the circuitry shown in Figs. 6(a)-(c). Typically, the delay is set between 8 milliseconds and 2-3 seconds. R/C one-shot circuit 86 operates off voltage supplied by power supply circuit 60 in a similar manner as described with respect to Fig. 4(b).

To lessen the chance of circuit damage which can occur when the FETs are switched back ON and an overcurrent condition still exists, R/C one-shot circuit 86 switches FETs 22, 24, 26, and 28 ON near the zero-crossing point of the ac current signal. To control switching the FETs ON at or near the zero-crossing point, R/C one-shot circuit 86 inputs the ac power signal as a clock input and outputs a signal to the gates of the FETs timed on this clock signal. Thus, even if a severe overcurrent condition is present on transmission line 14, FETs 22, 24, 26, and 28 are switched ON at a point near zero amps.

Claims

5 LΔIMS

1. A circuit protection arrangement which, when series connected in a line of an electrical circuit, will allow normal circuit currents to pass under normal operating conditions and will switch to produce an open state in the line when subjected to an overcurrent, and which comprises:

(a) a current sensing circuit, which, in use, senses a current level on the line;

(b) a first field effect transistor (FET) which comprises a source, a drain and a gate, and which, in use, has its source and drain connected in series with the line; (c) a second FET, which comprises a source, a drain and a gate, and which, in use, has its source and drain connected in series with the line; and

(d) a control circuit which is coupled to the current sensing circuit and to the gates of the first and second FETs, and which, in use, switches the first and second FETs OFF when the current level sensed by the current sensing circuit is above a predetermined current level, thereby producing an open state in the line.

2. An arrangement as claimed in claim 1 which is suitable for use when the current on the transmission line is ac current, and wherein the current sensing circuit comprises

(i) means for converting the ac current to a dc current; and (ii) an RC filter which senses the converted dc current level.

3. An arrangement as claimed in claim 1 or claim 2 wherein the current sensing circuit comprises a power supply control circuit which provides an output voltage level irrespective of whether the first and second FETs are ON or OFF.

4. An arrangement as claimed in any one of claims 1 to 3, wherein the control circuit comprises:

(i) a comparator which compares the sensed current level with the predetermined current level and outputs a first signal indicative of the comparison; and (ii) transistor control means which is coupled to the comparator and which switches the first and second FETs OFF in response to the first signal, when the sensed current level exceeds the predetermined current level.

5. An arrangement as claimed in claim 4 wherein the transistor control means comprises a pulse circuit which outputs a pulse of a predetermined duration to switch the first and second FETs OFF in response to the first signal.

6. An arrangement as claimed in claim 5 wherein the control circuit comprises resetting means for switching the first and second FETs ON after the predetermined duration.

7. An arrangement as claimed in claim 6 wherein the resetting means switches the first and second FETs ON at the zero-crossing point of the ac current.

8. An arrangement as claimed in any one of claims 1 to 7 further comprising: (a) voltage sensing means for sensing a voltage level across the circuit protection arrangement; and

(b) voltage protection means, coupled to the voltage sensing means, for shorting power across the arrangement to an absolute ground reference if the sensed voltage level is above a predetermined voltage level.

9. A circuit which comprises a power supply, an electrical load, a line connecting the power supply and the load, and a circuit protection arrangement as claimed in any one of claims 1 to 8 which is connected in series in the line.

10. A circuit according to claim 9 which is a cable television circuit.