WO1996013940A1

WO1996013940A1 - Digital data packet multiplexer, in particular for digital television

Info

Publication number: WO1996013940A1
Application number: PCT/FR1995/001396
Authority: WO
Inventors: Jean-Michel Masson; Frédéric GRENIER
Original assignee: Matra Communication
Priority date: 1994-10-26
Filing date: 1995-10-23
Publication date: 1996-05-09
Also published as: FR2726413B1; FR2726413A1; AU688616B2; AU3847095A; CA2203786A1; CN1166906A; EP0788717A1

Abstract

A device including a plurality of packetising modules (C1, C2, ..., Cn) supplying packet memories (PM1, PM2, ..., PMm) from digital input streams (IS1, IS2, ..., ISn), and multiplexing means (14). Each packet in a packet memory is combined with selection parameters written into a related parameter memory (ZM1, ZM2, ..., ZMm) by its packetising module. The multiplexing means include processing means connected to the parameter memories via a parameter bus (12) for selecting the packet memories from which the multiplex packets are to be retrieved by analysing the respective selection parameters combined with the first packets on stand-by in each of the packet memories, and transfer means connected to the packet memories via a packet bus (10) and controlled by the processing means to retrieve a series of multiplex packets from the selected packet memories.

Description

MULTIPLEXER OF DIGITAL INFORMATION PACKETS, ESPECIALLY FOR DIGITAL TELEVISION

The present invention relates to a device for producing a time multiplex of digital information packets, comprising several packetization modules each receiving a digital input stream, several packet memories each receiving packets from a respective packetization module, and multiplexing means selecting the packet memories from which the multiplex packets are to be extracted and successively transferring said packets to an output of the device.

The invention relates more particularly to the field of digital television. It applies in particular within the framework of the MPEG2 system standard defined in the draft international standard ISO / IEC 13818-1 of the International Organization for Standardization dated June 10, 1994 (Information Technology - Generic Coding of Moving Pictures and Associated Audio / Recommendation H.222.0). Reference may be made to this ISO / IEC 13818-1 document for any information on the structure of the packages referred to in the present request.

The MPEG2 system standard defines two types of multiplex digital streams: transport streams (TS), and program streams (PS). A "program" is defined as a set of elementary flows correlated in time, that is to say each carrying information to be restored with respect to a common time base. A program stream PS transmits a single program in the form of packets of relatively large length and possibly variable. PS flows are intended for transmission channels which introduce few errors. They are typically used for storing information on disk. Transport flows are consist of packets belonging to one or more programs, and are used for transmission in environments which may introduce errors. Transport packets (TP) have a fixed length of 188 bytes and each include a TP header of at least 4 bytes.

These multiplex flows are constructed from elementary packet flows (PES). The raw elementary streams (ES) directly coming from the video or audio coding are first put in the form of PES packets of variable length. The PES flows are then re-cut to constitute the TS or PS packets to be multiplexed. Currently, some coders leave elementary streams at the ES level, and others at the PES level. The elementary streams can also be composed of data other than audio or video, for example data detailing information specific to a program (PSI), data relating to conditional access to a program (ECM or EMM) ...

The role of an MPEG2 multiplexer is to receive these different elementary streams, to carry out TS or PS packets, then time multiplexing of these packets.

A device according to the invention can also be what is called a remultiplexer. A remultiplexer is a device for producing a multiplex as defined in the introduction, in which at least one of the input streams has already been multiplexed upstream, in PS or TS format. A remultiplexer can be used for example to extract from a transport stream packets relating to a program and produce as output another transport stream or program comprising only this program, to extract from one or more transport streams the packets relating to one or more programs in order to construct another transport flow, or else to convert a program flow into a transport flow in order to transmit it in a lossy environment.

The MPEG2 system standard specifies precisely the constraints that a multiplexer must take into account when multiplexing of packets transporting the various elementary signal flows. Indeed, in order to optimize the size of the input buffers necessary in a decoder (and therefore in order to reduce the price of these decoders), it is necessary to have over time a distribution as homogeneous as possible of the packets of each elementary flow. In the case of a large number of elementary streams to be managed and of significant bit rates for these streams, the work of the multiplexer may require great computing power, and on the other hand the chosen multiplexing method may lead to multiplex streams of different quality output (in terms of packet distribution).

An object of the present invention is to provide a device as defined in the introduction, which is flexible and efficient in order to be able to reach high flow rates.

A device according to the invention thus comprises parameter memories respectively associated with the packet memories. Each packet supplied to a packet memory by a packetization module is associated with a set of parameters, including election parameters, written by said packetization module in the corresponding parameter store. The multiplexing means comprise processing means connected to the parameter memories by a parameter bus to select the packet memories by analyzing the election parameters respectively associated with the first packets waiting in each of the packet memories, and means for transfer connected to the packet memories by a packet bus and controlled by the processing means for successively extracting the packets from the multiplex from the selected packet memories, the processing means selecting the packet memory from where a packet from the multiplex is at extracting while the transfer means transfer a previous packet of the multiplex from a previously selected packet memory. The communication between the specific package modules and the multiplexing module takes place via a memory plane type interface. The packet memories relating to the various package modules are seen as particular areas of the addressable space of the multiplexing module, as are the associated parameter memories. The data passing through this memory plane are organized identically whatever the type of corresponding input stream, which allows the multiplexing module to have systematic and therefore more efficient work. The exchanges via this interface are organized around two buses, which allows the multiplexing module to perform its tasks in parallel and not sequentially.

Other particularities and advantages of the present invention will appear in the description below of a preferred but nonlimiting embodiment, with reference to the appended drawings, in which:

- Figure 1 is a block diagram of a first embodiment of the invention;

- Figure 2 is a block diagram of a package module usable in the device of Figure 1;

- Figures 3 to 5 are diagrams illustrating the operation of package modules according to Figure 2;

Figure 6 is a diagram of a multiplexing module usable in the device of Figure 1;

- Figures 7 and 8 are graphs illustrating an example of priority calculation in a multiplexing module;

- Figure 9 is a diagram of an election circuit usable in the multiplexing module of Figure 6; and

- Figure 10 is an overall block diagram of a second embodiment of the invention. The device represented in FIG. 1 is described below in its application to the production of an OS output multiplex having the format of a TS transport stream within the meaning of the MPEG2 standard. It will be understood that the device would also be applicable for producing another type of multiplex, in particular a PS program stream within the meaning of the MPEG2 standard.

The device comprises n package modules C1, ..., Cn each receiving an input stream IS1, ..., ISn. The n input flows carry a total of m elementary flows. In the case of a multiplexer whose input streams are all constituted by elementary streams respectively coming from coders or from data sources, we have n = m. In the example shown in FIG. 1, the stream IS2 is already multiplexed (for example transport stream TS), and the device is designed to take into account two elementary streams included in this multiplexed stream.

The package modules C1, ..., Cn deliver transport packets TP from each of the elementary streams they receive. These transport packets are stored in two access buffer memories PM1, ..., PMm. Each PMi packet memory receives packets from a packetization module. The C2 package modules processing already multiplexed flows can supply several packet memories PM2, PM3. In the latter case, the packet memories PM2, PM3 can conveniently be constituted by two different addressing zones of the same memory plane.

Each packet memory PMi is associated with a parameter memory ZMi also with two ports. Each time a packetization module writes an information packet in a packet memory PMi, it also writes a set of parameters associated with this packet in the corresponding parameter memory ZMi. For reading, the packet memories PM1, ..., PMm are connected to a common packet bus 10, and the parameter memories ZM1, ..., ZMm are connected to a common parameter bus 12. These two buses are connected to a multiplexing module 14 whose role is to select the memories PMi from which the packets of the output multiplex OS are to be extracted and to successively transfer the packets in question to the output of the device.

The package modules Cj analyze the elementary flows they receive in real time and provide the transport packets to the PMi buffer memories. Real-time analysis of an elementary stream and double packetization (PES and TP layers) may require great computing power, in particular for video streams which can reach bit rates of 15 Mbit / s in standard resolution, or more than 100 Mbit / s in high resolution. The C1 package module illustrated in FIG. 2 makes it possible to meet these severe requirements.

This module C1 includes an input buffer 20 receiving the input stream IS1. At the output of the buffer 20, the bytes of the input stream pass through a detection circuit 22 before being transmitted to a storage unit 23 of the first in first out (FIFO) type. The output of the unit 23 is connected to the data input of the packet memory PMI.

The detection circuit 22 is produced in the form of a network of doors programmable by the user (FPGA). It consists of a shift register 24 with four stages of a byte, through which the bytes of the input stream pass before reaching the storage unit 23, and a detection logic 25 receiving the four bytes present in the stages of register 24. Logic 25 is programmed according to the states to be detected in the input stream. The logic 25 detects these states of the input stream and informs a microprocessor 26. The processor 26 can access the parameter memory ZMI by its address and data buses 28, 29. The buses 28, 29 are also connected to the PMI packet memory via a three-state gate 31. The storage unit 23 is managed to contain 184 bytes of the input stream at any time, and so that each byte leaving this unit causes the entry of another byte. The unit 23 could therefore be produced simply in the form of a shift register with 184 stages of a byte. If one does not have shift registers of this size, one can cascade several of them, or even use a random access memory whose read and write addresses are generated so as to keep between them a constant difference corresponding to a capacity of 184 bytes.

As a function of the states detected by the logic 25, the processor 26 supplies a transfer sequencer 32 with control parameters for carrying out the bytes of the input stream from the storage unit 23 to the packet memory PMI. These control parameters include a starting address for writing the data of a packet in the memory PM1, and the number of bytes to be transferred from this address. Sequencer 32 includes an address counter which initializes to the value of the starting address supplied by the processor, and which increments with each byte transferred until the specified number of bytes has been transferred . This counter provides the write addresses of the bytes in the PMI memory. If the storage unit 23 is in the form of a random access memory, the sequencer 32 also supplies the reading address of the byte to be transferred so as to comply with the first in - first out protocol in this memory. The sequencer delivers a signal SC which rates the transfers from and to the unit 23, the shifts in the register 24 of the detection unit, and the byte readings in the input buffer 20.

In the example shown in FIG. 2, the input stream IS1 is an elementary stream (ES or PES) to be packaged. The detection logic 25 is programmed to detect synchronization words in the input stream. As a function of the states detected by the logic 25, the processor 26 determines the length and the content of the header to be placed at the start of the next transport packet to be written into the memory PM1. This header is determined in accordance with the specifications of the MPEG2 standard, the processor 26 executing a header training program as described in the document ISO / IEC 13818-1. The length L of the header can vary between k = 4 bytes and K = 188 bytes. Thus, the capacity of K - k = 184 bytes of the storage unit 23 guarantees that all of the bytes of the input stream that can be introduced into a transport packet have been analyzed by the detection circuit 22 before this packet begins to be transferred from the storage unit 23 to the packet memory PMI.

FIG. 3 illustrates the construction of transport packets TP by the package module in the case of a raw elementary stream ES originating from an audio coder. In accordance with the MPEG2 standard, the audio ES stream consists of frames of constant length, each starting with a 35A frame header. The header 35A contains a 12-bit synchronization word equal to FFF in hexadecimal. The detection logic 25 of a package module processing an audio ES stream is therefore programmed to detect this synchronization word FFF. A PES stream constructed from such an ES stream may include a PES header 36 immediately before each ES header 35A. However, the present package module, when it processes an audio ES stream, does not explicitly pass through the PES stage, but on the contrary directly constructs TP transport packets. In the case shown in FIG. 3, as long as the logic 25 does not detect the synchronization word FFF in the input stream, the processor 26 calculates a header 37a of L = 4 bytes, and controls the transfer of 188 - L = 184 bytes from the storage unit 23 to the memory PMI to constitute a transport packet TP. When logic 25 detects a synchronization word during the transfer of a packet to the PMI memory, the processor 26 calculates the length L of the header 37b of the next packet so as to complete a transport packet of 188 bytes with the bytes of the elementary stream going up to the synchronization word detected. To produce a header of length L greater than 4 bytes, the processor 26 introduces flow management parameters or stuffing bytes in the adaptation field of the header, as specified by the MPEG2 system standard. . The packet which will follow the transport packet thus formed will not contain any byte of the input stream, but only a TP 37c header and a PES header 36. It can therefore be considered that the processor 26 has determined a header composite 37c-36 of L = 188 bytes and ordered the transfer of K - L = 0 bytes from unit 23 under this packet. The PES 36 header is calculated in accordance with the MPEG2 system standard, and the length of the TP 37c header will be adapted using the adaptation field as for the previous packet.

FIG. 4 is a diagram similar to that of FIG. 3 in the case of an ES stream of the video type. According to the MPEG2 standard, a video type ES stream comprises three types of headers: 35S sequence headers containing a 4-byte synchronization word equal to 000001B3 in hexadec, 35G image group headers containing a 4-byte synchronization word with the value 000001B8 in hexadecimal, and 35P image headers containing a 4-byte synchronization word with the value 00000100 in hexadecimal. The structure of the video ES stream is such that a 35S sequence header is always immediately followed by a 35G image group header or by a 35P image header, and that a header 35G image group is always followed by a 35P image header. The length of the video data relating to an image, according to each 35P image header, is variable. A PES stream constructed from such a video ES stream may contain a PES header 36 before each 35S sequence header, before each 35G group header which is not immediately preceded by a sequence header 35S, and before each 35P image header which is not immediately preceded by a 35G group header. However, the present packetization module, when processing a video ES stream, does not explicitly produce the corresponding PES stream, but directly TP transport packets. The insertion of the PES and TP headers is essentially carried out in the same way as in the audio case described with reference to FIG. 3, the detection logic 25 being programmed to detect the synchronization words of the headers 35S, 35G and 35P. However, processor 26 does not insert a PES header 36 before all 35P image headers, but only before those which are not immediately preceded by an image group header

35G or by a 35S sequence header. Likewise, processor 26 does not insert a PES header before all 35G image group headers, but only before those which are not immediately preceded by a 35S sequence header. These different conditions can easily be identified on the basis of the synchronization words detected by the logic 25.

FIG. 5 is a diagram similar to those of FIGS. 3 and 4 in the case of an audio or video PES type input stream. The PES header 36 present in each packet of the PES stream contains a synchronization word of 4 bytes, the first three of which are worth 000001 in hexadecimal and the fourth is a byte identifying the stream. This identification byte being known in advance for a given PES stream to be processed by the package module, logic 25 can be programmed to detect the 4 byte synchronization words of the PES stream. The division into TP transport packets is then carried out by the processor 26 in the same manner as in the case of FIGS. 3 and 4, on the basis of the PES headers 36. The processor 26 does not take account of the ES headers 35 which are treated as elementary stream data. As in the cases of FIGS. 3 and 4, the processor 26 can be programmed so that a TP packet containing a PES 36 header does not contain data from the elementary stream. The processor 26 then needs to know the length L 'of the PES header to constitute a packet containing only one TP header 37c of length L = K - L bytes followed by the PES header 36. This length L ′ can be read in the PES header itself by means of the detection circuit 22: if the seventh byte from the start of the PES header does not start with the two bits' 10 ', the PES header has a length of L' = 6 bytes; otherwise the length L 'is read in the ninth byte from the start of the PES header (see document ISO / IEC 13818-1).

The advantage of constituting the transport packets containing a PES 36 header by putting only in these packets a TP 37a-c header and said PES header 36 is to allow scrambling of all the transport packets containing ES elementary stream data, the PES header should not be scrambled.

The processor 26 writes, via the gate 31, the headers 37a-c and / or 36 at the appropriate positions in the packet memory PMI so as to respect the structure of the packets TP shown in FIG. 3, 4 or 5. This writing can take place before the transfer of the 188 - L bytes of the input stream belonging to the packet in question. It can also be performed later provided that the packet in question is still present in the PMI memory, in particular in the case where the header TP of a packet must contain parameters dependent on packets arriving subsequently at the packetization modules (by example of image splitting parameters in the case of a video ES stream).

When the input stream is a multiplex transport stream, the detection logic 25 is programmed to detect the synchronization byte indicating the start of a transport packet. This synchronization byte is 47 in hexadecimal. The processor 26 identifies the time of entry of the packet when the synchronization byte is detected. In analyzing the following bytes of the header TP via the detection circuit 22, the processor 26 can read the 13 bits of identification of the packet (PID field) and determine if it contains optional time fields of the type PCR or LTW. The presence of the PCR or LTW fields is indicated by bits of determined position in the TP header (see document ISO / IEC 13818-1). The position of the PCR field is fixed, but that of the LTW field can vary so that the position of this field is also indicated, if necessary, to the processor 26 by the circuit 22.

Knowing the PID identification parameter of the packet, which characterizes the elementary stream from which it comes, the processor 26 can perform a filtering operation in order to transfer to the packet memory only the packets of the elementary streams to be kept in the multiplex Release. To eliminate a packet, the processor 26 controls the transfer sequencer 32 so that it writes the packet in the packet memory to a trash address where it will never be read.

In the case where the package module is associated with several packet memories PM2, PM3, these memories are grouped in the same address space, and the write addresses generated by the transfer sequencer 32 are determined on the basis of the PID identification parameter supplied to the processor 26 by the detection circuit 22 so as to obtain the first in - first out operation in each of the packet memories PM2, PM3. It is thus possible to direct the elementary streams to be stored in an input multiplex stream to different packet memories.

The package module shown in Figure 2 has great flexibility. It is easily adaptable to a wide variety of input streams, by simple programming of the detection logic 25 and of the processor 26. This module is therefore particularly suitable for a modular architecture of the device. In the case of a flow input type ES, it allows simultaneous carrying out of the two packetization phases (PES and TP) by means of a single processor, the PES header being considered as an extension of the TP header . It is also suitable for TS or PS type input flows in remultiplexing applications.

The development of a packet is carried out in parallel with the transfer of data from the previous packet to the PMi memory, which makes it possible to process significant input bit rates. The transfer is entrusted to a separate sequencer, which frees the single processor from the package module for other processing to be performed.

Another task executed by the processor 26 is the calculation of the parameters associated with the packets and their writing in the parameter memory ZMi. These parameters include election parameters allowing the multiplexing module 14 to select the packet memories for transferring the packets to the output of the device. Thus, part of the tasks usually carried out by the multiplexing module are transported into the packaging modules. The additional load for the processor 26 is however low enough not to have a significant impact on the choice of this processor which is in any case necessary for packetization.

To approach an optimal time distribution at exit, it is necessary to know:

- packets that can be released immediately and the maximum delay that can be attributed to them.

- the packets which can be released soon and the time from which we can anticipate their transmission.

One solution for giving the multiplexing module 14 visibility over this broadcast information is to ask the packetization modules to associate with each packet written in the buffer PMi three election parameters each corresponding to a time expressed by compared to a time base common to the package and multiplexing modules. These three parameters are the minimum time Tmin, the maximum time Tmax and the ideal time Tideal of transmission of the packet with which they are associated.

Each processor 26 managing an elementary stream therefore defines a time window for the transmission of each packet created, and is free to adapt the width of this window to the nature of the stream it manages. In addition, to help the multiplexing module 14 in its task and to allow it to generate a quality stream, it defines an ideal position of the packet in its window. The management of the Tmin, Tmax and Tideal parameters is specific for each type of input stream.

In the case where the input stream is an elementary stream (ES, PES or data), the minimum transmission time Tmin is calculated by adding a latency time Tl to the entry time Te of the packet data in the input buffer 20 of the packetization module, and the difference Tmax - Tmin between the maximum time and the minimum time of emission is calculated as a function of the type of elementary flow and of the flow of this flow. If the source of the elementary flow has a regular flow, the input time Te is simply deduced by the processor 26 from the time of passage of the data by the detection circuit 22. If the source of the elementary flow has a flow in bursts, the entry time can be retrieved from bit rate information received from the encoder located upstream or read from the stream. The latency time T1 is a programmable time intended to delay the emission of certain streams compared to others. The window width Tmax - Tmin is taken smaller for temporal streams, in particular video streams, than for streams without very precise retransmission constraint, such as EMM conditional access data streams. The difference Tmax - Tmin is also a decreasing function of the elementary flow rate.

In the case of a multiplex input stream of the type transport stream, the minimum time Tmin of retransmission of a packet is calculated as a function of the time of entry Te of the packet into the module and of a latency time Tl as in the previous case, and furthermore depending on the strategy adopted by the previous multiplexer. This strategy is indicated in the LTW fields of the TP headers of the stream or in descriptor fields, these fields being able to be read by the processor 26 via the detection circuit 22. The minimum calculated time Tmin is for example delayed , compared to Te + Tl of the time corresponding to the window shift (LTW_offset) read in the stream. In the case of a multiplex input stream, the maximum re-transmission time Tmax is calculated according to the type of stream. For most of the elementary flows of a transport flow, the difference Tmax -Tmin is taken equal to 4 ms. However, for certain particular cases, this difference can be increased to alleviate the constraints of the multiplexing module.

The ideal time for sending a packet is obtained according to the multiplexing strategy adopted for the elementary stream containing this packet. This ideal time can be defined by an offset from the minimum time Tmin, this offset being fixed or even proportional to the width Tmax - Tmin of the transmission window. An "early" strategy corresponds to a Tideal time relatively close to the minimum time Tmin. Such a strategy favors the coder or the multiplexer situated upstream, which can have a reduced output buffer memory. A "late" strategy corresponds to a Tideal time relatively distant from the minimum time Tmin. Such a strategy favors the decoder or the remultiplexer situated downstream in the sense that its input buffer memory can be reduced in size. There is a range of "early" and "late" strategies.

In a typical embodiment, the election parameters stored in the ZMi parameter memories are the ideal transmission time Tidéal coded on 20 bits, the difference Tidéal - Tmin coded on 15 bits, and the difference Tmax - Tidéal coded on 15 bits, expressed in relation to a reference clock at 90 kHz. These parameters are stored at an address linked to the address of the associated packet in the PMi memory.

The parameters associated with a packet and stored in the ZMi parameter memories also include modification parameters allowing the multiplexing module 14 to update the header of the packet as a function of its transmission time when necessary. . These modification parameters include for example:

bits indicating the presence or absence, detected by the logic 25, of a PCR type field or of an LTW type field, which can only be updated when the exact time of exit of the packet is known, requiring very precise time references. In the case of a PCR type field whose position is fixed relative to the start of the packet, a bit is enough to indicate whether such a field is present in the packet. In the case of an LTW type field, the position of which can vary, the modification parameters also indicate the position of this field in the packet;

- size of the given part (payload) of the package.

This information is useful in the case where the multiplexing module 14 also performs scrambling of the packet;

- PID identification parameter of the packet. This information, useful in remultiplexing applications, allows the multiplexing module 14 to know if it must change this parameter (case where the same PID identification parameter is assigned to several elementary streams contained in the input streams).

An architecture of the multiplexing module 14 is shown in the diagram in FIG. 6. This module comprises on the one hand a microprocessor 40 and an election circuit 42 which process the data contained in the parameter memories ZMi, and on the other hand a transfer sequencer 44 which controls the transfer of packets from the packet memories PMi to the output buffer 46 of the device. It will be understood that the multiplexing module 14 could include still other elements, for example for scrambling the transferred packets before writing them into the output buffer.

The multiplexing module 14 further comprises an additional packet memory PM0 and an associated parameter memory ZM0. The PM0 memory contains information packets specific to the programs carried by the output multiplex (PSI), which specify, among other things, the PID identification parameters of the flows of each program (see chapter 2.4.4 of the document ISO / IEC 13818- 1). These PSI packets are written in the memory PM0 by a source (not shown) also belonging to the multiplexing module 14. This source also writes in the memory ZM0 election parameters associated with these packets: Tmin, Tmax, Tideal. The time constraints of the PSI packets not being very severe, the time window for transmission of these packets can be taken relatively wide.

From the point of view of the multiplexing module 14, the packet memories PM0, PM1, ..., PMm are considered as a single address space. Similarly, the parameter memories ZM0, ZM1, ..., ZMm are considered for reading as a single address space. FIG. 6 shows the data bus 10D and the address bus 10A included in the packet bus 10. These two buses 10A, 10D are connected respectively to the address and data inputs of each of the packet memories PMi. The addresses on the bus 10A are generated by the transfer sequencer 44 under the control of the processor 40. The data bus 10D is also connected to the input of the output buffer 46 where the writing of the data is controlled by the sequencer 44 .

Figure 6 also shows the 12D data bus and the address bus 12A controlled by the processor 40 and included in the parameter bus 12. These two buses 12A, 12D are respectively connected to the address and data inputs of each of the parameter memories ZMi. The packet 10 and parameter 12 buses are linked together by a three-state gate 48 allowing the processor 40 to take control of the packet bus 10. To order the sequencer 44 to transfer a transport packet from 188 bytes to the output buffer, the processor 40 has a start address on the address bus 12A. This starting address is transmitted to the bus 10A via gate 48, and the sequencer address counter 44 initializes to the value of this starting address, then increments until the 188 bytes of the packet are transferred.

The address buses 10A, 12A are wide enough for the PMi packet and ZMi parameter memories to be seen as a single address space by the processor 40. 24-bit address buses are suitable for a multiplexer or remultiplexer large capacity (m≤128 for example). To gain output speed, the data buses 10D, 12D can be 16-bit buses, transferring two bytes at a time.

The sequencer 44 is separated from the processor 40 in order to allow the processor 40 and the circuit 42 to carry out the processing relating to the transmission of a packet in the multiplex while the preceding packet of the multiplex is being transferred under control. of the sequencer. This allows the multiplexing module 14 to adapt to the high transmission rate required by the MPEG2 standard.

The treatments carried out before the transfer of a package include:

the selection of the packet memory PMi in which this packet will be read and the determination of the starting address to be supplied to the sequencer 44 to ensure the transfer of this packet;

- analysis of the relative modification parameters to the chosen package and the possible modification of the corresponding fields.

The processor 40 receives from the equipment located downstream of the device a signal CK of the timing of the output multiplex. The processor 40 calculates the transmission time Ts of the next packet from this signal CK.

The choice of the packet memory from which the next packet will be extracted is made on the basis of this transmission time Ts and the election parameters Tmin, Tmax, Tideal present in the first positions of the parameter memories ZMi, c that is to say election parameters associated with the first packets waiting in each of the packet memories PMi.

Annex 1 presented at the end of this description gives an example of a C language election algorithm which can be used to select the packet memories from which to extract the packets from the multiplex. In the notations of appendix 1, nb_sources corresponds to the number of packet memories connectable to the packet bus 10 (nb_ sources = m + 1 when the entire capacity of the multiplexing module 14 is used), valid_TP_flag [] is a array of length nb_sources consisting of boolean variables such as valid_TP_flag [current_channel] is true if a PMi packet memory is actually connected to the current_channel position and if this packet memory contains at least one packet awaiting transfer, the Tmin tables [] , Tmax [] and Tidéal [] contain the parameters for electing the first pending packets in each packet memory, current_priority is a priority coefficient calculated for the first pending packet in PM memory (current_channel), and elected_TP_priority is the priority coefficient maximized by the election algorithm, corresponding to the elected packet contained in the PM memory (elected_TP_channel).

A priority coefficient of -1 is assigned to a padding packet stored, for example, in PM0 memory to an address to which a memory number equal to -1 is assigned. This padding packet is selected by default if no packet memory contains a packet which has reached its minimum transmission time Tmin. No packet can normally be transmitted after its maximum time Tmax, since the device is dimensioned so that the sum of the flow rates of the input flows is less than the flow rate of the output flow.

Figures 7 and 8 show the variations of the priority coefficient of a packet having a given transmission window [Tmin, Tmax] as a function of the transmission time Ts in the case of an "early" strategy figure 7 ) and in the case of a "late" strategy (Figure 8 ,. We see that for a given transmission time and identical windows, the election algorithm favors the flows for which a "early" strategy has been defined ".

The election algorithm presented in appendix 1 can be implemented by processor 40 while the previous packet of the multiplex is being transferred. In this case, the processor 40 must perform readings in the parameter memories ZMi and then execute the algorithm. These tasks take a significant time to the processor. This is why, in high-speed applications, it is preferable to use a separate election circuit 42 as illustrated in FIG. 6. A wired circuit 42 allows the election to be carried out more quickly than a processor, and relieves the burden. processor 40 of the corresponding calculations.

The multiplexing module 14 includes a two-access memory 50 connected to the parameter bus 12 to supply the parameters useful to the election circuit 42. The election parameters Tideal, Tmax - Tideal and Tideal - Tmin associated with the first packet on standby in each packet memory PMi are read by the processor 40 in the corresponding parameter memory ZMi and are written in the memory 50 at an address ADD equal to the number of the packet memory. Processor 40 also writes to memory 50 BM bits corresponding to the previously defined valid_TP_flag Boolean variables: BM = 0 if no packet memory is connected to the position corresponding to the ADD address or if the packet memory connected to the position corresponding to the ADD address does not contain no packet pending at the time considered.

Figure 9 is a diagram of a wired election circuit. This circuit 42 includes a register 52 in which the value of the next transmission time Ts is written by the processor 40. A sequencer 54 supervises the operations performed by the circuit 42 in response to an election command EC received from the processor 40 The sequencer 54 begins by initializing the value of -1 (default packet packet) the contents of two registers 56, 58 intended to contain one the ADDS address corresponding to the selected packet memory and the other the coefficient of corresponding PRIO priority. The sequencer 54 then generates read orders in the working memory 50. At each read cycle, the sequencer 54 increments by an unit an address counter delivering the read address, so as to read the BM parameters sequentially , Tidéal, Tmax - Tidéal and Tidéal - Tmin relating to the different possible addresses. The election circuit 42 comprises a subtractor 60 receiving on its positive input the emission time Ts from the register 52 and on its negative input the ideal time Tideal from the memory 50. The sign bit of the output of the subtractor 60 controls a multiplexer 62 of which one input (positive sign) receives the parameter Tmax - Tideal from memory 50 and the other input (negative sign) receives parameter Tideal - Tmin from memory 50. A divider 64 calculates the quotient between the output of the subtractor 60 and the output of the multiplexer 62. The priority coefficient of the current packet thus provided by the divider 64 is addressed to an input of a comparator 66 whose other input receives the content of the register 58. An AND gate 68 receives on the one hand the bit BM relating to the current packet, and on the other hand the comparison bit produced by the comparator 66. This comparison bit is worth 1 if the calculated priority coefficient of the current packet is greater than that recorded in register 58 and 0 in the opposite case. For synchronism purposes, a shift register 70 delays the bit BM addressed to the AND gate 68 by a number of cycles equal to that necessary for the calculations performed by the elements 60 to 66. The address ADD generated by the sequencer 54 is sent to register 56 after passing through a shift register 72 which delays it by the same number of cycles. The priority coefficient produced by the divider 64 is sent to the register 58. The cycle clock CCK is supplied by the sequencer 54 to the registers 56 to 58 for updating, but this updating is only carried out. on condition that the output of the AND gate 68 is at 1.

The circuit 42 described above makes it possible to execute the election algorithm of appendix 1 in a very short time. Once the election circuit has scanned all the possible addresses, the address ADDS corresponding to the memory PMi where the next packet will be to be read is available in the register 56. The processor 40 can then read this register 56 by the via the parameter bus 12.

Once the processor 40 thus knows the selected packet memory PMi, it proceeds to the following operations:

the modification parameters of the selected packet are read in the associated parameter memory ZMi;

the processor 40 analyzes these modification parameters and, if necessary performs the corresponding modifications of the packet in the memory PMi. To modify a packet, the processor 40 takes control of the packet bus 10 via the gate 48. The modification addresses are deduced from the number of the selected memory and from the modification parameters. The time data at modify (PCR or LTW) are modified according to the transmission time Ts previously calculated. If PID identification fields have to be modified, the processor 40 uses the map data of the output multiplex (PSI). While the processor 40 takes control of the packet bus 10, the sequencer 44 interrupts the transfer of the packet in progress;

the processor 40 determines, as a function of the ADDS number of the selected packet memory, the starting address to be supplied to the transfer sequencer 44 for the transfer of the next packet of the OS multiplex; the processor determines this starting address so as to respect the order of entry of the packets in each packet memory;

the election parameters of the packet which came in second position in the selected memory PMi are read from the associated parameter memory ZMi and written into the working memory 50 at the corresponding address; in the absence of such a second packet, the corresponding bit BM is set to 0 in the working memory 50;

- The processor 40 calculates the transmission time Ts of the following packet and supplies it to the election circuit 42 as well as the following election order EC.

Of course, the processor 40 can also perform other functions which are not detailed here since they are not directly concerned with the present invention.

The proposed organization of the multiplexing module is well suited to the constraints imposed by the MPEG2 system standard.

The packetization modules provide the multiplexing module with information giving it the possibility of achieving an optimal distribution of the packets over time, giving it not only the ideal time of broadcast of each packet, but also the minimum time and the maximum time allowing to respect the input buffers of a decoder located downstream. The multiplexing module does not have to know the multiplexing characteristics of the sources it manages (bit rate, critical multiplexing factor). It is therefore possible to define a generic multiplexing card which covers the multiplexing aspects proper but also remultiplexing, this allowing very great flexibility.

The multiplexing processor is relieved to manage cumbersome configurations in terms of number and bit rate of elementary streams, without the need for prohibitive computing power. The multiplexing process is very systematic and can in part be implemented in very fast wired logic such as the election circuit 42.

The number m of elementary streams that can be managed is limited only by the width of the address buses of the multiplexing module. This allows great flexibility, since one can easily add or remove package modules to the multiplexing module. The device configures itself at power-up and knows how many package modules are present, and at which addresses on the packet bus and on the parameter bus it will write their data.

The parameters necessary for the election and modification of the packets are identical regardless of the type of flow that the package module manages. The multiplexing module therefore ignores the nature of the streams it multiplexes. He simply knows how many sources of transport packages are connected to him, and his work is systematic (and therefore faster). In the proposed organization, each packet from each source pending in the packet memory space has an associated zone in the parameter memory space.

A variant embodiment of the device in FIG. 1 is shown in FIG. 10. In this variant, the interface between the packaging modules C1, ..., Cn and the multiplexing module 14 includes packet memories PM1, ..., PMm, memories ZMI, ..., ZMm for receiving the parameters for electing the packets and memories YM1, ..., YMm for receiving the parameters package modification. Each package module therefore writes the modification parameters in a memory YMi also associated with the packet memory PMi, but distinct (at least as far as addressing is concerned) from the memory ZMi of the election parameters. The bus 12 which allows the multiplexing module 14 to see all of the memories ZMi as a single address space is used in this variant only for reading the election parameters. A similar bus 16 is provided between the multiplexing module 14 and the memories YMi to read the modification parameters. The YMi memories are therefore also seen as a single address space by the multiplexing module. This architecture allows the processor of the multiplexing module to carry out the modification of one or more elected packets while the election circuit selects a packet memory for a next packet of the OS output multiplex, it being observed that several packets can be elected in advance, the transmission times Ts of the packets can be anticipated. For example, while packet N leaves the output buffer, packet N + 1 can be written to the output buffer, packet N + 2 can be modified in its packet memory and packet N + 3 can be elected . By thus increasing the parallelization of operations, it is possible to adapt to even higher output flow rates.

Claims

1. Device for producing a time multiplex of digital information packets, comprising several package modules (C1, C2, ..., Cn) each receiving a digital input stream (IS1, IS2, ..., ISn) , several packet memories (PM1, PM2, ..., PMm) receiving each of the packets coming from a respective package module, and multiplexing means (14) selecting the packet memories from which the packets of the multiplex are extracting and successively transferring said packets to an output of the device, characterized in that it also comprises at least one set of parameter memories

(ZM1, ZM2, ..., ZMm) respectively associated with the packet memories, in that each packet supplied to a packet memory by a package module is associated with a set of parameters including election parameters written by said package module in the corresponding parameter memory, and in that the multiplexing means comprise processing means (40,42) connected to all of the parameter memories by a parameter bus (12) for selecting the memory of packets by analyzing the election parameters respectively associated with the first packets waiting in each of the packet memories, and transfer means (44) connected to the packet memories by a packet bus (10) and controlled by the processing means to successively extract the packets from the multiplex from the selected packet memories, the processing means selecting the packet memory from which a packet of the m ultiplex is to be extracted while the transfer means transfer a previous packet of the multiplex from a previously selected packet memory.

2. Device according to claim 1, characterized in that the set of parameters associated with a packet includes modification parameters determined by the module of package providing said packet to a packet memory, indicating whether the multiplexing means have to modify at least a determined portion of said packet.

3. Device according to claim 2, characterized in that the modification parameters associated with a packet include at least one modification indicator and a parameter giving the position of a determined portion of the packet to be modified according to the value of said indicator.

4. Device according to claim 2 or 3, characterized in that the parameters for modifying a packet are written by the package module in the same parameter memory (ZMi) as the election parameters, and in that after selecting a packet memory for extracting a packet from the multiplex, the processing means (40) read the modification parameters associated with said packet in the parameter memory (ZMi) associated with the selected packet memory, means (48) being provided for communicating the parameter bus (12) and the packet bus (10) and thus allowing the processing means (40) to modify at least a determined portion of the packet in the selected packet memory when the modification parameters read in the associated parameter memory indicate a modification to be carried out.

5. Device according to claim 2 or 3, characterized in that it comprises a first set of parameter memories (ZMi) for storing the election parameters associated with the packets present in the packet memories (PMi), connected to the means multiplexing (14) by a first parameter bus (12), and a second set of parameter memories (YMi) for storing the modification parameters associated with the packets present in the packet memories (PMi), connected to the multiplexing means (14) by a second parameter bus (16), the processing means controlling the transfer means so that a packet is transferred to the output of the device while they analyze the modification parameters of a next packet and they select a packet memory from which to extract a next packet again.

6. Device according to any one of the preceding claims, characterized in that the election parameters associated with a packet represent at least a minimum hour (Tmin) and a maximum hour (Tmax) of transmission of said packet by the means of multiplexing, and in that the processing means select the packet memory from which each packet from the multiplex is to be extracted on the basis of the time (Ts) of transmission of said packet and the election parameters associated with the first packets waiting in each of the packet memories.

7. Device according to claim 6, characterized in that the multiplexing means (14) are arranged to send a stuffing packet when the time of transmission of this packet is less than the minimum hours (Tmin) of transmission of all the first packets pending in the packet memories.

8. Device according to claim 6 or 7, characterized in that the election parameters associated with a packet further representing an ideal time (Tideal) of transmission of said packet by the multiplexing means.

9. Device according to claim 8, characterized in that the selection of a packet memory for the transmission of a packet at an hour Ts comprises the calculation of a priority coefficient for. each packet memory having at least one pending packet, this priority coefficient being taken equal to (Ts-Tideal) / (Tmax-Tideal) if Ts≥Tideal and to (Ts-Tideal) / (Tideal-Tmin) if Ts <Tideal, Tmin, Tmax and Tideal designating respectively the minimum, maximum and ideal hours of transmission of the first pending packet, the selected packet memory being the one for which the priority coefficient is maximum.

10. Device according to any one of the preceding claims, characterized in that the means processing devices include a processor (40) controlling packet transfers from the selected packet memories to the device output, and a wired election circuit (42) selecting the packet memories based on the election parameters associated with the first packets pending in each of the packet memories.

11. Device according to claim 10, characterized in that the multiplexing means comprise a memory (50) with two ports in which the processor (40) writes the parameters for electing the first packets pending in the packet memories, and wherein the election circuit (42) reads said parameters to select the packet memories.

12. Device according to any one of the preceding claims, characterized in that at least one package module comprises:

an input buffer (20) receiving the input stream;

- a detection circuit (22) connected to the output of the input buffer for detecting synchronization words of the input stream;

- a storage unit (23) successively receiving the bytes of the input stream which have been presented to the detection circuit (22);

- transfer means (32) for transferring bytes from the storage unit (23) to a packet memory (PMi); and

- a processor (26) for determining the headers of the packets constructed from the input stream on the basis of the synchronization words detected by the detection circuit (22), writing these headers in the packet memory ( PMi) and control the transfer means (32), and in that the storage unit (23) is organized as first input - first output so as to contain at all times Kk bytes of the input stream, K denoting the number of bytes in a packet of the output multiplex and k designating the minimum number of bytes in packet headers, and that the transfer of one byte from the storage unit (23) to the packet memory (PMi) is accompanied by the transfer of another byte from the detection circuit (22) to the storage unit (23), so that all the bytes of the input stream which can be introduced into a packet are presented to the detection circuit (22) before writing begins of this packet in packet memory.

13. Device according to claim 12, characterized in that the processor (26) of a package module calculates the number of bytes L of the header of a packet according to the detections of synchronization words carried out by the detection circuit (22) while the bytes of a previous packet coming from the input stream are transferred from the storage unit (23) to the packet memory (PMi), and controls the transfer means (32) to then transfer the KL bytes of the input stream to be included in said packet.

14. Device according to claim 12 or 13, characterized in that, for treating a raw elementary flow

(ES) from an audio or video encoder, the processor (26) of a package module is arranged to determine headers of a first package layer (PES) and headers of a second packetization layer (TP) on the basis of elementary stream synchronization words detected by the detection circuit (22), the packets written in the packet memory (PMi) each containing a header of the second layer, and the packets containing a header of the first layer each starting with a composite header written by the processor (26) in the packet memory (PMi) and consisting of a header of the second layer followed by said header of the first layer.

15. Device according to claim 14, characterized in that the processor (26) is arranged to determine said composite headers so that they each occupy the whole of a packet of K bytes.

16. Device according to claim 12 or 13, characterized in that to process an elementary stream packaged according to a first packetization layer (PES), the processor (26) of a packetization module is arranged to determine a header d '' a second packetization layer (TP) inserted at the start of each packet written in the packet memory (PMi) on the basis of synchronization words included in the headers of the first layer and detected by the detection circuit (22 ), the detection circuit (22) further providing the processor (26) with an indication of the number of bytes L ′ of each header of the first layer so that the processor (26) determines a header of the second layer of KL 'bytes for the packet containing this header of the first layer.

17. Device according to any one of claims 12 to 16, characterized in that the detection circuit (22) comprises a network of programmable doors.

18. Device according to claim 17, characterized in that the detection circuit (22) comprises a shift register (24) having a length of k bytes placed between the output of the input buffer (20) and the input of the storage unit (23), and a programmable detection logic (25) receiving the k bytes present in the shift register (24) and indicating to the processor (26) the detections of synchronization words.