WO1996013940A1 - Digital data packet multiplexer, in particular for digital television - Google Patents

Digital data packet multiplexer, in particular for digital television Download PDF

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Publication number
WO1996013940A1
WO1996013940A1 PCT/FR1995/001396 FR9501396W WO9613940A1 WO 1996013940 A1 WO1996013940 A1 WO 1996013940A1 FR 9501396 W FR9501396 W FR 9501396W WO 9613940 A1 WO9613940 A1 WO 9613940A1
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packet
memory
parameters
packets
processor
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PCT/FR1995/001396
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French (fr)
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Jean-Michel Masson
Frédéric GRENIER
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Matra Communication
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/24Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
    • H04J3/247ATM or packet multiplexing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television, VOD [Video On Demand]
    • H04N21/20Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a Uniform Resource Locator [URL] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H04N21/2365Multiplexing of several video streams

Abstract

A device including a plurality of packetising modules (C1, C2, ..., Cn) supplying packet memories (PM1, PM2, ..., PMm) from digital input streams (IS1, IS2, ..., ISn), and multiplexing means (14). Each packet in a packet memory is combined with selection parameters written into a related parameter memory (ZM1, ZM2, ..., ZMm) by its packetising module. The multiplexing means include processing means connected to the parameter memories via a parameter bus (12) for selecting the packet memories from which the multiplex packets are to be retrieved by analysing the respective selection parameters combined with the first packets on stand-by in each of the packet memories, and transfer means connected to the packet memories via a packet bus (10) and controlled by the processing means to retrieve a series of multiplex packets from the selected packet memories.

Description

MULTIPLEXER PACKET OF DIGITAL INFORMATION, PARTICULARLY FOR DIGITAL TELEVISION

The present invention relates to a device for producing a time multiplex of packets of digital information comprising a plurality of modules packetization each receiving an input digital stream, multiple packets memories each receiving packets from a respective packetization module, and packet multiplexing means for selecting the memories which multiplex the packets are extracted and successively transferring said packets to an output of the device.

The invention more particularly the field of digital television. It applies in particular in the framework of the standard MPEG2 system defined in the draft international standard ISO / IEC 13818-1 of the International Organization for Standardization dated 10 June 1994 (Information Technology - Generic Coding of Moving Pictures and Associated audio / Recommendation H.222.0). Reference may be made to ISO / IEC 13818-1 for information on the structure of the packets discussed in this application.

The MPEG2 system standard defines two types of digital multiplexes streams: transport stream (TS) and program stream (PS). A "program" is defined as a set of elementary streams temporally correlated, that is to say, each carrying information to be restored relative to a common time base. A program stream PS transmits one program in the form of relatively large and possibly variable length packets. The PS stream are provided to the transmission channels introduce bit errors. They are typically used to store information on disk. transport streams consist of packets belonging to one or more programs, and are used for transmission in environments that can introduce errors. transport packets (TP) have a fixed length of 188 bytes and each comprise a TP header of at least 4 bytes.

These multiplexed streams are constructed from packetized elementary streams (PES). Raw elementary streams (ES) directly from the video and audio coding are first formed into PES packets of variable length. PES streams are then redécoupés to form the TS or PS packets to be multiplexed. Currently, some coders out elementary streams in ES, and others at PES. The elementary streams can also be composed of other data that audio or video, for example, data detailing information specific to a program (PSI), data relating to conditional access to a program (ECM or EMM) ...

The role of an MPEG2 multiplexer is to receive these different elementary streams, to perform the setting or PS TS packets and the time multiplexing of these packages.

A device according to the invention may also be what is called a re-multiplexer. A re-multiplexer is a device for producing a multiplex as defined in the introduction, wherein the at least one input stream has been multiplexed upstream as PS or TS format. A re-multiplexer can be used for example for extracting a transport stream packets relating to a program and outputting another transport stream or program having only the program, to extract one or more transport stream the packets relating to one or more programs to build another transport stream, or to convert a program stream into a transport stream for transmission losses in an environment.

The MPEG2 system standard specifies in detail the constraints that a multiplexer must consider when multiplexing packets carrying different elementary streams of the signal. Indeed, in order to optimize the size of the input buffers necessary in a decoder (and therefore to reduce the price of these decoders), it is necessary to have in time a very homogeneous distribution of packets of each elementary stream. In the case of a large number of elementary streams to manage and flow rates for these flows, the labor multiplexer may require high computing power, and secondly the chosen multiplexing method may lead to multiplexes flow different output quality (in terms of distribution of packets).

An object of the present invention is to provide a device as defined in the introduction, which is flexible and efficient in order to achieve high flow rates.

A device according to the invention thus comprises memories parameters respectively associated with the packet memory. Each packet supplied to a packet memory by a packetization module is associated with a set of parameters, including election parameters, written by said packetization module in the corresponding parameter memory. multiplexing means comprise processing means connected to the memory parameters by a parameter bus to select the packet memory by analyzing the election parameters respectively associated with the first packet in the queue in each of the packet memory, and means for transfer connected to the memory packets by a packet bus and controlled by the processing means for successively reading out the packets of the multiplex from the memories of selected packets, the processing means selecting the packet memory from which a multiplex package has to extract while the transfer means transfers a previous packet from the multiplex a packet memory previously selected. Communication between modules specific packetization and multiplexing module is performed by a memory plane interface type. The packet memory on the different packetization modules are seen as particular areas of the addressable space of the multiplexing module, as well as the associated parameters memories. The data passing through the memory array are organized in the same way regardless of the type of corresponding input stream, which allows the multiplexing module to have a systematic and therefore more effective. The exchange via this interface are organized around two buses, which allows the multiplexing module to perform its tasks in parallel and not sequentially.

Other features and advantages of the present invention will become apparent in the following description of a preferred embodiment but not limited to, reference to the accompanying drawings, wherein:

- Figure 1 is an overall block diagram of a first embodiment of the invention;

- Figure 2 is a block diagram of a packetization module used in the device of Figure 1;

- Figures 3 to 5 are diagrams illustrating the operation of packetization modules according to Figure 2;

Figure 6 is a diagram of a multiplexing module used in the device of Figure 1;

- Figures 7 and 8 are graphs illustrating an example of calculation of priorities in a multiplexing module;

- Figure 9 is a diagram of a usable election circuit in the multiplexing module of FIG 6; and

- Figure 10 is a block diagram overview of a second embodiment of the invention. The device shown in Figure 1 is described below in its application to the production of an OS output multiplex having the format of a transport stream TS as defined in the MPEG2 standard. It will be understood that the device would also be applicable to produce another type of multiplex, in particular a PS Program Stream as defined in the MPEG2 standard.

The device comprises n packetization modules C1, ..., Cn, each receiving a stream of input IS1, ..., ISn. The n input streams are a total of m elementary streams. In the case of a multiplexer whose inflows are comprised of elementary streams respectively from encoders or data sources, one year = m. In the example shown in Figure 1, the IS2 flows is already multiplexed (e.g., transport stream TS), and the device is intended to take into account two elementary streams included in the multiplexed stream.

The packetization modules C1, ..., Cn deliver the transport packets TP from each of the elementary streams they receive. These transport packets are stored in buffers to access two PM1, ..., MCS. Each packet memory MPi receives packets from a packetization module. The modules packetization C2 dealing with already multiplexed streams can supply several memories PM2 packages, PM3. In the latter case, the memories PM2 packets, PM3 may conveniently be constituted by two different address areas of the same memory array.

Each packet memory MPi is associated with memory settings ZMi also two access. Whenever a packetization module writing an information packet into a packet memory PMi, it writes a further parameter set associated with this packet in the memory corresponding parameters ZMi. For playback, the memories PM1 packs, ..., MCS are connected to a common packet bus 10, and the memories of ZM1 settings ... ZMM are connected to a common parameter bus 12. These two buses are connected to a multiplexing module 14 whose role is to select the PMi memories from which the packets of the OS output multiplex are to be extracted and successively transferring the packets in question to the output of the device.

The modules packetization Cj analyze in real time the elementary streams they receive and provide the transport packets to PMis buffers. The analysis in real time of an elementary stream and the double packetized (PES layers and TP) may require a high computing power, especially for video streams that can achieve data rates of 15 Mbit / s standard resolution, or more than 100 Mbit / s in high resolution. The packetization module C1 illustrated in Figure 2 can meet these demands.

This module C1 includes an input buffer 20 receiving the input stream IS1. The output of the buffer 20, bytes of the input stream passes through a detection circuit 22 before being transmitted to a storage unit 23 of first-in-first-out (FIFO). The output of unit 23 is connected to the data input of the IMP packet memory.

The detection circuit 22 is constructed as a programmable gate array (FPGA). It is composed of a shift register 24 four-stage one byte, through which pass the bytes of the input stream before reaching the storage unit 23, and a detection logic 25 receiving the four bytes present in the stages of the register 24. the logic 25 is programmed according to the states to be detected in the input stream. The logic 25 detects the states of the input stream and informs a microprocessor 26. The processor 26 can access the memory settings ZMI by its address bus and data 28, 29. Buses 28, 29 are also connected the PMI packet memory via a tri-state gate 31. the storage unit 23 is controlled to contain at any moment 184 bytes of the input stream, and for each outgoing byte of this unit causes the input of another byte. The unit 23 could be achieved simply as a shift register 184 floors of a byte. If there is no shift register of this size can be cascaded several, or use a random access memory whose addresses for read and write are generated so as to keep a constant gap therebetween corresponding to a capacity of 184 bytes.

Depending on the states detected by the logic 25, the processor 26 provides a sequencer 32 transfers control parameters to perform the transfer byte input stream from the storage unit 23 to the IMP packet memory. These control parameters include a starting address for writing a packet data in the memory PM1, and the number of bytes to transfer from that address. The sequencer 32 comprises an address counter which is initialized to the start address value provided by the processor, and which is incremented at each byte transferred until the specified number of bytes has been transferred . This counter provides the byte write addresses in the PMI memory. If the storage unit 23 is in the form of a random access memory, the sequencer 32 also provides the read address of the byte to be transferred so as to comply entered the first protocol - first out in this memory. The sequencer supplies a signal SC which clocks the transfers to and from the unit 23, the offsets in the register 24 of the sensing uit and the byte read in the input buffer 20.

In the example shown in Figure 2, the IS1 input stream is an elementary stream (ES or PES) to packetize. The detection logic 25 is programmed to detect the sync words in the input stream. Depending on the states detected by the logic 25, the processor 26 determines the length and content of the header to place the beginning of the next transport packet to be recorded in the memory PM1. This header is determined as specified in the MPEG2 standard, the processor 26 running a training program header as described in ISO / IEC 13818-1. The length L of the header can vary between 4 bytes and k = K = 188 bytes. Thus, the ability to K - k = 184 bytes from the storage unit 23 ensures that all of the bytes of input streams may be fed into a transport packet were analyzed by the detection circuit 22 before this pack begins to be transferred from the storage unit 23 to the IMP packet memory.

Figure 3 illustrates the construction of TP transport packets by the packetization module in the case of a crude elementary stream ES from an audio encoder. In accordance with the MPEG2 standard, audio ES stream consists of fixed-length frames each starting with a header frame 35A. The header 35A contains a 12-bit sync word worth FFF in hexadecimal. The detection logic 25 of a packetization processing module an audio ES stream is therefore programmed to detect this FFF synchronization word. A PES stream constructed from such a stream ES may comprise a PES header 36 immediately before each header 35A ES. However, this packetization module when processing an audio ES stream does not explicitly through the PES stadium, but instead built directly TP transport packets. In the case shown in Figure 3, as the logic 25 does not detect the FFF synchronization word in the input stream, the processor 26 calculates a header 37a of L = 4 bytes, and controls the transfer of 188 - L = 184 bytes of the storage unit 23 to the PMI memory to form a transport packet TP. When the logic 25 detects a synchronization word for transferring a packet to the IMP memory, the processor 26 calculates the length L of the header 37b of the next packet to complete a 188-byte transport packet with the bytes of elementary stream up to the detected synchronization word. To produce a header of L length greater than 4 bytes, the CPU 26 introduces the stream or stuffing bytes management parameters in the adaptation field of the header, as specified by the MPEG2 system standard . The packet will follow the transport packet thus formed will not contain any bytes of the input stream, but only a header TP 37c and a PES header 36. It can therefore be considered that the processor 26 has determined a header composite 37c-36 L = 188 bytes and ordered transfer K - L = 0 bytes from the unit 23 under this package. The PES header 36 is calculated in accordance with MPEG2 system standard, and the length of the TP header 37c will be adapted using the adaptation field as for the previous packet.

Figure 4 is a diagram similar to that of Figure 3 in the case of a video ES stream types. According to the MPEG2 standard, a type of video ES stream includes three types of headers: the headers 35S sequence containing a 4-byte synchronization word worth 000001B3 in hexadecimal, of the headers of 35G GOP containing a 4-byte sync word worth 000001B8 in hexadecimal, and headers 35P image containing a 4-byte sync word worth 00000100 in hexadecimal. The structure of the video stream ES is such that a header 35S sequence is always followed immediately by a 35G group of pictures header or a header 35P image and a header of 35G GOP is always followed by a header 35P image. The length of about a picture video data, according to each header 35P image is variable. A PES stream constructed from such ES video stream may contain a PES header 36 before each header 35S sequence before each header 35G group that is not immediately preceded by a header sequence 35S, and before each header 35P picture that is not immediately preceded by a 35G group header. However, this packetization module when it processes a video stream ES, does not explicitly produced the corresponding PES stream, but directly TP transport packets. The insertion of headers and PES construction is essentially performed in the same manner as in the case audio described with reference to Figure 3, the detection logic 25 is programmed to detect headers of the synchronization words 35S, 35G and 35P. However, the processor 26 does not insert a PES header 36 before all headers 35P image, but only before those who are not preceded immediately by a GOP header

35G or a 35S sequence header. Similarly, the processor 26 does not fit a PES header before every GOP headers 35G, only before those who are not immediately preceded by a header 35S sequence. These different conditions can be easily identified on the basis of the synchronization words detected by the logic 25.

Figure 5 is a diagram similar to those of Figures 3 and 4 in the case of a PES audio or video input stream. The PES header 36 in each packet PES stream contains a 4-byte sync word of which the first three valent 000001 hexadecimal and the fourth is a flow identification byte. This identification byte being known in advance for a given PES stream to be treated by the packetization module can be programmed logic 25 for detecting the synchronizing words of 4 bytes of the PES stream. The division into transport packets TP is then performed by processor 26 in the same manner as in the case of Figures 3 and 4, on the basis of the PES header 36. The processor 26 does not include ES headers 35 are treated as data of the elementary stream. As in the cases of Figures 3 and 4 can be programmed processor 26 for a TP packet contains a PES header 36 does not contain data of the elementary stream. Processor 26 then need to know the length L 'of the PES header to form a packet containing a header TP 37c length L = K - L bytes followed by the PES header 36. the length L 'can be read in the PES header itself using the detection circuit 22, if the seventh byte from the beginning of the PES header does not begin with the two bits' 10 ', the PES header has a length of L' = 6 bytes; if the length L 'is read from the ninth byte from the beginning of the PES header (see document ISO / IEC 13818-1).

The advantage of forming transport packets containing a PES header 36 by keeping only those packets a header TP 37a-c and said PES header 36 is to enable scrambling of all the transport packets containing data elementary stream ES, the PES header that should not be confused.

The processor 26 writes, via the door 31, 37a-c headers and / or 36 at the appropriate positions in the packet memory PMI so as to follow the structure of the TP packet shown in Figure 3, 4 or 5. This writing can take place before the transfer of 188 - L bytes of input stream belonging to the package in question. It can also be performed later as long as the package in question is still present in the PMI memory, especially if the TP header of a packet should contain packets dependent settings later reaching the packetization modules (by example of image slicing parameters in the case of a video ES stream).

When the input stream is a multiplexed transport stream, the detection logic 25 is programmed for detecting the synchronization byte indicating the start of a transport packet. This synchronization byte is 47 hex. Processor 26 mark the packet input time when the synchronization byte is detected. Analyzing the following bytes of the header construction through the detection circuit 22, the processor 26 may read the 13 bits of the packet identification (PID field) and determine if it contains optional time field PCR type or LTW. The presence of PCR or LTW fields is indicated by the determined position of bits in the TP header (see ISO / IEC 13818-1). The position of the PCR field is fixed, but that of LTW field may vary so that the position of this field is indicated, if necessary, to the processor 26 by the circuit 22.

Knowing the PID parameter identification of the package, which characterizes the elementary stream from which it came, the processor 26 may perform a filtering operation to do t ransférer in the packet memory that packets of the elementary streams to keep in the multiplex Release. To remove a package, the processor 26 controls the transfer sequencer 32 that it writes the packet in the packet memory to a garbage address where it will never be read.

If the packetization module is associated with several memories PM2 packages, PM3, these memories are grouped in the same address space, and the write addresses generated by the sequencer 32 transfers are determined on the basis of PID identification parameter provided to the processor 26 by the detecting circuit 22 so as to obtain the operating first in - first out in each of the memories PM2 packets, PM3. We can thus move towards different memories of elementary streams packets keep in a multiplexed stream input.

The packetization module shown in Figure 2 has flexibility. It is easily adaptable to a wide variety of input stream, simply by programming the detection logic 25 and processor 26. This module is particularly suitable for a modular architecture of the device. In the case of a PE type of input stream, it can simultaneously achieve both packetizing phases (PES and TP) by means of a single processor, the PES header is regarded as an extension the TP header. It is also suitable for TS or PS input stream, in re-multiplexing applications.

The development of a packet is performed in parallel with the transfer of the previous packet data to the memory MPi, allowing to process large input rates. The transfer is entrusted to a separate sequencer, which will release the single processor packetization module for other treatments to perform.

Another task performed by the processor 26 is calculating the parameters associated with the packets and writing in the memory of ZMi parameters. These parameters include parameters for returning to the multiplexing module 14 to select the packet memories for the transfer of packets to the output of the device. Thus, some of the tasks are transported in the packetization modules customarily performed the multiplexing module. The additional CPU load 26 is however small enough to have no significant impact on the choice of the processor that is anyway needed for packetization.

To approach an optimal time distribution output, it is necessary to know:

- the packages may get out immediately and the maximum delay that can be attributed to them.

- packages that will come out soon and the time which we can anticipate their issue.

A solution to give the multiplexing module 14 visibility on the broadcast information is to ask packetization modules to associate each packet written in the buffer PMi three election parameters each corresponding to a time expressed in relation to a common time base for packetization and multiplexing modules. These three parameters are the minimum time Tmin, the maximum time Tmax and the ideal time of packet emission Tidal which they are associated.

Each processor 26 managing an elementary stream thus defines a time window for the transmission of each package created, and is free to adapt the width of the window to the nature of the flow it manages. In addition, to help the multiplexing module 14 in its task and to allow it to generate a stream quality, it sets an ideal position of the packet in her window. The management parameters Tmin, Tmax, and Tidal is specific for each type of input stream.

In the case where the input stream is an elementary stream (ES, PES or data), the minimum time Tmin emission is calculated by adding a lag time Tl to the time Te input data of the packet in the input buffer 20 of the packetization module, and the difference Tmax - Tmin between the maximum time and the minimum transmission time is calculated according to the type of elementary stream and the flow rate of this stream. If the source of the elementary stream has a steady flow, the input time Te is simply deducted by the processor 26 from the time of passage of the data by the detection circuit 22. If the source of the elementary stream has a flow rate gusty, the input time can be found from a flow of information received from the encoder upstream or read from the stream. Tl latency is a programmable time for delaying the emission of certain flows compared to others. The window width Tmax - Tmin is less taken for temporal flows, including video streams, as flows without restraint precise retransmission, such as flow EMM conditional access data. The difference Tmax - Tmin is also a decreasing function of the rate of the elementary stream.

In the case of a multiplexed input stream type transport stream, the Tmin minimum time of retransmission of a packet is calculated according to the packet input time Te in the module and a time Tl latency as in the previous case, and also according to the strategy that had been adopted the previous multiplexer. This strategy is shown in the fields LTW headers TP stream or into descriptor fields, these fields can be read by the processor 26 via the detection circuit 22. The calculated minimum time Tmin is for example delayed with respect to Te + Tl time corresponding to the window offset (LTW_offset) read in the stream. In the case of a multiplexed input stream, Tmax maximum retransmission time is calculated based on the flow type. For most elementary streams of a transport stream, the difference Tmax -Tmin is taken equal to 4 ms. However, for special cases, this difference can be increased to alleviate the constraints of the multiplexing module.

The ideal time of transmission of a packet is obtained based on the multiplexing strategy for the elementary stream containing the package. Tidal this time can be defined by an offset relative to the minimum time Tmin, this offset being fixed or proportional to the width Tmax - Tmin of the transmission window. A strategy "early" is one hour Tidal relatively close to the minimum time Tmin. This strategy promotes the encoder or multiplexer upstream, which can have a smaller output buffer. A strategy "later" is one hour Tidal relatively far from the minimum time Tmin. This strategy encourages the decoder or the remultiplexer located downstream in the sense that its input buffer may be reduced in size. There are a whole range between strategies "early" and "late".

In a typical embodiment, the election of parameters stored in the parameter memories are ZMi the ideal time coded Tidal transmission of 20 bits, the difference Tidal - Tmin coded on 15 bits, and the difference Tmax - Tidal coded on 15 bits, expressed in relation to a reference clock at 90 kHz. These settings are stored at an address associated with the address of the associated packet in the memory MPi.

The parameters associated with a package and stored in the memories of ZMi parameters further include changing settings allowing the multiplexing module 14 to update the packet header according to its transmission time when necessary . These changing parameters, for example:

- bits indicating the presence or absence detected by the logic 25 of a PCR type of field or LTW type field, which can not be updated only when the exact release time of packet is known, requires very precise time references. In the case of a PCR type of field whose position is fixed relative to the beginning of the packet, just a bit to indicate if such a field is present in the package. In the case of a LTW type field, whose position can vary, the modification parameters further indicate the position of this field in the packet;

- size of the data portion (payload) of the packet.

This information is useful in the case where the multiplexing module 14 further performs a scrambling of the packet;

- identification PID parameter of the packet. This information, useful in re-multiplexing applications, allows the multiplexing module 14 whether to change this (if the same PID parameter identification is assigned to several elementary streams contained in the input stream).

An architecture of the multiplexer module 14 is shown in the diagram of Figure 6. This module comprises firstly a microprocessor 40 and a returning circuit 42 which process the data contained in the memories of ZMi parameters, and other share a transfer sequencer 44 which controls the packet memories PMi packet transfers to the output buffer 46 of the device. It is understood that the multiplexing module 14 may further include other elements, for example to confuse the packets transferred before registering them in the output buffer.

The multiplexing module 14 further comprises a memory PM0 additional packets and a memory ZM0 associated parameters. The PM0 memory contains specific information packets to the programs carried by the output multiplex (PSI), which specify, among other PID identification parameters of flow of each program (see Section 2.4.4 of ISO / IEC 13818- 1). The PSI packets are written to the memory PM0 by a not shown source also belonging to the multiplexing module 14. This source also written in the memory of election ZM0 parameters associated with these packages: Tmin, Tmax, Tidal. The time constraints of PSI packets are not very severe, the time window of issuance of these packages can be made relatively large.

From the perspective of the multiplexing module 14, the memory packages PM0, PM1, ..., MCS are considered a single address space. Similarly, memories ZM0 parameters BA1, ... ZMM are considered to play as a single address space. 6 shows the data bus 10D and 10A bus address included in the packet bus 10. These two buses 10A, 10D are respectively connected to address and data inputs of each of memories PMi packets. The addresses on the bus 10A are generated by the transfer sequencer 44 under the control of processor 40. The data bus 10D is also connected to the input of output buffer 46 where the data writing is controlled by the sequencer 44 .

Figure 6 also shows the data bus 12D and 12A bus address controlled by the processor 40 included in the parameter bus 12. These two buses 12A, 12D are respectively connected to address and data inputs of each memories ZMi parameters. The packet bus 10 and parameter 12 are interconnected by a tri-state gate 48 allows the hand 40 to take the processor to the packet bus 10. To direct the sequencer 44 the transfer of a transport packet of 188 bytes to the output buffer, the processor 40 has a starting address on the address bus 12A. This start address is transmitted to the bus 10A by door 48, and the sequencer address counter 44 is initialized to the value of said starting address and is incremented until all 188 bytes of the packet are transferred.

The bus addresses 10A, 12A are wide enough that packets memories PMi and ZMi parameters are seen as a unique address space by processor 40. A 24 bit address bus suitable for a multiplexer or remultiplexer large capacity (m≤128 for example). To gain in output speed, bus 10D data 12D may be 16-bit bus, transferring two bytes at a time.

The sequencer 44 is separated from the processor 40 to enable the processor 40 and the circuit 42 to perform the processing relating to transmission of a packet in the multiplex while the previous packet of the multiplex is being transferred under the control sequencer. This allows the multiplexing module 14 to adapt to the large transmission rate required by the MPEG2 standard.

Applications made before the transfer of a package include:

- selecting the packet memory PMi wherein this pack will be read and determining the starting address to be supplied to the sequencer 44 to ensure the transfer of this packet;

- analysis of changing parameters related to elected package and possible changes in relevant fields.

The processor 40 receives the equipment located downstream of the device cadenceuent a CK signal of the output multiplex. The processor 40 calculates the transmission time Ts of the next packet from this signal CK.

The choice of memory where packages will be retrieved the next packet is performed based on the time Ts and emission of Tmin election parameters, Tmax, Tidal present in the top positions of memory ZMi parameters, c that is to say the election parameters associated with the first packets waiting in each memory MPi packets.

Annex 1 submitted to the f in the present description provides an example of election in C language algorithm used to select the memory where packages extract the packets of the multiplex. In the notation of Appendix 1, nb_sources corresponds to the number of connectable memory packets to the packet bus 10 (nb_ sources = m + 1 when the entire capacity of the multiplexer module 14 is used), valid_TP_flag [] is a array of length nb_sources consisting of Boolean variables such as valid_TP_flag [current_channel] is true if a packet memory PMi is actually connected to the current_channel position and if the packet memory contains at least one awaiting transfer packet, the Tmin [] array Tmax [] and Tidal [] contain the election parameters of the first packets waiting in each packet memory, current_priority is a priority coefficient calculated for the first packet in the queue in the PM memory (current_channel), and is the elected_TP_priority priority coefficient maximized by the election algorithm corresponding to the package chosen content in the PM memory (elected_TP_channel).

A -1 priority coefficient is assigned to a padding packet stored, for example, in the PM0 memory at an address which is assigned a memory number -1. This padding packet is selected by default if no packet memory contains a packet having reached its minimum time Tmin show. No packets can normally be issued after its maximum time Tmax, given that the device is dimensioned so that the sum of the input flow rates is less than the flow rate of the output stream.

Figures 7 and 8 show the variations of the priority coefficient of a packet having a given transmission window [Tmin, Tmax] according to Ts emission time in the case of a strategy "early" Figure 7 ) and in the case of a strategy "late" (8 ,. we see that for a given transmission time and the same windows, the algorithm of election favors flows for which we defined a strategy "soon ".

The election algorithm presented in Appendix 1 can be implemented by the processor 40 while the previous packet of the multiplex is being transferred. In this case, the processor 40 must perform readings in memory ZMi parameters and execute the algorithm. These tasks take a significant time to the processor. Therefore, in high speed applications, it is preferred to use a separate voting circuit 42 as shown in Figure 6. A wired circuit 42 allows the election faster than a processor, and relieves processor 40 of the corresponding calculations.

The multiplexing module 14 comprises a dual-port memory 50 connected to the parameter bus 12 to provide useful parameters to the election system 42. The election parameters Tidal, Tmax - Tidal and Tidal - Tmin associated with the first packet in the queue in each PMi packet memory are read by the processor 40 in the memory corresponding ZMi parameters and are written in the memory 50 to an address ADD equal to the packet memory number. The processor 40 also written in the memory 50 of the BM bit corresponding to boolean variables valid_TP_flag previously defined: GS = 0 if no packet memory is connected to the position corresponding to the address ADD or if the packet memory connected to the position corresponding to the address ADD contains no packet in the queue at the time concerned.

9 is a diagram of an election wired circuit. This circuit 42 includes a register 52 in which the value of the next issue of time Ts is written by the processor 40. A sequencer 54 supervises the operations performed by the circuit 42 in response to a received CE election order of the processor 40 . the sequencer 54 first initializes the value -1 (default padding packet) the contents of two registers 56, 58 for containing one ADDS address corresponding to the selected packet memory and the other coefficient corresponding priority PRIO. The sequencer 54 then generates read commands in the work memory 50. At each read cycle, the sequencer 54 increments by one an address counter providing the read address, so as to sequentially read the BM parameters , Tidal, Tmax - Tidal and Tidal - Tmin for the various possible addresses. The election circuit 42 comprises a subtractor 60 receiving on its positive input the transmission time Ts after the register 52 and at its negative input the target time Tidal end of the memory 50. The sign bit of the output of the subtractor 60 controls a multiplexer 62 having an input (positive sign) is the parameter Tmax - Tidal from the memory 50 and the other input (negative sign) receives the Tidal parameter - Tmin from the memory 50. a divider 64 computes the quotient of the output of the subtractor 60 and the output of the multiplexer 62. the priority coefficient of the current packet and supplied by the divider 64 is sent to an input of a comparator 66 whose other input receives the content of register 58. an aND gate 68 receives, firstly, the BM bit for the current packet, and secondly the comparison bit produced by the comparator 66. This comparison bit is 1 if the priority coefficient calculating the current packet is gran of that part of the register 58 and 0 otherwise. For purposes of synchronization, a shift register 70 delays the BM bit sent to the AND gate 68 a number of cycles equal to that required for calculations made by the elements 60 to 66. The ADD address generated by the sequencer 54 is sent to the register 56 after passing through a shift register 72 which delays the same number of cycles. The priority coefficient produced by the divider 64 is sent to the register 58. The clock CCK cycle is provided by the sequencer 54 to the registers 56-58 for updating, but this update is performed that provided that the output of the AND gate 68 is 1.

The circuit 42 described above can perform the election algorithm of Schedule 1 in a very short time. Once the election system swept all possible addresses, the address corresponding to the ADDS PMis memory where the next packet will be available to read in the register 56. The processor 40 can then read the register 56 by the intermediate settings bus 12.

Once the processor 40 and knows the packet memory MPi selected, it does the following:

the modification parameters of the selected packet are read from the memory ZMi associated parameters;

- the processor 40 analyzes these modification parameters and if necessary performs the corresponding modifications of the IMP packet in memory. To edit a packet, the processor 40 takes hold of the packet bus 10 via gate 48. amendment addresses are deducted from the selected memory number and changing settings. Temporal data to change (or PCR LTW) are based on the previously calculated transmission time Ts. If a change of PID identification fields, the processor 40 uses the mapping data of the output multiplex (PSI). While the processor 40 takes hold of the packet bus 10, the sequencer 44 interrupts the transfer of the current packet;

- the processor 40 determines, based on the ADDS number of the selected packet memory, the starting address to provide the transfer sequencer 44 to transfer the next OS of the multiplex packet; the processor determines the starting address in order to respect the packets of the input order in each packet memory;

- the package election parameters coming in the second position in the selected memory PMi are read from the parameter memory associated ZMi and recorded in the work memory 50 at the corresponding address; in the absence of such a second packet, the corresponding BM bit is set to 0 in the work memory 50;

- the processor 40 calculates the transmission time Ts of the next packet and supplies it to the returning circuit 42 as well as the following order of EC election.

Of course, the processor 40 can still perform other functions not detailed here because not directly affected by this invention.

The proposed organization of the multiplexing module is well suited to the constraints imposed by the MPEG2 system standard.

The packetization modules provide the multiplexing module information giving the opportunity to achieve an optimal distribution of packages in time, giving him not only the ideal time to release of each package, but the minimum time and maximum time to comply with the input buffer of a downstream decoder. The multiplexing module does not have to know the multiplexing characteristics of the sources that it manages (flow, critical multiplexing). We can define a generic multiplexing card that covers aspects multiplexing themselves but also re-multiplexing, allowing this very important flexibility.

The multiplexing processor is relieved to reach manage heavy configurations in terms of number and debit elementary streams without the need of a crippling power calculation. The multiplexing process is very systematic and can partly be implemented in a very fast wired logic as the election circuit 42.

The number m of elementary streams that can manage is limited only by the width of the address bus multiplexing module. This allows great flexibility because you can easily add or remove modules packetization multiplexing module. The device is configured to power and knows how packetization modules are present, and what addresses on the bus packet and the bus parameters it will write data.

The parameters for the election and the modification packages are the same regardless of the type of flow that manages the packetization module. The multiplexing module does not know the nature of that stream multiplex. He just knows how to transport packets sources connected to it, and his work is systematic (and therefore faster). In the proposed organization, each packet of each source waiting in the packet memory has an area associated in the parameter memory.

Figure 1 a device of the alternative embodiment is shown in Figure 10. In this variant, the interface between the packetization modules Cl, ..., Cn and the multiplexing module 14 includes memory PM1 packets. .., MCS, the ZMI memories ... ZMM to receive the packets of election parameters and YM1 memories ... YMM to receive packets changing settings. Each packetization module therefore written modification parameters in a memory YMi also associated with the packet memory MPi but separate (at least as regards addressing) the election ZMi memory settings. The bus 12 which allows the multiplexing module 14 of the all ZMi remembered as a unique address space is only used in this variant that a reading of election parameters. A similar bus 16 is provided between the multiplexing module 14 and YMi memories to read the changing parameters. The YMi memories are therefore also seen as a unique address space by multiplexing module. This architecture allows the processor of the multiplexing module to carry out the modification of one or more packets elected while the returning circuit selects a packet memory for a next packet of the OS output multiplex, it being observed that several packets may be pre elected, packets Ts issuance of hours that can be anticipated. For example, as the packet N out of the output buffer, the packet N + 1 can be written into the output buffer, the packet N + 2 can be changed in the packet memory and the N packet + 3 may be elected . By increasing the parallelization of operations, we can adjust to output rates even higher.

Figure imgf000028_0001

Claims

1. Device for producing a time multiplex of packets of digital information comprising a plurality of packetization modules (C1, C2, ..., Cn) each receiving an input digital stream (IS1, IS2, ..., ISn) several packet memories (PM1, PM2, ..., MCS) each receiving packets from a respective packetization module, and multiplexing means (14) selecting packets from the memory from which the packets of the multiplex are extracting and transferring said packets successively to an outlet of the device, characterized in that it further comprises at least one set of memory parameters
(ZM1, ZM2, ..., Zmm) respectively associated with the packet memory, in that each packet included in a packet memory by a packetization module is associated with a set of parameters including election parameters written by said packetization module in the corresponding parameter memory, and in that the multiplexing means comprises processing means (40,42) connected to the memory set parameters by a bus parameters (12) for selecting the memory packets by analyzing the election parameters respectively associated with the first packet in the queue in each of the packet memory, and transfer means (44) connected to the packet memory by a packet bus (10) and controlled by the processing means for successively extracting the packets of the multiplex from the memories of selected packets, the processing means selecting the packet memory from which a packet of m ultiplex is to be extracted while the transfer means transfers a previous packet from the multiplex a packet memory previously selected.
2. Device according to Claim 1, characterized in that the parameter set associated with a packet includes modification of parameters determined by the packetization module providing said packet to a packet memory, indicating whether the multiplexing means have to modify the least one defined portion of said package.
3. Device according to claim 2, characterized in that the modifying parameters associated with a packet comprises at least one change flag and a parameter giving the position of a particular portion of the packet to change according to the value of said indicator.
4. Device according to claim 2 or 3, characterized in that the modification of a packet parameters are written by the packetization module in the same memory parameters (ZMi) that the election parameters, and in that after selecting a packet memory for extracting a packet from the multiplex processing means (40) reads the packet associated with said modification parameters in the parameter memory (ZMi) associated with the selected packet memory, the means (48) being provided for communicating the parameter bus (12) and the packet bus (10) and thereby enable the processing means (40) to modify at least one predetermined portion of the packet in the selected packet buffer when the modification parameters read from the memory associated parameters indicate a change to be made.
5. Device according to claim 2 or 3, characterized in that it comprises a first set of memory parameters (ZMi) for storing the election parameters associated with the packets present in the packet memories (PMi), connected to means multiplexing (14) by a first bus parameters (12), and a second set of memory parameters (YMi) for storing the modification parameters associated with the packets present in the packet memories (PMi), connected to the multiplexing means (14) by a second bus parameters (16), the processing means controlling the transfer means to a packet to be transferred to the output of the device while they analyze the modification parameters of a next packet and that they select a packet memory from which to extract a package according to yet.
6. Device according to any one of the preceding claims, characterized in that the election parameters associated with a packet representing at least a minimum time (Tmin) and a maximum time (Tmax) of transmission of said packet by means of multiplexing, and in that the processing means selects the packet memory from which to extract each packet of the multiplex based on the time (Ts) transmitting said packet and returning parameters associated with the first packet waiting in each packet memories.
7. Device according to claim 6, characterized in that the multiplexing means (14) are arranged to emit a padding packet when the transmission time of the packet is less than the minimum times (Tmin) Issue all the first packets waiting in the packet memory.
8. Device according to claim 6 or 7, characterized in that the election parameters associated with a representative package further includes a target time (Tidal) transmitting said packet by the multiplexing means.
9. Device according to claim 8, characterized in that selecting a packet memory for transmission of a packet at a time Ts comprises calculating a priority coefficient. each packet memory having at least one packet in the queue, the priority coefficient being set equal to (Ts-Tidal) / (Tmax-Tidal) if Ts≥Tidéal and (Ts-Tidal) / (Tidal-Tmin) if Ts <Tidal, Tmin, Tmax, and Tidal respectively denoting minimum hours, and maximum ideal of the first packet transmitting waiting, the selected packet memory being that for which the priority coefficient is maximum.
10. Apparatus according to any preceding claim, characterized in that the processing means comprise a processor (40) controlling packet transfers packets memories selected to the output of the device, and a wired circuit election ( 42) selecting the packet-based memories of election parameters associated with the first packet in the queue in each of the packet memory.
11. Device according to claim 10, characterized in that the multiplexing means comprise a memory (50) dual port wherein the processor (40) writes the election parameters of the first packets waiting in the packet memory, and wherein the returning circuit (42) reads said parameters to select the packet memories.
12. Device according to any one of the preceding claims, characterized in that at least a packetization module comprises:
an input buffer (20) receiving the input stream;
- a detection circuit (22) connected to the output of the input buffer for detecting word synchronization of the input stream;
- a storage unit (23) successively receiving the bytes of the input stream that were presented to the detection circuit (22);
- transfer means (32) for transferring bytes of the storage unit (23) towards a packet memory (PMi); and
- a processor (26) for determining the headers packets constructed from input stream on the basis of the synchronization words detected by the detection circuit (22), write the headers in the packet memory ( PMi) and controlling the transfer means (32), and in that the storage unit (23) is organized first in - first out so as to contain at any moment Kk bytes of the input stream, where K denotes the number of bytes of a packet of the output multiplex, and k is the number of minimum byte packet headers, and that the transfer of one byte of the storage unit (23) to the memory packets (PMi) is accompanied by the transfer of another byte of the detection circuit (22) to the storage unit (23), so that all the bytes of the input stream may be introduced into a package are submitted to the detection circuit (22) before beginning the writing of this packet in the packet memory.
13. Device according to claim 12, characterized in that the processor (26) of a packetization module calculates the number of bytes L from the header of a packet according to sync word detections made by the detection circuit (22) while the bytes of a previous packet from the input stream are transferred from the storage unit (23) to the packet memory (PMi), and controls the transfer means (32) then transfer the KL bytes of input stream to include in said packet.
14. Device according to claim 12 or 13, characterized in that, for treating a crude elementary stream
(ES) from an audio or video encoder, the processor (26) of a packetization module is arranged to determine the headers of a first layer packetization (PES) headers and a second layer packetization (TP) on the basis of the elementary stream synchronization words detected by the detection circuit (22), the packets written in the packet memory (PMi), each containing a header of the second layer, and packets containing a header of the first layer each beginning with a composite header written by the processor (26) in the packet memory (PMi) and constituted by a header of the second layer followed by said header of the first layer.
15. Device according to claim 14, characterized in that the processor (26) is arranged to determine said composite headers so that they each occupy the whole of a K-byte packet.
16. Device according to claim 12 or 13, characterized in that for processing a packetized elementary stream in a first layer packetization (PES), the processor (26) of a packetization module is arranged to determine a header of a second layer packetization (TP) inserted at the beginning of each packet written in the packet memory (PMI) on the basis of sync words included in the headers of the first layer and detected by the detection circuit (22 ), the detection circuit (22) further providing to the processor (26) indicating the number of bytes L 'of each header of the first layer so that the processor (26) determines a header of the second layer KL bytes for the packet containing the header of the first layer.
17. Device according to any one of claims 12 to 16, characterized in that the detection circuit (22) comprises a field programmable gate array.
18. Device according to claim 17, characterized in that the detection circuit (22) comprises a shift register (24) having a k-byte length located between the output of the input buffer (20) and the input of the storage unit (23), and a programmable detection logic (25) receiving the k bytes present in the shift register (24) and indicating to the processor (26) the synchronization words detections.
PCT/FR1995/001396 1994-10-26 1995-10-23 Digital data packet multiplexer, in particular for digital television WO1996013940A1 (en)

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FR9412815A FR2726413B1 (en) 1994-10-26 1994-10-26 Multiplexer packets of digital information, including digital television
FR94/12815 1994-10-26

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