WO1996013928A1

WO1996013928A1 - A device for allowing to make a toll-free telephone call

Info

Publication number: WO1996013928A1
Application number: PCT/BR1995/000049
Authority: WO
Inventors: Rogério Leandro VIEIRA; Luiz Roberto Peixoto
Original assignee: Fg - Comércio De Produtos E Serviços De Telefonia Ltda.
Priority date: 1994-10-26
Filing date: 1995-10-26
Publication date: 1996-05-09

Abstract

A device for allowing the user to make a toll-free telephone call, comprised of a circuit (8) for checking whether a telephone call has been put through and a predetermined time interval has elapsed since the linkage thereof, as well as for making the talking mode of said call unavailable after said predetermined time interval has been completed; a serial communications circuit (9) which acts as an interface between a user (2 and 6) and the device (1) itself; at least a circuit (10 and 11) for transmitting a pre-recorded publicity message to each of the users (2 and 6) participating in the call; and a central processing circuit (7) for managing all circuits (8, 9, 10, 11) in the device (1).

Description

"A DEVICE FOR ALLOWING TO MAKE A TOLL-FREE TELEPHONE CALL"

Description of the Invention The invention is related to a device specifically designed for allowing the user to make a toll-free telephone call from a fixed and/or mobile public terminal station in a telecommunications system of the type comprised of fixed and/or mobile public terminal stations. In the state of the art, there is a wide range of different telecommunications systems comprised of fixed and/or mobile public terminal stations commonly called public telephones, through which someone who is not provided with a terminal station at home or is at a public place can make a telephone call.

In such a conventional telecommunications system, the task of connecting two or more public and/or private terminal stations is carried out by telephone switching exchanges wherein said terminal stations are connected to said exchanges. When the connection between terminal stations belonging to distinct telephone exchanges is made, interconnecting routes are used among telephone exchanges.

Telephone calls made from public terminal stations are charged through two distinct ways, that is, the user who makes the call shall pay same by inserting coins or using credit instruments such as tokens, cards and the like, through a specially formed slot to this end on the terminal cover; or the user makes a collect call, which shall be paid by the recipient. However, there are frequently cases where someone interested in making a telephone call is not carrying coins or any credit instruments required therefor, and it is not possible or desirable for him to make a collect call.

Such a situation is particularly true in the case of public terminal stations presently available in economically unstable countries with high inflation rates.

Indeed, in most of said countries, in view of the multiplicity of coins having different values, shapes and dimensions, the telecommunications service companies have decided to replace coins with tokens or credit cards whose cost is consistent with the current telephone rate.

In other words, in such countries there may be situations wherein even if the user has the money required for making a call he cannot make it because he is not carrying tokens or credit cards or he can go nowhere around to buy same due to different reasons. Such a situation may become extremely serious when the user cannot make an urgent call such as for asking for medical help or the like.

Thus, one of the objects of this invention is to provide a device for allowing a user to make a toll-free telephone call wherein the user can make said toll-free telephone call from a fixed and/or public terminal station.

Another object of this invention is to provide a device for allowing a user to make a toll-free telephone call that may bring benefits to the telephone service companies, such as a reduction in the number of damages due to trickery; an equalization of traffic among the several installed public terminal stations; a reduction in terminal stations operating costs due to the non-use of tokens, coins or cards that depend inter alia on manufacture, collection and/or distribution.

Another object of this invention is to provide a device for allowing a user to make e toll-free telephone call without the intervention of a telephonist or operator.

Still another object of this invention is to provide a device for allowing a user to make a toll-free telephone call which can be installed without the need of any change in the existing systems at the telephone exchange and/or terminal stations. And finally another object of this invention is to provide a device for allowing a user to make a toll-free telephone call wherein said call can be paid by an advertiser that transmits a publicity message to the user, which message has a programmable period of time that starts at the moment the recipient answers the call. These and other objects of this invention can be accomplished by the use of a device for allowing a user to make a toll-free telephone call which is comprised of a circuit for checking whether a telephone call has been put through and a predetermined time interval has elapsed since the linkage thereof, as well as for making the talking mode of said call unavailable after said predetermined time interval has been completed; a serial communications circuit which acts as an interface between a user and the device itself; at least a circuit for transmitting a pre-recorded publicity message to each of the users participating in the call; and a central processing circuit for managing all circuits in the device. With the above-mentioned device for allowing the user to make a toll-free telephone call installed along interconnecting routes between switching exchanges of a telecommunications system, in the event the user is not provided with means for paying for the desired call, it is possible that same can be paid by an advertiser who, in turn, shall transmit a publicity message to the user, which message has a programmable period of time that starts at the moment the recipient answers the call.

In order to access the device for allowing the toll-free call, the user shall add a numerical prefix to the terminal station number he is calling. The corresponding switching exchange is already programmed to direct all calls started with the access prefix dialed to the interconnection routes provided with said device.

Considering that all switching exchanges in a telecommunications system allow for the programming of different classifications for terminal stations connected thereto, public terminal stations shall have a permission for accessing routes provided with said device included in the classification thereof. However, it is noted that at the discretion of the telecommunications system operating company even the other private terminal stations of telephone exchanges can be programmed for accessing routes provided with said device during less heavy periods, for example, from ten p.m. to six a.m. Yet, in view of the flexible programming of telephone exchanges in the state of the art, there are several options for controlling the access to the device. One of them can be defined by an access of private terminal stations controlled by the generation and suppression of interconnecting routes; terminal stations dedicated to toll-free calls where it would not be required to dial the above-mentioned prefix could also be defined. In the latter case, the access to the device can be determined by the classification programmed for the terminal station. Thus, any and every call made from one of such terminal stations shall be directly directed to a route provided with the device, the dialing of the access prefix being not required. This invention shall be described below in more details for the sake of exemplification, without any limiting intention, with reference to the accompanying drawings, wherein:

Figure 1 is a block diagram of the device for allowing the user to make a toll-free telephone call, which shall be called device FG afterwards;

Figure 2 is a block diagram showing the installation mode of the device if order to put through telephone calls between two terminal stations of distinct telephone exchanges and two terminal stations of the same telephone exchange; Figures 3 through 6 show one of the constructive options for an answering and occupancy interface circuit and the other interface circuits, with the interconnecting route among telephone exchanges;

Figures 7 through 10 show one of the constructive options for A and B messages generating circuits; Figure 11 shows one of the constructive options for the serial communication port circuit; and

Figures 12 through 18 show one of the constructive options for the central processing circuit or the service managing unit of the relevant device. According to the figures, the device for allowing the user to make a toll-free telephone call is comprised of a plurality of circuits 7, 8, 9, 10, 11 96/13928 6 PC-7B-R95/00049

having independent functions installed along a route interconnecting switching exchanges in a telecommunications system 4, between a source switching exchange 2 and a target switching exchange 6, as shown in Figures 1 and 2. For the sake of detailing, an output junctor 3 is illustrated as an interface element between a source switching exchange 2 and interconnecting route 4, whereas the interface element between a target switching exchange 6 and interconnecting route 4 is an input junctor 5.

Said interface elements defined by junctors 3 and 5 make part of a telecommunications systems of the type comprising public terminal stations connected to telephone switching exchanges.

The device for allowing the user to make a toll-free telephone call, or device FG 1, is basically comprised of a service managing unit 7, an answering and occupancy interface circuit 8, a serial communication port 9, an A-message generating device 10 and a B-message generating device 11, all of them joined in an enclosure which is serially coupled to interconnecting route 4 and can be physically positioned at any point along same.

Said service managing unit 7 is a central processing unit which concentrates the intelligent features of device 1. Said unit 7 is responsible for the process sequencing and decision making based on the information provided by the other circuits.

The aim of answering and occupancy interface circuit 8 is to continuously monitor the direction and intensity or the electrical current present at the electrical circuit on interconnecting route 4. Other functions of this device comprise the simulated presence of an input junctor means connected to output junctor means 3; the simulated presence of an output junctor means connected to input junctor means 5; and the insertion of publicity messages provided by circuits 10 and 11 in both sound circulation directions along interconnecting route 4. When the recipient answers the call, the polarity of the voltage present at the target exchange output connecting wires is inverted. Said inversion is detected by answering and occupancy interface circuit in such a way that service managing unit 7 starts then counting the time elapsed in the call. According to Figure 1, device FG 1 makes use of a B-message generating circuit 11 which is actuated by service managing unit 7, simultaneously with A-message generating circuit 10. While A-message generating circuit 10 is connected for answering the user who made the telephone call, B-message generator circuit 11 is connected to the telephone call recipient, that is, transmits messages to the call recipient. Thus, it is not required to use the same message for both users. By the time the two messages are finished, the users are then provided with a programmable time interval for conversation. As no credit charge command is issued, the call is normally out through. By the end of the period designated to conversation, device FG 1 emits an occupied tone for both users through message generating circuits 10 and 11, thus blocking the communication between same.

When the end of telephone call is detected, device FG 1 assumes the waiting mode for a new call. The aim of serial communication port 9 is to allow the configuration of the operating features of device FG 1. The port sends information to managing unit 7 and receives information therefrom, thus making it possible to have an interaction between device FG 1 and an operator.

As shown in Figure 1, device FG 1 is installed along an interconnecting route represented by numbers 3, 4 and 5, between telephone exchanges 2 and 6. Device FG 1 is accessed by programming the route of calls using device FG 1. Thus, the service is accessed by dialing a prefix added to the telephone number of the recipient station.

Access to the service can also be controlled by classifying the station where the call was made. Thus, during heavier periods only devices having a classification equivalent to that of public terminals should access the service. During less heavy periods, for example, from 10 p.m. to six a.m., all terminals could be programmed for accessing the service. Access to private terminal stations can also be controlled through the generation and suppression of interconnecting routes. In the case of terminal stations dedicated to toll-free calls, it may not be required to dial the above-mentioned prefix. Access to device FG 1 in this case can be determined by the classification programmed for the terminal station. In Figure 2, it can be seen that device FG 1 is placed between two telephone switching exchanges 2 and 6, thus intercepting the telephone call using the toll-free call service. In order to be able to use this service, the user shall add a numerical prefix to the number of the recipient terminal station. Optionally, as described above, access to device FG 1 can be achieved by classifying the terminal station or directing the route. Thus, once telephone switching exchanges 2 and 6 are programmed for that aim, they can direct the call connection to a route provided with device FG 1 for allowing the user to make a toll-free telephone call.

Still in Figure 2, we have the situation of a call between two terminal stations from the same telephone exchange 2, said call being sent to a route provided with device FG 1 but, instead of reaching another telephone exchange 6, it returns to telephone exchange 2 itself, where it can reach the recipient. Figures 3 through 6 show the electrical diagram of answering and occupancy interface circuit 8 and the other interface circuits with the interconnecting route between telephone exchanges 2 and 6.

Figure 3 shows details of the circuit which performs the interface function between an input junctor 5 and two wires. Modules Dl, D5, D7, D8, D9 and the photoemitting diodes of OPl and OP4 make out a rectifying bridge circuit responsible for the detection of the electrical current circulation direction with respect to the voltage offered by input junctor 5 of switching exchanges 2 and 6. Thus, if target switching exchange 6 offers regular polarity potentials, that is, the call was not answered, the phototransistor of OP4 shall be saturated, thus activating line signal NORMAL which is active at 0 volts. If target switching exchange 6 offers inverted polarity potentials, that is, the call was answered, the phototransistor of OP4 shall be saturated, thus activating line signal INVERT which is active at 0 volts. Resistors R3 and R4 supply the polarization for the collector of phototransistors of OPl and OP4. Figure 3 still shows modules Rl, R2, OP2, OP3, D3, D4, R5, Tl, T2,

T3, R6, C3 and R7 which perform the active charge function for the circuit comprising wires ADEST and BDEST from input junctor 5 of target exchange 6. This active charge circuit is commanded by logical signals LOW and HIGH, both active at 0 volts, and shall always have a very high impedance for alternated signals in view of the use of C3. When both signals are deactivated, the photo transistors of OP2 and OP3 are cut off and the active charge is off. This situation is equivalent to the remote blocking of input junctor 5 of target exchange 6. When signal HIGH is active, the charge has an impedance of approximately 18 Kohms for input junctor 5, thus indicating circuit present and in rest mode. When signal LOW is activated together with HIGH, the active charge circuit starts draining a constant current, assuming there are small variations in the total connection impedance of approximately 30 mA, which indicates occupation of input junctor 5 and target exchange 6.

Through Cl and C2, the audio present in the line connected to input junctor 5 is deactivated and sent to the audio switching and inserting circuit, signals AOUT and BOUT.

In Figure 4, we have the electrical circuit of the audio switching and inserting step. Diodes D10 and Dll provide a low impedance path for high amplitude transients from the interface circuit to output junctor 3 of source exchange 2, and diodes D12 and D13 perform the same function for connection to input junctor 5 of target exchange 6. Transformers TR1 and TR2 provide the galvanic insulation between the audio circuit of device FG 1 and the connections to source exchange 2 and target exchange 6. Integrated circuit CIl comprises a set of three analog interting switches responsible for switching the audio path in both directions for insertion of messages amplified by amplifiers CI2A and CI2B. The switching is activated by signal COMUT, active at 0 volts, in such a way that the audio path between TRl and TR2 is interrupted and signal AUDIOA is sent to TR2 and signal AUDIOB is sent to TRl. By deactivating signal COMUT (5 volts), the audio path between TRl and TR2 is restored. Modules TP1 and TP2 adjust the audio level to be inserted in both directions. Resistors R8, R9, RIO and Rll provide the polarity on amplifiers CI2A and CI2B. Capacitors C4 and C5 deactivate the DC components of signals AUDIOA and AUDIOB.

Figure 5 shows the electrical scheme of the interface circuit for connection to output junctor 3 of source exchange 2. In this case, the interface simulates the action of input junctor 5 of target exchange 6, thus offering potential through wires AORIG and BORING connected to output junctor 3 cited above. Similarly to the circuit in Figure 3, capacitors C6 and C7 deactivate the audio signal and send same to the audio switching and inserting circuit through AIN and BIN. In the circuit of Figure 5 we have two more active charge circuits comprising T4, T6, T8, R16, R18, R19, C9 and T5, T7, T9, R14, R15, R20, C8, which are always ready to supply a constant current of approximately 30 mA to the line connected to output junctor 3. As shown in Figure 3, these active charge circuits show a very high impedance to audio signals and maintain a stable current if the impedance of the connection is kept within certain limits. OP9 and R17 detect the high current circulation in the connection, which indicates occupation of the junctor by source exchange 2. This indication is sent to CPU 7 through line ATEND, active at 0 volts. Since the interface of Figure 5 shall simulate an input junctor circuit 5, it shall be responsible for providing normal potential when in the rest mode, and indicates inverted potential when the call is answered by target exchange 6. This condition is governed by signals CINVERT and CNORNAL, both active at 0 volts. When CNORMAL is active, the light emitting diodes of OP6 and

OP7 shall conduct, thus bringing about the saturation of the corresponding phototransistors and the provision of positive potential on line BORIG and negative potential on line AORIG, through D20 and D19, respectively. If, however, CINVERT is active, the light emitting diodes of OP5 and OP8 shall conduct, thus forcing the corresponding phototransistors to saturate and providing positive potential on line AORIG and negative potential on line BORIG, which indicates that the recipient has answered the call. With both signals deactivated, the provision of electrical potentials to the output junctor is terminated, which is equivalent to the remote blocking thereof.

Figure 6 shows the electrical circuit for connecting interface answering and occupancy circuit 8 to CPU 7, in which connection signals DO to D7 make out the data busbar where the information provided by interface circuit 8 shall be read and the command therefor shall be written. For such, octal latch CI5 shall store the data present at the busbar when selective signals IO2 and IOWR from CPU 7 are active, and tri-state buffers CI3A and CI3B shall provide the information from lines NORMAL, INVERT and ATEND in the data busbar, as well as a fixed test and recognition standard in the bits odd D4 to D7 when they are selected the signals IORD and 102 from CPU 7. Modules CI4A and CI4B combine the enabling signals for the correct actuation of buffers and latches.

The electrical circuits of A-message and B-message generators 10 and 11 are shown in Figures 7 through 10. More particularly, Figure 7 shows the time-based generating circuit for both message generating circuits 10 and 11. Modules XI, Rl, R2, Cl and CI1A through CI1D generate the 2,048 MHz basic clock signal. Said signal, besides being supplied to the rest of the generating circuits after being inverted by CUE, is supplied to CI2 and CI3, which are two asynchronous binary counters. The outputs of these two counters are sent to a decodifying circuit CI4 responsible for the generation of the signal for enabling the digital/analog conversion of circuits generating FSR messages that is inverted by CIlF.

In Figure 8 we have the digital/analog converters of message generators 10 and 11 and the audio pre-amplifying circuits. In addition, since CPU 7 shall provide the PCM codified audio signal through 8 bit words, one word for each output, two serializers for feeding the converters are used for they shall receive the serial signals. Modules CI5 and CI8 are PCM30 converters, regulation A, which capture one by one all 8 bits that make out the PCM digitized audio sample supplied by CI7 and CI10 after receiving the FSR active signal. These latter ones, in their turn, receive the two 8 bit words through busbar AUDO-AUD15 from the generating circuit interface with CPU 7. The capture of the words shall also be governed by signal FSR and rated by the 2 MHz clock signal. The audio pre-amplifying circuits are comprised of the following assemblies: C2, TP1, CI6, C3, C4, R3 and C5, TP2, CI9, C6, C7, R4. In order that CPU 7 can supply the digitized audio at a constant rate and synchronized for the audio generating circuits, use is made of an interruption generating circuit as described in Figure 9.

In this circuit, C8 and R5 assure that flip-flop CI13A shall be in the reset condition when the equipment is turned on, in such a way that NAND port CI11A shall have its output set to 5 volts. This port can only activate signal INTO, thus causing the CPU to be stopped when flip-flop CI13A is put into set condition through AUDO and by activating INTWR. From that moment on, when flip-flop CI12A is put into set condition by output of flip-flop CI12B, CPU 7 is stopped and shall serve message generating circuits 10 and 11, thus supplying a no digitized audio sample. Flip-flop CI12B activates only flip-flop CI12A when there is a ramp rise in the signal FSR refused, that is, by the end of a digital/analog conversation. In order that both flip-flops return to the rest mode, CPU 7 when serving the interruption shall firstly read the state of flip-flops CI12A and CI13B. By doing so, by the end of the reading and consequent rise of signal ERD (enabling the reading of flip-flops), the interruption circuit gets into the reset mode thus becoming ready to capture another end of digital/analog conversation cycle and stop CPU 7 once again. Figure 10 shows the electrical diagram of the interface between the audio generating circuits and CPU 7. There, modules CI15 and CI17 are two octal latches designed to retain the two PCM codified 8 bit audio samples supplied by CPU 7 when signals 103, IOWR are active and address line A12 is at logical level 1. This combination causes output pin 13 of CI14D to be switched, thus provoking the storage of the data present in data busbar DO-D15 through the actuation of CI14C; similarly, when signals 103, IORD are activated and line A12 is at logical level 1, output pin 8 of CI16C switches to logical level zero, thus activating signal ERD and enabling buffer CI18A to supply signals INTRDO through INTRD3 to the busbar. As already mentioned, this operation puts the interruption generating circuit into the rest mode and ready to a new activation by the end of another digital/analog conversation cycle. In addition, CI16A, CI14A and CI14B are responsible for the activation of signal INTWR so that it may be possible to enable or disable the interruption generating circuit from the programming of CI13A in Figure 9 and the activation of latches CI15 and CI17 through CI14C. It should be noted that said latches are activated either for writing the interruption enabling command or for storing PCM samples. Thus, the PCM samples writing operation shall always be the last to be carried out before a digital/analog conversion cycle in order to avoid loss of data.

Figure 11 shows the electrical diagram of the circuit of serial communication port 9. In this diagram, module C16 performs all functions designed for the serial communication interface itself between device FG 1 and an external operator. It is an integrated circuit 8251 for controlling synchronous/asynchronous serial communication. CI2 and CI3 are circuits for adapting electrical levels between the control circuit and external line RS232-C, whereas CI1A, CUB and CI3A detect the activation of signals IOWR, IO1 and IORD, thus enabling CI6 for a reading or writing cycle. They shall also enable and select the direction for the data flow through CI5 which is a data transceptor for the data busbar of CPU 7. Modules C17A, CIlC and CUD detect the occurrence of any event requiring the intervention of CPU 7 at serial communication port 9 and then activate signal INTl, causing a hardware interruption at CPU 7.

Figures 12 through 17 show and make out the electrical diagram of the service managing UCO 7 of device FG 1.

In Figure 12, the CPU 7 core is comprised of UlO and U9, wherein UIO is a 32 bit microprocessor (80386DX) which effectively controls the data processing at CPU 7, defining the data flow sequence within device FG 1 and in the communication with the external world through serial communication port 9 or answering and occupancy interface 8. U9 is the controller of peripherals, timer and controller of direct access to the memory (82380). With the help of the decodifying circuit comprised of U1A, U1B, U1C, U2A, U2B, U3A and U4A, control circuit U9 detects the access to different blocks controlled by CPU 7, input and output ports and distinct memory regions, generating waiting cycles for UIO in such a way that less speedy devices can be served thereby.

These waiting cycles are ordered through signal READYO which is also combined with signal REAYO through U11A for composing signal READY, sent to UIO. Signal READO is generated by dynamic RAM memory controlling circuit. U5 is a TTL compatible clock generator to sent to U9, UIO, U6A and the rest of CPU 7 the signal for rating its processing, in this case 32 MHz. U6 divides this signal by two, thus generating another rating signal synchronized with the internal clock of UIO, U7A, Dl, R2, R3, Cl and Si, being responsible for the generation of the reset mode of CPU 7 during the energization of the device or through manual actuation of SI. This reset condition is supplied to U8 which carries out the synchronism thereof with signal CLK2 and is then sent to U9 for its own reset condition and for supplying a synchronous reset condition for UIO.

XI, C2, R4, U4B, U4C and U4D supply the basic clock to serial communication port 9, this clock being sent to U9, where it shall be divided by a rate defined by software in such a way that signal SERCLK can be generated, which signal shall then be sent to serial communication port 9, thus making it possible to operate at different speeds (19,200 bps, 14,400 bps, 9,600 bps, etc). Figure 13 shows the circuit for selecting memory and I/O (input- output) wherein, through U12, enabling signals are generated for different memory areas of the CPU: DRAM for enabling dynamic RAM memory bank; FLASH0 for enabling the first "FLASHFILE" type non¬ volatile memory bank; FLASH 1 for enabling the second "FLASHFILE" type memory bank; and EPROM for enabling memory bank EPROM. This last signal shall even activate line BS16 of UIO for switching the microprocessor operation for 16 bit busbar. Ports U13A, U13B and U13D shall define the access to the upper or lower pair of EPROM's of the CPU, according to the state of the addressing signal A17. Ports U14B and U14C generate the signals for enabling the selection of the EPROM's connected to upper or lower eight bits of the data busbar. Ports U13C, U14A and U4F generate signals IORD (reading of I/O devices) and IOWR (written on I/O devices). Port U16 supplies the signals for enabling I/O devices connected to the CPU: IOl for selecting serial communication port 9; IO2 for selecting answering and occupancy interface 8; IO3 for selecting message generating circuits 10, 11. Ports U2C, U2D, U15A, 96/13928 18 --

U17A, U17B, U17C, UllB and U15C shall generate ancillary addressing signals AO and Al.

Figure 14 shows the electrical scheme of EPROM type non-volatile memory bank of CPU 7. When the CPU 7 is reset, the CPU 7 program starts being performed from the contents thereof. U18 and U20 supply the contents to be sent to the eight lower bits of the data busbar. U19 and U21 supply the contents to be sent to the eight upper bits of the data busbar. In addition, U18 and U19 make out the part of the bank located in addresses FFFCOOOO to FFFDFFFF, and U20 and U20 are located on top of the addressable memory (addresses FFFEOOOO to FFFFFFFF).

The electrical diagram of the dynamic RAM memory controlling circuit is shown in Figure 15. The simultaneous enabling of signals ADS and DRAM is detected by U22A and triggers the flip-flop comprising U17D and U3B. This flip-flop not only supplies signal READYO that determines the waiting of CPU 7 for the end of access to RAM memory , but also enables the counter formed by U27 to begin the sequence of events for generating the other signals. It is also through U22A that signal RAS generated by the flip-flop formed by U26A and U24C is enabled. U23B shall then detect the moment for enabling signals MUX and CAS, U25A shall detect the moment for desabling signals CAS, RAS and WE, and U23A shall detect the moment for desabling signal READYO and finish the access cycle.

In addition, U14D, U22B, U22C and U22D generate signals CASO, CAS1, CAS2 and CAS3 according to the state of lines BEO, BE1, BE2 and BE3 generated by UIO. Signal WE (enabling the writing in RAM memory) shall only be released by activation of RAS, and is generated by U24B. For the occurrence of refresh cycles of RTM memories, U15D and U24D detect the ordering thereof through signals REF (generated by U9) and HLDA (generated by UIO). Thus, signal RAS is enabled without the need to begin a new full access cycle. Figure 16 shows an electrical diagram of the dynamic RAM memory bank of CPU 7. Modules U29, U30, U31 and U32 are the memories themselves, whereas U34, U37 and U38 are transceptors of busbars designed to connect the data lines of RAM memories to the data busbar of CPU 7. They shall be enabled by signal RAS, and the direction of their transmission shall be defined by signal WE. Modules U28, U33 and U36 perform the multiplexing of the address busbar and shall be switched by signal MUX.

The electrical diagram of "FLASHFILE" type non-volatile memory bank is shown in Figure 17. Modules U40, U41, U42 and U43 are the "FLASHFILE" devices characterized by being electrically turned off in 64 Kbytes blocks. Each of these integrated circuits is provided with 16 storage blocks, amounting to a total of 1 Mbyte of inner space. Since said memories do not lose their contents, unless they are purposely erased, they shall be used for storing the messages to be used by device FG 1. Module U15F shall generate the writing pulse, and U39A, U39B, U39C and U39D are responsible for the selection of each memory according to the state of signals BEO, BEl, BE2 and BE3 concurrently with the activation of signal FLASHO. This electrical circuit describes the first "FLASHFILE" memory bank. Figure 18 shows the electrical diagram of the second

"FLASHFILE" memory bank, wherein the only difference with respect to the first bank is the utilization of signal FLASH 1 for enabling the selection to same.

Although this invention has been described and illustrated with relation to its utilization at a public terminal station, it should be understood that there are no restrictions to the utilization of the device for allowing the user to make a toll-free telephone call in private terminal stations located at homes and/or offices, provided that the access to connection routes provided with device FG 1 is programmed by said terminal stations at telephone switching exchanges 2 and 6. It should also be emphasized the fact that, though the presently embodiment of the invention has been described with relation to the interconnection between said two telephone switching exchanges 2 and 6 provided with input junctor 5 and output junctor 3 and two wires, it should be understood that there are no restrictions to the utilization of device FG 1 through telephone switching exchanges provided with connection routes to four wires or PCM link, for instance. So that this can be possible, the adaptation of the answering and occupancy interface 8 to each case in particular shall suffice. It should also be understood that the same procedure for releasing calls between several types of equipment such as videotext terminals, call through videophones, fac¬ simile transmission, transmission of data in general, among others, can be used.

After the best mode for presently practicing this invention has been described and shown, several changes and variations in the realization thereof shall be immediately apparent to those skilled in the art who may introduce same as well. Thus, it is understood that this invention is not restricted to the presently practical embodiments for its realization that have been shown and described and that said changes and variations shall be considered to be within the spirit and scope of the invention.

Claims

-Claims

1. A device for allowing to make a toll-free telephone call, wherein said device is comprised of a circuit (8) for checking whether a telephone call has been completed and a predetermined time interval has elapsed since the linkage thereof, as well as for making the talking mode of said call unavailable after said predetermined time interval has been completed; a serial communications circuit (9) which acts as an interface between a user (2 and 6) and the device (1) itself; at least a circuit (10 and 11) for transmitting a pre-recorded publicity message to each of the users (2 and 6) participating in the call; and a central processing circuit (7) for managing all circuits (8, 9, 10, 11) of the device (1).

2. A device for allowing to make a toll-free telephone call according to claim 1, wherein it is further comprised of a plurality of circuits (7, 8, 9, 10, 11) having independent functions installed along a route interconnecting switching exchanges in a telecommunications system (4), between a source switching exchange (2) and a target switching exchange (6), wherein it is accessed through a numerical prefix added to the number of the recipient terminal station.

3. A device for allowing to make a toll-free telephone call according to claim 1, wherein the interface element between a source switching exchange (2) and interconnecting route (4) is defined by an output junctor (3), whereas the interface element between a target switching exchange (6) and interconnecting route (4) is defined by an input junctor (5).

4. A device for allowing to make a toll-free telephone call according to claim 3, wherein the interface elements defined by junctors (3 and 5) are integral with a telecommunications system of the type comprising public terminal stations connected to telephone switching exchanges.

5. A device for allowing to make a toll-free telephone call according to claim 1, wherein it is comprised of a service managing unit (7), an answering and occupancy interface circuit (8), a serial communications port (9), an A-message generating circuit (10) and a B-message generating circuit (11), all of them joined in an enclosure that is serially coupled to the circuit in interconnecting route (4) and can be physically positioned at any point along same.

6. A device for allowing to make a toll-free telephone call according to claim 5, wherein service managing unit (7) is a central processing unit which concentrates the intelligent features of device (1), said unit (7) being responsible for the process sequencing and decision making based on the information provided by the other circuits.

7. A device for allowing to make a toll-free telephone call according to claim 5, wherein the aim of the answering and occupancy interface circuit (8) is to continuously monitor the direction and intensity of the electrical current present in the electrical circuit on interconnecting route (4); the additional functions thereof being the simulated presence of an input junctor means connected to output junctor means (3); the simulated presence of an output junctor means connected to input junctor means (5); and the insertion of publicity messages provided by circuits (10 and 11) in both sound circulation directions along interconnecting route (4).

8. A device for allowing to make a toll-free telephone call according to claim 7, wherein, when the recipient answers the call, the polarity of the voltage present at the target exchange output connecting wires is inverted, said inversion being detected by answering and occupancy interface circuit (8) in such a way that service managing unit (7) starts then counting the time elapsed in the call.

9. A device for allowing to make a toll-free telephone call according to claim 5, wherein the aim of serial communication port (9) is to allow the configuration of the operating features of device FG (1), wherein said port sends information to managing unit (7) and receives information therefrom, thus making it possible to have an interaction between device FG (1) and an operator.