WO1995019067B1 - A digitally controlled first order jitter attenuator using a digital frequency synthesizer - Google Patents
A digitally controlled first order jitter attenuator using a digital frequency synthesizerInfo
- Publication number
- WO1995019067B1 WO1995019067B1 PCT/US1994/014892 US9414892W WO9519067B1 WO 1995019067 B1 WO1995019067 B1 WO 1995019067B1 US 9414892 W US9414892 W US 9414892W WO 9519067 B1 WO9519067 B1 WO 9519067B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- clock signal
- phase
- generating
- counter
- Prior art date
Links
Abstract
A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.
Claims
1. A circuit for attenuating phase jitter on an incoming signal, comprising: (a) a phase detector for generating digital control signals representing a phase difference between the incoming signal and a clock signal, the digital control signals comprising a direction signal for indicating a polarity of the phase difference and a magnitude signal for indicating a magnitude of the phase difference; and
(b) a frequency synthesizer, coupled to the phase detector, for generating the clock signal at one of a plurality of selectable frequencies in response to the direction and magnitude signals, wherein frequency synthesizer comprises means for initializing a loadable counter with a starting value determined from the magnitude signal from the phase detector, means for incrementing the loadable counter using the clock signal, means for generating an adjustment signal when the loadable counter overflows, and means for controlling the frequency of the clock signal in response to the adjustment signal from the loadable counter and the direction signal from the phase detector.
2. The circuit set forth in claim 1, wherein the phase detector comprises: an up/down counter for determining the phase relationship between the incoming signal and the clock signal and for producing the output signal proportional thereto; and means, coupled to the up/down counter, for incrementing and decrementing the up/down counter when the incoming signal is out of phase with the incoming signal.
3. The circuit as set forth in claim 2, wherein the phase detector further comprises limiter means, coupled to the up/down counter, for disabling the up/down counter to prevent rollover when a count therein reaches a range boundary.
4. The circuit as set forth in claim 1, wherein the frequency synthesizer means comprises means for generating the clock signal at one of a plurality of selectable frequencies.
5. The circuit as set forth in claim 4, wherein the circuit has a selectable bandwidth BW :
BW = Dw
(2 * π * B) wherein Dw is the pull range per step of the frequency synthesizer means and B is a multiplier value for the clock signal as compared to the incoming signal .
6. A jitter attenuation circuit, comprising:
(a) a digital phase detector for determining a phase difference between an incoming signal and a clock signal and for generating output signals proportional to the phase difference, wherein the output signals indicate both a direction and a magnitude of frequency change required to eliminate the phase difference; and
(b) a digitally controlled frequency synthesizer, coupled to the digital phase detector, for generating the clock signal in response to the direction and magnitude signals from the phase detector, wherein the frequency synthesizer comprises means for initializing a loadable counter with a starting value determined from the magnitude signal from the phase detector, means for incrementing the loadable counter using the clock signal, means for generating an adjustment signal when the loadable counter overflows, and means for controlling the frequency of the clock signal in response to the adjustment signal from the loadable counter and the direction signal from the phase detector.
7. The jitter attenuation circuit as set forth in claim 6, wherein the phase detector comprises: an up/down counter for determining the phase relationship between the incoming signal and the clock signal and for producing the output signal proportional thereto; and means, coupled to the up/down counter, for incrementing and decrementing the up/down counter when the incoming signal is out of phase with the incoming signal .
8. The jitter attenuation circuit as set forth in claim 7, wherein the phase detector further comprises limiter means, coupled to the up/down counter, for disabling the up/down counter to prevent rollover when a count therein reaches a range boundary.
9. The jitter attenuation circuit as set forth in claim 6, wherein the frequency synthesizer means comprises means for generating the clock signal at one of a plurality of selectable frequencies.
10. The jitter attenuation circuit as set forth in claim 9, wherein the jitter attenuator has a selectable bandwidth BW :
BW = Dw
{2 * π * B) wherein Dw is the pull range per step of the frequency synthesizer means and B is a multiplier value for the clock signal as compared to the incoming signal.
11. A method for attenuating phase jitter on an incoming signal, comprising the steps of:
(a) generating digital control signals representing a phase difference between the incoming signal and a clock signal, wherein the digital control signals are comprised of a direction signal for indicating a polarity of the phase difference and a magnitude signal for indicating a magnitude of the phase difference; and
(b) generating the clock signal at one of a plurality of selectable frequencies in response to the digital control signals, the generating step further comprising the steps of generating the clock signal according to the direction and magnitude signals, wherein the generating step comprises the steps of loading a counter with a starting value determined by the magnitude signal, incrementing the counter using the clock signal, generating an adjustment signal when the counter overflows, and controlling the frequency of the output clock signal using the adjustment signal from the counter and the direction signal from the phase detector.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE69405016A DE69405016D1 (en) | 1994-01-04 | 1994-12-30 | DIGITALLY CONTROLLED JITTER DAMPING DEVICE WITH DIGITAL FREQUENCY SYNTHETIZER |
| DE69405016T DE69405016T4 (en) | 1994-01-04 | 1994-12-30 | DIGITALLY CONTROLLED JITTER DAMPING DEVICE WITH DIGITAL FREQUENCY SYNTHETIZER |
| EP95905468A EP0738437B1 (en) | 1994-01-04 | 1994-12-30 | A digitally controlled first order jitter attenuator using a digital frequency synthesizer |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/177,172 US5493243A (en) | 1994-01-04 | 1994-01-04 | Digitally controlled first order jitter attentuator using a digital frequency synthesizer |
| US177,172 | 1994-01-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1995019067A1 WO1995019067A1 (en) | 1995-07-13 |
| WO1995019067B1 true WO1995019067B1 (en) | 1995-08-17 |
Family
ID=22647493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1994/014892 WO1995019067A1 (en) | 1994-01-04 | 1994-12-30 | A digitally controlled first order jitter attenuator using a digital frequency synthesizer |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5493243A (en) |
| EP (1) | EP0738437B1 (en) |
| CA (1) | CA2180466A1 (en) |
| DE (2) | DE69405016D1 (en) |
| IL (1) | IL112252A (en) |
| WO (1) | WO1995019067A1 (en) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5502750A (en) * | 1994-06-15 | 1996-03-26 | Pericom Semiconductor Corp. | Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network |
| JP3358335B2 (en) * | 1994-11-04 | 2002-12-16 | 富士通株式会社 | Clock signal regeneration circuit and load capacitance control circuit of voltage controlled oscillator |
| US5757652A (en) * | 1995-12-21 | 1998-05-26 | Tektronix, Inc. | Electrical signal jitter and wander measurement system and method |
| JPH1022822A (en) * | 1996-07-05 | 1998-01-23 | Sony Corp | Digital pll circuit |
| US5754437A (en) * | 1996-09-10 | 1998-05-19 | Tektronix, Inc. | Phase measurement apparatus and method |
| DE19802001C1 (en) * | 1998-01-20 | 1999-09-02 | Siemens Ag | Digitally controlled circuit for reducing the phase modulation of a signal |
| US5977805A (en) * | 1998-01-21 | 1999-11-02 | Atmel Corporation | Frequency synthesis circuit tuned by digital words |
| US6140852A (en) * | 1998-11-09 | 2000-10-31 | Lucent Technologies, Inc. | Digital phase-locked loop with pulse controlled charge pump |
| US6535567B1 (en) | 1998-12-03 | 2003-03-18 | Level One Communications, Inc. | Method and apparatus for suppression of jitter in data transmission systems |
| WO2000035094A1 (en) * | 1998-12-07 | 2000-06-15 | Broadcom Corporation | Low jitter high phase resolution pll-based timing recovery system |
| US6711227B1 (en) * | 1999-02-05 | 2004-03-23 | Broadcom Corporation | Synchronizing method and apparatus |
| EP1149482B1 (en) * | 1999-02-05 | 2006-09-06 | Broadcom Corporation | Synchronizing method |
| US6950484B1 (en) * | 2000-05-12 | 2005-09-27 | Cypress Semiconductor Corp. | Linearized digital phase-locked loop method |
| US6934731B1 (en) | 2000-05-25 | 2005-08-23 | Broadband Innovations, Inc. | Rational frequency synthesizers employing digital commutators |
| US6351165B1 (en) | 2000-08-21 | 2002-02-26 | Exar Corporation | Digital jitter attenuator using an accumulated count of phase differences |
| US6333651B1 (en) * | 2000-12-01 | 2001-12-25 | Exar Corporation | Second order digital jitter attenuator |
| US7079615B2 (en) * | 2001-11-20 | 2006-07-18 | Hewlett-Packard Development Company, L.P. | Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop |
| US7142042B1 (en) * | 2003-08-29 | 2006-11-28 | National Semiconductor Corporation | Nulled error amplifier |
| CN1697324B (en) * | 2004-05-10 | 2010-04-07 | 华为技术有限公司 | Method and device for redlization of debouncing for transmission signal |
| US7227402B2 (en) * | 2004-08-23 | 2007-06-05 | Micron Technology, Inc. | System and method for controlling input buffer biasing current |
| US7826581B1 (en) | 2004-10-05 | 2010-11-02 | Cypress Semiconductor Corporation | Linearized digital phase-locked loop method for maintaining end of packet time linearity |
| US7583948B2 (en) * | 2005-04-28 | 2009-09-01 | Kabushiki Kaisha Toshiba | Time constant automatic adjusting circuit, filter circuit system, and method of automatically adjusting time constant |
| US7276952B2 (en) * | 2005-10-28 | 2007-10-02 | Hewlett-Packard Development Company, L.P. | Clock signal generation using digital frequency synthesizer |
| US8284884B2 (en) * | 2006-06-23 | 2012-10-09 | Mediatek Inc. | Method of frequency search for DCO and decoder using the same |
| US8018950B2 (en) * | 2008-03-17 | 2011-09-13 | Wi-Lan, Inc. | Systems and methods for distributing GPS clock to communications devices |
| US7889012B2 (en) * | 2008-05-06 | 2011-02-15 | Hittite Microwave Corporation | System and method for cycle slip prevention in a frequency synthesizer |
Family Cites Families (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL6702110A (en) * | 1967-02-11 | 1968-08-12 | ||
| US3579122A (en) * | 1969-12-23 | 1971-05-18 | Nasa | Digital filter for reducing sampling jitter in digital control systems |
| BE786798A (en) * | 1971-07-29 | 1973-01-29 | Int Standard Electric Corp | LOCK-IN-PHASE LOOP FOR MIC SIGNAL DEMULTIPLEXER |
| US3931585A (en) * | 1974-06-17 | 1976-01-06 | Navidyne Corporation | Phase comparison systems employing improved phaselock loop apparatus |
| US4129748A (en) * | 1975-09-10 | 1978-12-12 | Idr, Inc. | Phase locked loop for providing continuous clock phase correction |
| US4091335A (en) * | 1976-12-13 | 1978-05-23 | Texas Instruments Incorporated | Phase locked loop using current controlled ring oscillator |
| US4270183A (en) * | 1977-02-11 | 1981-05-26 | Lockheed Aircraft Corp. | Data dejittering apparatus |
| US4242639A (en) * | 1978-09-05 | 1980-12-30 | Ncr Corporation | Digital phase lock circuit |
| US4360788A (en) * | 1980-07-14 | 1982-11-23 | John Fluke Mfg. Co., Inc. | Phase-locked loop frequency synthesizer |
| US4490688A (en) * | 1981-04-06 | 1984-12-25 | Motorola, Inc. | Digital and analog phase detector for a frequency synthesizer |
| US4563657A (en) * | 1982-03-15 | 1986-01-07 | Codex Corporation | Frequency synthesizer and digital phase lock loop |
| US4565976A (en) * | 1983-08-05 | 1986-01-21 | Advanced Micro Devices, Inc. | Interruptable voltage-controlled oscillator and phase-locked loop using same |
| US4617679A (en) * | 1983-09-20 | 1986-10-14 | Nec Electronics U.S.A., Inc. | Digital phase lock loop circuit |
| US4539531A (en) * | 1983-09-26 | 1985-09-03 | Northern Telecom Limited | Phase locked loop variable oscillator with switched capacitors |
| US4584695A (en) * | 1983-11-09 | 1986-04-22 | National Semiconductor Corporation | Digital PLL decoder |
| US4633488A (en) * | 1984-11-13 | 1986-12-30 | Digital Equipment Corporation | Phase-locked loop for MFM data recording |
| JPH0752838B2 (en) * | 1985-03-20 | 1995-06-05 | 株式会社日立製作所 | Integrated circuit |
| JPS6315530A (en) * | 1986-07-08 | 1988-01-22 | Sumitomo Electric Ind Ltd | Digital phase locked loop |
| US4712223A (en) * | 1986-10-09 | 1987-12-08 | Rockwell International Corporation | Linear all-digital phase locked loop |
| US4733197A (en) * | 1987-02-19 | 1988-03-22 | Northern Telecom Limited | Extended range phaselocked loop |
| US4941156A (en) * | 1987-05-19 | 1990-07-10 | Crystal Semiconductor | Linear jitter attenuator |
| US4805198A (en) * | 1987-05-19 | 1989-02-14 | Crystal Semiconductor Corporation | Clock multiplier/jitter attenuator |
| US4862485A (en) * | 1987-10-14 | 1989-08-29 | National Semiconductor Corporation | Quotient phase-shift processor for digital phase-locked-loops |
| US4855683A (en) * | 1987-11-18 | 1989-08-08 | Bell Communications Research, Inc. | Digital phase locked loop with bounded jitter |
| JPH01296733A (en) * | 1988-05-25 | 1989-11-30 | Toshiba Corp | Digital phase synchronizing circuit |
| US5059924A (en) * | 1988-11-07 | 1991-10-22 | Level One Communications, Inc. | Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider |
| SE462823B (en) * | 1989-01-16 | 1990-09-03 | Ericsson Telefon Ab L M | PROCEDURE AND DEVICE FOR AUTOMATIC FUSING IN A FIXED LOOP |
| US4972442A (en) * | 1989-04-27 | 1990-11-20 | Northern Telecom Limited | Phase-locked loop clock |
| US5077529A (en) * | 1989-07-19 | 1991-12-31 | Level One Communications, Inc. | Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter |
| US5008637A (en) * | 1989-11-15 | 1991-04-16 | Level One Communications, Inc. | Fully integrated charge pump phase locked loop |
| US5181228A (en) * | 1990-10-12 | 1993-01-19 | Level One Communications, Inc. | System and method for phase equalization |
| US5068628A (en) * | 1990-11-13 | 1991-11-26 | Level One Communications, Inc. | Digitally controlled timing recovery loop |
| US5159291A (en) * | 1990-11-13 | 1992-10-27 | Level One Communications, Inc. | Digitally controlled timing recovery loop with low intrinsic jitter and high jitter tolerance |
| US5079519A (en) * | 1991-02-14 | 1992-01-07 | Notorola, Inc. | Digital phase lock loop for a gate array |
| US5057794A (en) * | 1991-02-26 | 1991-10-15 | Level One Communications, Inc. | Phase-locked loop with pattern controlled bandwidth circuit |
| US5313503A (en) * | 1992-06-25 | 1994-05-17 | International Business Machines Corporation | Programmable high speed digital phase locked loop |
| US5317283A (en) * | 1993-06-08 | 1994-05-31 | Nokia Mobile Phones, Ltd. | Method to reduce noise in PLL frequency synthesis |
-
1994
- 1994-01-04 US US08/177,172 patent/US5493243A/en not_active Expired - Lifetime
- 1994-12-30 DE DE69405016A patent/DE69405016D1/en not_active Expired - Fee Related
- 1994-12-30 WO PCT/US1994/014892 patent/WO1995019067A1/en active IP Right Grant
- 1994-12-30 CA CA002180466A patent/CA2180466A1/en not_active Abandoned
- 1994-12-30 EP EP95905468A patent/EP0738437B1/en not_active Expired - Lifetime
- 1994-12-30 DE DE69405016T patent/DE69405016T4/en not_active Expired - Lifetime
-
1995
- 1995-01-04 IL IL11225295A patent/IL112252A/en not_active IP Right Cessation
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