WO1995012288B1 - A two-part synchronization scheme for digital video decoders - Google Patents
A two-part synchronization scheme for digital video decodersInfo
- Publication number
- WO1995012288B1 WO1995012288B1 PCT/US1994/011883 US9411883W WO9512288B1 WO 1995012288 B1 WO1995012288 B1 WO 1995012288B1 US 9411883 W US9411883 W US 9411883W WO 9512288 B1 WO9512288 B1 WO 9512288B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bitstream
- decoding system
- signal
- signal decoding
- synchronizing
- Prior art date
Links
- 230000005540 biological transmission Effects 0.000 claims abstract 10
- 230000001360 synchronised Effects 0.000 claims abstract 3
- 230000000873 masking Effects 0.000 claims 1
Abstract
A novel synchronization scheme for use in connection with digital signal video decoder (58) comprises a pre-parser (52), a channel buffer (54), and a post-parser (56). The pre-parser (52) synchronizes to a multiplexed system bitstream received from a fixed rate channel (50). The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser (52) to a channel buffer (54). The post-parser (56) is coupled to the channel buffer (54) and to a video decoder (58) in a series configuration. The post-parser (56) separates the various layers of video data from the video bitstream component. The post-parser (56) performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder (58) so as to reconstruct an originally encoded picture or frame. Preferably, the multiplexed system bitstream data structure conforms to some format agreed upon among video digital businesses involved in transmission and reception. In accordance with one aspect of the present invention, the pre-parser (52) and the post-parser (56) operate independent of each other, and operate at different processing rates.
Claims
1. (Amended) A signal decoding system comprising: a first signal synchronizing means, having an input coupled to a transmission channel, for synchronizing to a variable bit-rate coded signal received from said input, and for parsing a portion of said variable bit-rate coded signal; a buffer having an input coupled to an output of said first synchronizing means; a decoder, coupled to an output of said buffer, for decoding said portion of said variable bit-rate coded signal; and a second synchronizing means, disposed between said buffer and said decoder, for parsing said portion of said variable bit-rate coded signal.
2. A signal decoding system as defined in Claim 1 wherein the input of said first synchronizing means and said transmission channel are coupled in a series configuration.
3. A signal decoding system as defined in Claim 2 wherein said variable bit-rate coded signal is processed bit-serially by said first synchronizing means.
4. A signal decoding system as defined in Claim 1 wherein said first synchronizing means further includes means for aligning said variable bitrate coded signal.
5. A signal decoding system as defined in Claim 1 wherein said parsed portion of said variable bit-rate coded signal comprises video information.
6. A signal decoding system as defined in Claim 1 wherein said parsed portion of said variable bitrate coded signal comprises audio information.
7. A signal decoding system as defined in Claim 1 wherein a structure of said variable bit-rate coded signal conforms to an MPEG format.
8. A signal decoding system as defined in Claim 1 further comprising a multiplexer for selectably switching the input to said first synchronizer means between said transmission channel and a second signal source providing a second variable bit-rate coded signal.
9. A signal decoding system as defined in Claim 1 further including means for parsing a video portion of said variable bit-rate coded signal.
10. A signal decoding system as defined in Claim 1 further including a channel write buffer disposed between said buffer and said first synchronizing means.
11. CANCELLED
12. (Amended) A signal decoding system as defined in Claim 1 wherein said second synchronizing means and said decoder are coupled in a parallel configuration.
13. (Amended) A signal decoding system as defined in Claim 1 wherein the synchronizing and parsing performed by said first synchronizing means are executed independent of the operations of said second synchronizing means. * 14. (Amended) A signal decoding system as defined in Claim 1 wherein said second synchronizing means
4 includes means for translating said parsed portion of said variable bit-rate signal.
15. (Amended) A signal decoding system as defined in Claim 1 wherein said second synchronizing means includes means for detecting and masking synchronizing errors.
16. A signal decoding system as defined in Claim 1 wherein said first synchronizing means accepts variable bit-rate coded signals from said transmission channel at transmission rates between 1 and 16 megabits per second.
17. A signal decoding system comprising: a first synchronizing means for receiving a multiplexed bitstream from a transmission channel, said multiplexed bitstream comprising at least an audio bitstream and a video bitstream; means, coupled to said first synchronizing means, for parsing a video bitstream from said multiplexed bitstream; a channel buffer, coupled to said parsing means, receiving said video bitstream; a second synchronizing means, coupled to said channel buffer, for further parsing said video bitstream; and a decoder, coupled to said second synchronizing means, for decoding said parsed video bitstream.
18. A signal decoding system as defined in Claim 17 wherein said multiplexed bitstream is processed bit- serially by said first synchronizing means.
19. A signal decoding system as defined in Claim 17 wherein a structure of said multiplexed bitstream conforms to an MPEG format.
20. A signal decoding system as defined in Claim 17 further comprising a multiplexer for selectably switching the input to said first synchronizer means between said transmission channel and a second signal source providing a video bitstream.
21. A signal decoding system as defined in Claim 17 further including a channel write buffer disposed between said buffer and said first synchronizing means.
22. A signal decoding system as defined in Claim 17 wherein said second synchronizing means and said decoder are coupled in parallel.
23. A signal decoding system as defined in Claim 17 wherein operations performed by said first synchronizing means are executed independent of operations performed by said second synchronizing means.
24. A signal decoding system as defined in Claim 17 wherein said second synchronizing means further includes means for translating said parsed video bitstream.
25. A signal decoding system as defined in Claim 17 further including a channel read buffer disposed between said channel buffer and said second synchronization means.
26. (Amended) A process of decoding a bitstream comprising the steps of: receiving a multiplexed bitstream from a transmission channel, the multiplexed bitstream including at least a video bitstream; synchronizing to the received multiplexed bitstream; parsing the video bitstream from the synchronized multiplexed bitstream; transferring the video bitstream to a channel buffer; further parsing the video bitstream; and decoding the parsed video bitstream.
27. (Amended) The process of claim 26 including the further step of switching between said transmission channel and an external video bitstream source.
28. The process of Claim 26 wherein the multiplexed bitstream has a structure that conforms to an MPEG format.
29. (Amended) The process of claim 26 wherein the steps of synchronizing to the multiplexed bitstream and parsing the video bitstream from the synchronized multiplexed bitstream proceed independently with respect to the steps of parsing the video bitstream and decoding the parsed video bitstream.
30. (Amended) The process of claim 26 wherein the step of synchronizing to the multiplexed bitstream is performed bit-serially.
31. (Amended) The process of claim 26 wherein the step of further parsing the video bitstream is performed in a parallel manner.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94930821A EP0676116A4 (en) | 1993-10-25 | 1994-10-18 | A two-part synchronization scheme for digital video decoders. |
JP7512707A JPH08505513A (en) | 1993-10-25 | 1994-10-18 | Two-step synchronization scheme for digital video decoder |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/143,316 US5452006A (en) | 1993-10-25 | 1993-10-25 | Two-part synchronization scheme for digital video decoders |
US143,316 | 1993-10-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1995012288A1 WO1995012288A1 (en) | 1995-05-04 |
WO1995012288B1 true WO1995012288B1 (en) | 1995-05-26 |
Family
ID=22503527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1994/011883 WO1995012288A1 (en) | 1993-10-25 | 1994-10-18 | A two-part synchronization scheme for digital video decoders |
Country Status (4)
Country | Link |
---|---|
US (2) | US5452006A (en) |
EP (1) | EP0676116A4 (en) |
JP (1) | JPH08505513A (en) |
WO (1) | WO1995012288A1 (en) |
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- 1993-10-25 US US08/143,316 patent/US5452006A/en not_active Expired - Lifetime
-
1994
- 1994-10-18 JP JP7512707A patent/JPH08505513A/en active Pending
- 1994-10-18 WO PCT/US1994/011883 patent/WO1995012288A1/en not_active Application Discontinuation
- 1994-10-18 EP EP94930821A patent/EP0676116A4/en not_active Withdrawn
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1995
- 1995-09-18 US US08/529,687 patent/US5686965A/en not_active Expired - Lifetime
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