WO1995005705A1 - Systeme de transmission numerique sans fil et procede de fonctionnement associe - Google Patents

Systeme de transmission numerique sans fil et procede de fonctionnement associe Download PDF

Info

Publication number
WO1995005705A1
WO1995005705A1 PCT/US1994/009175 US9409175W WO9505705A1 WO 1995005705 A1 WO1995005705 A1 WO 1995005705A1 US 9409175 W US9409175 W US 9409175W WO 9505705 A1 WO9505705 A1 WO 9505705A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
digitally encoded
unit
digital
frequency
Prior art date
Application number
PCT/US1994/009175
Other languages
English (en)
Inventor
Jong-Keung Cheng
Ravi Subramanian
Mihran H. Touriguian
Nan-Sheng Lin
Biswa Ghosh
Robert Kavaler
Amine Haoui
Kenkichi Suzuki
Original Assignee
Teknekron Communications Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/107,938 external-priority patent/US5491726A/en
Priority claimed from US08/108,084 external-priority patent/US5436942A/en
Priority claimed from US08/107,451 external-priority patent/US5400368A/en
Priority claimed from US08/108,061 external-priority patent/US5438595A/en
Application filed by Teknekron Communications Systems, Inc. filed Critical Teknekron Communications Systems, Inc.
Publication of WO1995005705A1 publication Critical patent/WO1995005705A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S11/00—Systems for determining distance or velocity not using reflection or reradiation
    • G01S11/02—Systems for determining distance or velocity not using reflection or reradiation using radio waves
    • G01S11/10—Systems for determining distance or velocity not using reflection or reradiation using radio waves using Doppler effect
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Definitions

  • the present invention is a digital wireless communication system and a method of operation therefor.
  • Wireless communication is well known in the art.
  • one type of wireless communication is known as a "cellular" communication wherein each stationary unit receives and transmits signals to mobile units within its allocated geographical region, called a cell.
  • cellular communication is analog based and has risen in popularity.
  • the airways have become increasingly crowded and the capacity of the communication system to take on new subscribers is becoming increasingly of a problem.
  • Digital cellular communication offers an opportunity to increase the number of subscribers to operate within the cellular system.
  • a standard has been proposed.
  • the standard proposed by EIA/TIA (Electronic Industry Association/Telecommunications Industry Association) , known as the IS-54 standard, specifies that communication between a mobile unit and a base unit should be capable of operating in both the analog and the digital mode. More particularly, when operating in the digital wireless communication mode, the IS-54 standard specifies that communication between a base unit and a mobile unit occur in a Time Division Multiplex Access (TDMA) mode.
  • TDMA Time Division Multiplex Access
  • the digitally encoded signal is transmitted in a plurality of non-contiguous time slots. Communication between a base unit and a mobile unit occurs in an assigned time slot, within each frame. In each time slot, digitally encoded synchronization signal must first be transmitted followed by the digitally encoded data signal.
  • a digitally encoded marker signal is transmitted.
  • One of the problems of a digital wireless communication system is the problem of equalizing the digitally encoded signals. As the digitally encoded signal is transmitted from one unit to another, through a multiplicity of data paths, the various signals arriving at the other unit can cause delay spread between the digitally encoded signals. This is known as inter-symbol interference.
  • An equalizer is a digital hardware/software apparatus which corrects inter-symbol interference between the digitally encoded signals arriving from a plurality of signal paths.
  • the present invention is a digital wireless communication system and a method of operation therefor. More particularly, the present invention relates to a method of estimating the speed of a mobile unit moving relative to a stationary unit in the digital wireless communication system. In addition, the digital wireless communication system can adjust the sampling phase of the digitally encoded signal transmitted between the mobile unit and the stationary unit. The invention also relates to an apparatus to control the frequency of reception in the digital wireless communication system, and a method for adjusting the carrier frequency of reception in such a system. Further, the invention relates to a technique to correct deviation in the frequency in the transmission from one unit to another in the digital wireless communication system. Finally, the invention relates to a method and apparatus for equalizing the signals transmitted in such a digital wireless communication system.
  • Figure 1 is a block level diagram of a wireless communication unit which is a remote unit or is a portion of a stationary unit of a digital wireless communication system.
  • Figure 2 is a block level diagram of the signal flow path when the wireless communication unit shown in Figure 1 is operating in the analog mode.
  • Figure 3 is a block level diagram of the signal flow path when the wireless communication unit shown in Figure 1 is operating in a digital mode.
  • Figure 4 is a detailed block level diagram of the RF unit portion of the communication unit shown in Figure 1.
  • FIG. 5 is a detailed block level diagram of the AFE portion of the communication unit shown in Figure 1.
  • Figure 6 is a flow chart showing the operation of the software used in the Modem DSP of the communication unit shown in Figure 1, when the Modem DSP is operating in the receive mode and having two modes of operation : sync acquisition mode and steady state mode.
  • Figure 7 is a functional block diagram of the Modem DSP with its software, operating in the sync acquisition mode.
  • Figure 8 is a functional block diagram of the
  • Figure 9 is a detailed functional block diagram of the timing recovery function during the steady state mode shown in Figure 8.
  • Figure 10 is a detailed functional block diagram of the DQPSK receiver function during the steady state mode shown in Figure 8.
  • Figure 11 is a timing diagram of the protocol of communication between like units of Figure 1, when operating in a digital mode.
  • Figure 12 is a diagram showing the difference in energy of a signal received by a mobile unit when moving.
  • Figure 13 is a block level diagram showing the measurement of energy in a time slot to estimate the speed of a mobile unit.
  • Figure 14 (a-c) are diagrams showing the methods of training an equalizer.
  • FIG. 1 there is shown a schematic block level diagram of a communication unit 10.
  • the communication unit 10 is that of the mobile unit.
  • the schematic block level diagram shown in Figure 1 represents a portion of the stationary unit. More particularly, as will be appreciated by those having ordinary skilled in the art, the stationary unit would comprise additional units to accomplish function such as hand off and the ability to process many remote units at the same time.
  • the communication unit 10 comprises an antenna 12 which receives the RF (radio frequency) wireless signal .
  • the RF signal is then processed by an RF processing unit 14.
  • the base band processor 20 comprises in AFE (analog front end) 22, which receives the RF signal from the RF processing unit 14.
  • the signal from the AFE unit 22 is then received by a Modem DSP 24.
  • the signal from the Modem DSP 24 is received by a VSELP DSP 26.
  • a FPGA (Field Programmable Gate Array) 28 communicates with the Modem DSP 24 and the VSELP DSP 26.
  • the FPGA 28 also communicates with an audio codec 30.
  • the FPGA 28 is connected to a controller 32.
  • the audio codec 30 is connected to a conventional speaker and microphone.
  • the communication unit 10 in the preferred embodiment implements the IS-54 standard.
  • the communication unit 10 can process both analog wireless signals as well as digital by encoded wireless signals.
  • the above-identified components operate in the following manner: RF processing unit 14 receives the analog or the digitally encoded RF signal and converts them into an baseband signal for further processing by the based band processor 20.
  • the RF processing unit 14 also demodulates the received IF signal to produce the analog I,Q signals.
  • the AFE unit 22 implements analog to digital and digital to analog conversions with associated filtering functions for the I/Q signals. In addition, it provides for four (one not used) channel D/A for RF control. It also has one A/D for RSSI (Receive Signal Strength Indicator) measurement.
  • RSSI Receiveive Signal Strength Indicator
  • the Modem DSP 24 in the preferred embodiment is a digital signal processor which is ROM coded (TMS 320c51) which implements analog mode processing, modem functions in the digital mode, as well as FACCH (Fast Access Control Channel) /SACCH (Slow Access Control Channel) error control functions. FACCH/SACCH are defined by the IS-54 standard and is well known in the art.
  • the modem processor 24 interfaces with the FPGA I/O decoder 28 through its serial port. Through the FPGA 28, the FPGA 28 then communicates with the controller 32.
  • the Modem DSP 24 also maintains the time division multiplex (TDM) bus for communication with the VSELP DSP processor 26 and the audio codec 30 when operating in the analog mode.
  • the Modem DSP 24 communicates with the RF processor 14 through the AFE 22.
  • the VSELP DSP 26 is also a ROM coded DSP (TMS 320c51) which implements the VSELP codec functions, which is a speech compression algorithm. In addition, it performs error control functions associated with the speech frame and echo cancellation. Finally, it communicates with the Modem DSP 24 via the TDM port and is powered down during the analog mode operation.
  • TMS 320c51 ROM coded DSP
  • the audio codec 30 implements the speech A to D and D to A conversion and associated filtering. It interfaces directly to the speaker and to the microphone (not shown) .
  • the speech samples are exchanged with the Modem DSP 24 through the TDM port and TDM to pulse code modulation (PCM) conversion circuit in the FPGA I/O decoder 28 during the analog mode operation.
  • PCM pulse code modulation
  • the audio codec 30 interfaces with the VSELP DSP 26 through the PCM bus.
  • the FPGA I/O decoder 28 consist of a first FPGA1 28a, a second FPGA2 28d, and a PAL (Programmable Array Logic - not shown) , for I/O address decoding.
  • the first FPGA1 28a includes timing generation circuitry, wideband data demodulator, sync control interface, and baseband test interface.
  • the second FPGA2 28b includes an interface (UPIF) to interface with the controller 32. In addition, it communicates with the audio codec 30 and the VSELP DSP 26 through the PCM port and has TDM/PCM conversion circuitry. Finally, the second FPGA2 28b has a sampling clock (interrupt control) .
  • FIG. 2 there is shown the signal flow for the communication unit 10 when operating in the analog mode.
  • the VSELP DSP 26 is completely "turned off".
  • the analog wireless signal is received by the RF unit 14 and is supplied to the AFE unit 22. From the AFE unit 22, the signal is supplied to the Modem DSP 2 .
  • the Modem DSP 24 through its TDM port communicates with the second FPGA2 28b. From the PCM port of the second FPGA2 28b, the second FPGA2 28b communicates with the codec 30.
  • FIG. 3 there is shown a block level diagram of the signal flow when the communication unit 10 operates in the digital mode.
  • the VSELP DSP 26 is actively involved in the processing of the received digitally encoded signal.
  • FIG 11 there is shown a timing diagram of a digitally encoded signal when the communication unit 10 operates in the digital mode, implementing in particular, the 1S-54 standard.
  • the communication between a base unit and a mobile unit is divided into a plurality of frames, designated as Fl, F2, etc., with each frame lasting 20 msec.
  • each 20 msec, frame is further divided into a plurality of time slots, shown as Tl, T2 and T3.
  • the base unit can serve to communicate with three different mobile units. Further, when the VSELP DSP 26 is operating at half rate compression i.e., 4 kbits per second, communication between the base unit and a plurality of mobile units can occur using a 40 msec, frame with each frame divided into six different time slots or serving six users. Each time slot Tn can accommodate the transmission of 162 symbols or 324 bits.
  • the base unit and the mobile unit communicate over separate frequency channels thereby accomplishing full duplex transmission.
  • the protocol of transmission from the base unit to the mobile unit is shown and designated as f (for forward) .
  • the protocol of transmission from the mobile unit to the base unit is shown and is designated as r (for reverse) .
  • the IS-54 standard dictates that the digitally encoded signal begins with 14 symbols of synchronization signal followed by 148 symbols of data signal, with 6 symbols of DVCC (a marker signal) located in the middle of the data field between symbols 85-91.
  • DVCC a marker signal
  • the RF processing unit 14 receives the signal from the antenna 12 through a duplexer.
  • the received signal is supplied to an RF + IF stage 72.
  • the RF + IF stage 72 has an RF filter, low noise amplifier which serves to filter and amplify the received signal, and an RF to IF converter to convert the received RF signal into an intermediate frequency signal.
  • the conversion is based upon a difference frequency signal generated by an RX frequency synthesizer 74.
  • the frequency selected by the RX frequency synthesizer 74 is based upon a signal supplied from a temperature compensated crystal oscillator 70, passing through an appropriate multiplier 78.
  • the output of the RF + IF stage 72 is then supplied to an amp and I/Q demodulator 76 whose gained is selected by an automatic gain control signal AGC.
  • the outputs of the amp + I/Q demodulator 76 are the analog I and analog Q signals.
  • the RF processing unit 14 comprises similar components as the above.
  • the analog I and analog Q signals are supplied to an I/Q modulator 86, which modulates the analog I,Q signals on an IF carrier signal.
  • the output of the I/Q modulator 86 is then supplied to an RF + IF stage 82.
  • the RF + IF stage 82 converts up the output of the I/Q modulator 86 into an RF signal for transmission by the antenna 12.
  • the frequency to convert from the intermediate frequency to the RF frequency is controlled by the TX frequency synthesizer 84.
  • the TX frequency synthesizer 84 also receives the output of the temperature compensated crystal oscillator 70 multiplied by an appropriate multiplier 88.
  • the AFE unit 22 comprises a first LPF (low pass filter) 91.
  • the first LPF 91 receives the received analog I/Q signals from the RF unit 14.
  • the output of the LPF 91 is then supplied to an A-to-D converter 90 from which the digital Rxl and the digital RxQ signals are produced.
  • the A-to-D converter 90 also receives a clock signal from a clock 92.
  • the clock 92 is adjusted by a sampling phase adjustment signal (which will be described hereinafter) .
  • the AFE unit 22 also comprises a D-to-A converter 118.
  • the D-to-A converter 118 receives the transmit digital I and Q (Tx I/Q) signals and converts them into analog Tx I/Q signals.
  • the D-to-A converter 118 also receives the clock signal from the clock 92.
  • the analog Tx I/Q signals are then supplied to a second LPF 117.
  • the output of the second LPF 117 is then supplied as the Tx analog I/Q signals and are provided to the RF unit 14.
  • the AFE unit 22 also comprises a WBDD (wide band data demodulator) 119. From the WBDD 119, the signal wide band data is produced.
  • the wide band data demodulator signal is an analog control channel. It is disclosed herein only because the IS-54 standard requires that the communication unit 10 can handle both analog and digital communication. It is not used during digital communication.
  • the AFE unit 22 also comprises a D-to-A converter 93 which receives the control signals of Tx_Power, AFC, and AGC. These digital signals are converted into an analog signal and are supplied to the RF unit 14 to control the RF unit 14. Finally, the AFE unit 22 receives the RSSI (receive signal strength indicator) signal and digitizes it by the A-to-D converter 95.
  • FIG. 6 there is shown a flowchart of the operation of the software used in the Modem DSP 24 when the Modem DSP 24 is operating in the received mode.
  • the Modem DSP 24 has two modes of operation: a sync acquisition mode, and a steady state mode.
  • the sync acquisition mode the operation occurs at the start of each communication session.
  • the software proceeds into the steady state mode. There, the operation occurs once every frame or once every 20 millisec.
  • the Modem DSP 24 initially performs a timing recovery operation 42 which is shown in Figure 9 and which will be explained in greater detail .
  • the Modem DSP 24 operates on the signal shown in block level diagram form in Figure 10 and will be discussed in greater detail hereinafter. Referring to Figure 7, there is shown a detailed functional block diagram of the sync acquisition mode of operation for the Modem DSP 24.
  • the digital I/Q received signals from the AFE unit 22 are supplied to a normalizing circuit 96.
  • the normalizing circuit 96 serves to normalize the magnitude or the amplitude of the digitized I,Q signals from the A to D converter 90.
  • the digitally encoded signal is then stored in a storage unit 98, which is just a buffer.
  • the storage 98 stores at least 15 symbols (or 30 samples) which is the length of the synchronization signal portion of the digitized signal.
  • the stored signals are then supplied to a first bank of match filters 100.
  • Each of the filters in the first bank 100 is adapted to receive the digital signal from the storage 98 and to filter this digital signal through a frequency range different from one another.
  • the output of the first bank of match filters 100 is a plurality of filtered digital signals.
  • the plurality of filtered digital signals are supplied to a plurality of first magnitude circuits 102.
  • Each of the plurality of first magnitude circuits 102 determines the magnitude of the filtered digital signal from the first bank of match filters 100.
  • the output of the first magnitude circuits 102 is yet another plurality of digital signals which are supplied to a first maximum and threshold circuit detector 106.
  • the output of the first maximum and threshold circuit detector 106 serves to detect the filtered digital signal having the maximum magnitude.
  • the first maximum and threshold circuit 106 selects the match filter from the first bank of matched filters 100 that generated the signal having the maximum output.
  • the output of the first maximum and threshold circuit 106 is supplied to a second bank of match filters 108.
  • Each of the filters in the second bank of match filters 108 has a fine frequency offset from one another and having a different filter coefficients from one another.
  • the output of the second bank of match filters 108 is a plurality of fine filtered digital signals which are supplied to a second magnitude circuit 110.
  • the second magnitude circuit 110 similar to the first magnitude circuit 102, comprises a plurality of circuits each of which receives a fine filtered digital signal and determines the amplitude or the magnitude thereof.
  • the output of the second magnitude circuit 110 is a plurality of signals which are supplied to a second maximum and threshold circuit detector 112.
  • the second maximum and threshold detector 112 selects the digital signal having the maximum amplitude as the output thereof.
  • the second maximum and threshold circuit 112 selects the filter from the second bank of match filters 102, producing that output.
  • the output of the second maximum and threshold circuit 112 is an initial carrier frequency offset signal to correct the carrier frequency to the AFC (automatic frequency control), and a time slot position signal.
  • the time slot position signal is used internally to control the start and stop of each subsequent frame.
  • the Modem DSP 24 performs SQRC filtering function 42 and 50 (for receive and transmit) and timing recovery 42 (for receive) , DQPSK modulation 44 and 52 (again receive and transmit respectively) and frame interleaving/De-interleaving 46 and 54 (receive and transmit respectfully) , and FACCH decode and encode 48 and 56 (receive and transmit respective) .
  • the VSELP DSP 26 performs channel decode and encoding 62 and 66 (receive and transmit, respectively) and speech decode and encode 64 and 68 (receive and transmit respectively) .
  • FIG. 9 there is shown a detailed block level functional diagram of the timing recovery function 42 performed by the Modem DSP 24 when operating in the steady state mode.
  • the Rx I/Q signals from the second maximum and threshold circuit detector 112 are supplied to a 1:4 interpolator 114.
  • the output of the interpolator 114 is then supplied to a third match filter 116.
  • the match filter 116 also receives the stored sync signal from a storage location 104.
  • the match filter 116 is a single filter and it matches each input sample symbol with the stored sync signal from the storage location 104. After each match, the input signal is shifted by T/8, or by one input sample and then is matched again with the sync signal from the storage location 104. Thus, the output of the match filter 116 is a signal operating at the T/8 rate.
  • the outputs of the match filter 116 are then supplied to a peak detector 118.
  • the peak detector 118 receives the plurality of outputs from the match filter 116, being supplied thereto at the T/8 rate, and determines the output having the highest peak value.
  • the output of the peak detector 118 is the value imax, the use of which will be discussed hereinafter.
  • the output from the peak detector 118 is then supplied to a second order phase lock loop 119.
  • the second order phase lock loop 119 has an internal variable AVG-POS, the use of which will be described hereinafter in greater detail.
  • the output of the second order phase lock loop 119 is the sampling phase adjustment signal which is supplied to the clock 92 of the AFE 22 shown in Figure 5.
  • the received digital Rx I/Q signals at the T/2 rate are also supplied to a bank of SQRC filters 117.
  • the output of the second order PLL 119 is used to select the appropriate SQRC filter from the bank of SQRC filters 117.
  • the output of the second order PLL 119 is the signal Avg-pos (n+1) . It is supplied to the AFE unit 22 and is adjusted once every frame during the idle period. the coefficient filter of each of the bank of SQRC filters 117 is tuned to a different sampling phase adjustment. Thus, the output of the second order PLL 117 selects one of the coefficient filters from the bank of SQRC filters 117.
  • the DQPSK receiver 44 receives each symbol as the output of the timing recovery function 42.
  • the digital Rx I/Q symbols are supplied to a pre-processing unit 121 which generates the control signals: speed estimation, energy calculation, and CTRL.
  • the CTRL signal controls the DQPSK receiver 44 in its two modes of operation. In one mode, each symbol from the output of the timing recovery 42 is supplied to a fine all pass filter 120. From the fine all pass filter 120, each symbol signal is supplied to a differential detector 122. From the differential detector 122, the symbol signal is then supplied to a phase slicer 126 and an arc tangent processor 128.
  • each symbol from the timing recovery function 42 is supplied to an equalizer 124.
  • the equalizer 124 operates on all the symbols received during the assigned time slot.
  • each symbol is outputted from the equalizer 124, one at a time.
  • Each symbol signal from the equalizer 124 is also supplied to the phase slicer 126 and at the same time to the arc tangent processor 128.
  • Each of the symbol signal from the equalizer 124 or the differential detector 122 is received simultaneously by the phase slicer 126 and the arc tangent processor 128.
  • the phase slicer 126 operates upon the symbol signal by quantizing the input phase into one of a plurality of pre-determined constellation points (i.e. 45°, 135°, 225°, 315°) and generates the phase signal ⁇ .
  • the arc tangent processor 128 receives the same symbol signal and serves to operate on the symbol signal received to determine the arc tangent of its phase.
  • the output of the arc tangent processor 128 is the phase signal ⁇ .
  • the phase signal ⁇ and the phase signal ⁇ are supplied to a first subtractor (or adder with a negative input) 130 which generates the phase error signal ( ⁇ - ⁇ ) .
  • the phase error signal ( ⁇ - ⁇ ) is then supplied to a first multiplier 132 to which a constant g 1 is multiplied. Thereafter, the output of the first multiplier 132 is supplied to a second adder 134 to which the frequency signal output from a prior operation on a prior symbol was stored in the storage 136. From the second adder 134, the adjustment to the frequency to the next symbol or the frequency error signal, is then generated.
  • the frequency error signal which is generated is in accordance with:
  • ⁇ f(n+1) ⁇ f(n) + g 1 ( ⁇ (n) - ⁇ (n) ) ;
  • the output of the first adder 130 is also supplied to a second multiplier 138 to which the constant g 2 is supplied.
  • the output of the second multiplier 138 is then supplied to a third adder 140 to which the frequency error signal ⁇ f (n) from a prior symbol is also supplied.
  • the output of the third adder 140 is supplied to a fourth adder 142 to which the carrier phase ⁇ signal from a prior bit has been supplied and stored in storage 144.
  • the digital wireless communication unit 10 is particular adapted for digital cellular communication wherein errors such as rayleigh fading, intersymbol interference and carrier frequency offset present problems.
  • the remote unit and the base unit must necessarily establish initial frequency and time slot position.
  • the IQ signals are digitized by the analog to digital converter 90, they are normalized by the normalizing unit 96 to retain only the phase information.
  • the digitized I,Q samples are then stored in a storage unit 98 or a delay line of size of 30 complex. The size is chosen because the storage unit 98 or the delay line must contain 14 phase changes for the sync word, which is 15 symbols or 30 samples at T/2 sampling rate.
  • the output of the storage unit 98 is supplied to a first bank 100 of 6 matched filters consisting of six 15-TAP FIR complex filters. Each one is matched to the same sync word but with a different carrier frequency offset. The range of offset is designed to cover the plus or minus 2.5 ppm offset of an 850 MHz carrier or an offset of about 1900 Hz. Even though each of the filters has 15 symbols spaced taps, odd and even samples from the delay line 98 are alternately entered into each of the match filters so that T/2 resolution is maintained. Thus, the output of each match filter is an output also at the T/2 rate.
  • Each of the match filters of the first bank 100 is matched to the carrier phase shifted versions of the sync word symbols-not the phase changes from symbol to symbol.
  • each of the match filters from the first bank 100 has a center of frequency offset covering the 2.5 ppm 1900 Hz range of possible frequency offsets as shown below. -1900 -1566 -938 -315 0 +315 +938 +1566 +1900
  • Fi-F g being the center frequency of six 15-TAP FIR filters.
  • Each of the match filters from the first bank 100 simultaneously provides frequency offset estimate, start of frame, and time slot and symbol timing to within T/2 accuracy. If a particular match filter of the first bank 100 matches a particular sync word, then there will be a high output when the contents of the storage 98 are exactly aligned with the sync word and low output for any other alignment. Thus, the match filters from the first bank 100 provide a good indication of frame, slot and symbol timing to within one T/2 sample.
  • the detection range of a particular offset can be found empirically to be about ⁇ 11 degree, i.e., each match filter has high output only when the match filter's offset matches the signal's offset within this range.
  • match filter producing the largest amplitude is detected and is chosen, i.e., that match filter from the first bank 100 has the exact or the closest offset to the frequency, then it is supplied to a second bank 108 of match filters.
  • the second bank 108 of match filters is a bank of 4 fine match filters each spaced 126 Hz apart.
  • the output of the first maximum and threshold circuit detector 106 or the coarse frequency estimate is used to find the center frequency.
  • the received sync word samples are then digitally rotated by this estimate to bring them down to near the baseband.
  • the rotated sync samples are then run through the second bank 108 comprising of 4 fine match filters.
  • the filter with the highest output from the five filters determines the final fine frequency offset estimate.
  • the final frequency offset estimate should be accurate to within 0.9 degrees or 63 Hz.
  • the centers of the match filters for the second bank 108 are offset to the plus and minus of the center frequency from the coarse estimate.
  • the time slot position is precise up to T/2 because the filters from the first bank 100 are precise up to T/2.
  • frequency offset such as drift
  • the communication unit 10 must adaptively control the frequency during the communication session.
  • the symbol signal from the output of the differential detector 122 or from the output of the equalizer 124 is supplied to both the phase slicer 126 and the arc tangent processor 128.
  • the phase slicer 126 g 3 enerates the phase sig a nal ⁇ (,n.) . _Th,e arc t.angent.
  • processor 128 generates the phase signal ⁇ (n) .
  • the output of the phase slicer processor 126 and the arc tangent processor 128 are supplied to a first adder 130 which computes the phase error signal as previously discussed.
  • the frequency error signal ⁇ f (n) is computed as previously discussed.
  • the constant g ⁇ is 2 " during sync acquisition and is 2 in a steady state mode.
  • the constant g 2 is 2 " during the sync acquisition and 2 in a steady state mode.
  • the adjustment based upon frequency error signal is performed once after the assigned time slot in question i.e., during the idle slot and does not affect the received sample until the beginning of the next frame.
  • the higher order 10 bits of ⁇ f are used for AFE correction and this number is subtracted from
  • the carrier phase error signal is also calculated as shown above.
  • the carrier phase error signal (different from sampling phase error signal) is used to adjust the carrier phase of the frequency.
  • sampling phase during the operation of the communication session must also be adaptively controlled.
  • the received I/Q ' samples around the sync word are passed to an interpolator 114.
  • the interpolator 114 generates 8xT samples (the input to the interpolator 114 is already at 2T rate) .
  • the output of the interpolator 114 is match filtered by the filter 116 with an ideal sync word stored from the storage 104 at T sampling rate.
  • the acquisition mode has already determined timing to within T/2 sampling phase, by interpolating at 4x the input rate, in theory, the match filter 116 must only determine within a plus or minus four sample range.
  • Four samples at 8XT sampling rate means the search window is T/2.
  • the detected peak may belong to the delayed path, hence its timing may be the delayed version of ideal timing.
  • the main signal may not be the largest.
  • the search is extended over minus 1 and plus 2 symbols of the expected symbol or minus 8 to plus 16 sample range.
  • the sampling phase adjustment of the phase adjuster 94 is computed in a second order timing recovery loop.
  • the sampling phase is adjusted after the completion of the assigned time slot and prior to the commencement of the next frame.
  • the sampling phase adjustment occurs during the idle time slot.
  • the purpose of using a second order rather than first is to minimize jitter of the correction.
  • Instant sampling phase correction or first order timing correction can cause a jitter.
  • the first order timing phase error is corrected by choosing the best matched filters from the bank of match filters 108 for each frame. The frequency offset from frame to frame is adjusted as previously discussed.
  • drift(n+l) drift(n) + ⁇
  • avg-pos(n+l) avg-pos(n) +
  • n is the frame count
  • imax(n) is the peak position of matched filter output for frame n
  • ⁇ 2 for the first 100 frames
  • ⁇ 2 "7 for the next 100 frames
  • ⁇ 2 after 200 frames.
  • the adjustment to the sampling phase adjuster 94 depends upon whether the argument inside L-J is negative argument (in which case the unit 10 should advance timing, sample should be sooner) or is positive argument (in which case the unit 10 should retard timing, the samples being later) .
  • negative argument i.e. avg-pos(n) > imax(n)
  • the timing adjustment in the preferred embodiment should be limited by: a. -3 x — for n ⁇ 100 8
  • timing adjustment in the preferred embodiment should be limited by
  • the advance magnitude is larger than the retard magnitude so that the equations are biased towards moving to the first ray, which implies earlier sampling.
  • the sampling time for the current frame is determined by picking the SQRC filter closest to avg- pos.
  • the sampling clock 92 is corrected by the' amount avg-pos (n+l) but is limited by T/8. In practice, because the base station's clock accuracy is 5 ppm and the remote unit is 100 ppm, the correction is never even as large as T/8.
  • each of the fine all pass filters is a complex T/2 spaced 4 tap FIR filter.
  • the bank of the coarse filters from the maximum and threshold detector 112 along with the timing recovery equations determine timing for the current frame to an accuracy of T/8. Finer accuracy T/32 is obtained by using one of five fine all pass filter 120 spaced 11.25 degrees apart.
  • the correct filter is determined by the residual value of avg-pos after choosing the coarse all pass filter.
  • the fine filter centers are: -22.5 -11.25 0 +11.25 +22.5
  • Vehicle speed estimation is necessary. Vehicle speed can be roughly estimated from the slope of the received signal amplitude.
  • FIG. 12 there is shown a graph of the amplitude of transmission by a moving vehicle (or reception by the moving vehicle) of a signal generated by the other.
  • the slope of the amplitude is indicative of the speed of the mobile unit.
  • the information required is very coarse, e.g., slow, medium or fast. Thus, accuracy is not critical. At higher speeds fades occur more rapidly so the slopes are greater.
  • the slope is estimated by measuring the difference between short term energies of a plurality of contiguous symbols.
  • the short term energy E(k) is averaged over 8 contiguous samples. Since there are 162 symbols in a time slot plus 14 symbols of the sync field of an adjacent time slot, there are a total of 176 symbols. The 176 symbols are processed at T/2 rate. Thus there are 352 (T/2) samples. With eight samples per short term average, there are 44 short term average samples.
  • the slope estimation updated equation is
  • the average energy of groups of five contiguous short term energy E (k) is taken.
  • a second group is separated from a first group by five short term energy points.
  • the magnitude of the difference between the first group and the second group is computed. This process is repeated 30 times by shifting the groups by one short term energy point each time.
  • Diff Ave x Diff Av ⁇ + (1- ⁇ ) x Diff where a is a smoothing constant.
  • equalization can be improved significantly by doing equalization bi- directionally.
  • one minimum energy point is located in the assigned time slot (as shown in Figure 14 (a) )
  • the RLS equalizer is trained by progressing forward from the commencement of the sync signal of the assigned time slot until the minimum energy point and progressing backward from the end of the sync signal of the succeeding, non-assigned time slot, until the minimum energy point is reached.
  • the performance of equalization can be further improved by making use of the DVCC signal as a training sequence.
  • two minimum energy points one in datal field and one in data2 field
  • the RLS equalizer is trained by progressing forward from the commencement of the sync signal of the assigned time slot until the first minimum energy point is reached.
  • the RLS equalizer is trained by progressing backwards from the DVCC marker signal until the first minimum energy point is reached.
  • the RLS equalizer is then trained by progressing forward from the DVCC marker into the data2 field, until the second minimum energy point is reached.
  • the RLS equalizer is trained by progressing backward from the end of the sync signal of the succeeding, non-assigned time slot backward to the second minimum energy point.
  • the RLS equalizer can be trained by first progressing forward from the sync signal until the DVCC marker is encountered. There, the DVCC marker signal is decoded and the RLS equalizer is trained by progressing backwards from the DVCC marker into the first data field, datal, until the first minimum energy point is reached. This is shown in Figure 14 (c) .
  • the minimum energy point detected can be compared to a threshold level.
  • the RLS equalizer proceeds as if there is no minimum energy point. In that event, the RLS equalizer is trained starting with sync of the assigned time slot proceeding through the datal field, through the DVCC marker signal, and through the data2 field.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Système de transmission numérique sans fil (figure 1) dans lequel des appareils peuvent estimer la vitesse d'une unité mobile par rapport à une unité fixe (figure 12). L'appareil peut également régler la phase d'échantillonage d'un signal codé numériquement dans un système de ce type (figures 6 et 9); commander de manière adaptative la fréquence de réception et déterminer la fréquence et la position de la tranche de temps dans une session de transmission numérique sans fil (figures 4 et 6). Le système peut fonctionner pour égaliser (figure 6) des signaux codés numériquement transmis dans une pluralité de tranches de temps non contiguës (figure 11).
PCT/US1994/009175 1993-08-17 1994-08-12 Systeme de transmission numerique sans fil et procede de fonctionnement associe WO1995005705A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US10811393A 1993-08-17 1993-08-17
US08/107,938 US5491726A (en) 1993-08-17 1993-08-17 Method and apparatus to determine the frequency and time slot position in a digital wireless communication session
US08/108,084 US5436942A (en) 1993-08-17 1993-08-17 Method of equalizing digitally encoded signals transmitted in a plurality of non-contiguous time slots
US08/108,084 1993-08-17
US08/108,061 1993-08-17
US08/107,938 1993-08-17
US08/108,113 1993-08-17
US08/107,451 US5400368A (en) 1993-08-17 1993-08-17 Method and apparatus for adjusting the sampling phase of a digitally encoded signal in a wireless communication system
US08/108,061 US5438595A (en) 1993-08-17 1993-08-17 Method of estimating the speed of a mobile unit in a digital wireless communication system
US08/107,451 1993-08-17

Publications (1)

Publication Number Publication Date
WO1995005705A1 true WO1995005705A1 (fr) 1995-02-23

Family

ID=27537188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/009175 WO1995005705A1 (fr) 1993-08-17 1994-08-12 Systeme de transmission numerique sans fil et procede de fonctionnement associe

Country Status (1)

Country Link
WO (1) WO1995005705A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998009384A1 (fr) * 1996-08-28 1998-03-05 Nokia Telecommunications Oy Procede pour commander la puissance et systeme de radiocommunication cellulaire
EP0845174A1 (fr) * 1995-08-18 1998-06-03 Adtran Procede de codage et traitement du signal pour accroitre la portee des transmissions sur une ligne telephonique deux fils sans repeteurs

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466108A (en) * 1981-10-06 1984-08-14 Communications Satellite Corporation TDMA/PSK Carrier synchronization without preamble
US4558460A (en) * 1983-06-14 1985-12-10 Honda Giken Kogyo Kabushiki Kaisha Audio apparatus for vehicle
US4879728A (en) * 1989-01-31 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories DPSK carrier acquisition and tracking arrangement
US4947409A (en) * 1987-11-27 1990-08-07 Telefonaktiebolaget L M Ericsson Apparatus for correcting frequency in a coherent receiver
US5012491A (en) * 1988-08-05 1991-04-30 Nec Corporation Preamable detection circuit for digital communications system
US5018166A (en) * 1989-10-10 1991-05-21 Hayes Microcomputer Products, Inc. Method and apparatus for baud timing recovery
US5027432A (en) * 1988-05-18 1991-06-25 Delco Electronics Corporation Motor vehicle radio with an automatic volume control device
US5040192A (en) * 1990-02-06 1991-08-13 Hayes Microcomputer Products, Inc. Method and apparatus for optimally autocorrelating an FSK signal
US5263026A (en) * 1991-06-27 1993-11-16 Hughes Aircraft Company Maximum likelihood sequence estimation based equalization within a mobile digital cellular receiver
US5272446A (en) * 1991-11-29 1993-12-21 Comsat Digitally implemented fast frequency estimator/demodulator for low bit rate maritime and mobile data communications without the use of an acquisition preamble
US5274670A (en) * 1991-03-01 1993-12-28 Kabushiki Kaisha Toshiba Method of equalization in digital mobile communication with improved tracking ability
US5276706A (en) * 1992-05-20 1994-01-04 Hughes Aircraft Company System and method for minimizing frequency offsets between digital communication stations
WO1994019704A1 (fr) * 1993-02-26 1994-09-01 Fujitsu Limited Appareil a mesurer la vitesse de mouvement d'un systeme de communication mobile

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466108A (en) * 1981-10-06 1984-08-14 Communications Satellite Corporation TDMA/PSK Carrier synchronization without preamble
US4558460A (en) * 1983-06-14 1985-12-10 Honda Giken Kogyo Kabushiki Kaisha Audio apparatus for vehicle
US4947409A (en) * 1987-11-27 1990-08-07 Telefonaktiebolaget L M Ericsson Apparatus for correcting frequency in a coherent receiver
US5027432A (en) * 1988-05-18 1991-06-25 Delco Electronics Corporation Motor vehicle radio with an automatic volume control device
US5012491A (en) * 1988-08-05 1991-04-30 Nec Corporation Preamable detection circuit for digital communications system
US4879728A (en) * 1989-01-31 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories DPSK carrier acquisition and tracking arrangement
US5018166A (en) * 1989-10-10 1991-05-21 Hayes Microcomputer Products, Inc. Method and apparatus for baud timing recovery
US5040192A (en) * 1990-02-06 1991-08-13 Hayes Microcomputer Products, Inc. Method and apparatus for optimally autocorrelating an FSK signal
US5274670A (en) * 1991-03-01 1993-12-28 Kabushiki Kaisha Toshiba Method of equalization in digital mobile communication with improved tracking ability
US5263026A (en) * 1991-06-27 1993-11-16 Hughes Aircraft Company Maximum likelihood sequence estimation based equalization within a mobile digital cellular receiver
US5272446A (en) * 1991-11-29 1993-12-21 Comsat Digitally implemented fast frequency estimator/demodulator for low bit rate maritime and mobile data communications without the use of an acquisition preamble
US5276706A (en) * 1992-05-20 1994-01-04 Hughes Aircraft Company System and method for minimizing frequency offsets between digital communication stations
WO1994019704A1 (fr) * 1993-02-26 1994-09-01 Fujitsu Limited Appareil a mesurer la vitesse de mouvement d'un systeme de communication mobile

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0845174A1 (fr) * 1995-08-18 1998-06-03 Adtran Procede de codage et traitement du signal pour accroitre la portee des transmissions sur une ligne telephonique deux fils sans repeteurs
EP0845174A4 (fr) * 1995-08-18 2001-05-16 Adtran Procede de codage et traitement du signal pour accroitre la portee des transmissions sur une ligne telephonique deux fils sans repeteurs
WO1998009384A1 (fr) * 1996-08-28 1998-03-05 Nokia Telecommunications Oy Procede pour commander la puissance et systeme de radiocommunication cellulaire
AU724693B2 (en) * 1996-08-28 2000-09-28 Nokia Telecommunications Oy Power control method and cellular radio system
US6272355B1 (en) 1996-08-28 2001-08-07 Nokia Telecommunications Oy Power control method and cellular radio system
CN1096762C (zh) * 1996-08-28 2002-12-18 诺基亚电信公司 功率控制方法和蜂窝无线系统

Similar Documents

Publication Publication Date Title
US5400368A (en) Method and apparatus for adjusting the sampling phase of a digitally encoded signal in a wireless communication system
US5436942A (en) Method of equalizing digitally encoded signals transmitted in a plurality of non-contiguous time slots
US5241545A (en) Apparatus and method for recovering a time-varying signal using multiple sampling points
US5581579A (en) Method and apparatus to adaptively control the frequency of reception in a digital wireless communication system
US5491726A (en) Method and apparatus to determine the frequency and time slot position in a digital wireless communication session
KR960006476B1 (ko) 이동 디지탈 셀룰라 수신기의 최대 공산 순차 추정에 기초한 등화 방법
CA2071869C (fr) Methode et dispositif d'extraction de porteuse a temps de reponse determine par les caracteristiques de la porteuse
US5241688A (en) Frequency and time slot synchronizaton using adaptive filtering
EP0605188A2 (fr) Synchronisation de symbole et de trame pour un système TDMA
JP3220144B2 (ja) シリアル・データ・システムでの時間変動する信号を回復するための装置及び方法
CA2065638A1 (fr) Circuit d'echantillonnage et de determination de frequence de porteuse pour detecteurs sinusoidaux-cosinusoidaux
JP2001504670A (ja) セルラー通信システムにおける移動局の速度推定方法
JP2002532006A (ja) 復号シンボルを用いる適応性チャンネルの特性化
CA2065647A1 (fr) Detecteur differentiel du type tangentiel pour signaux modules par deplacement de phase en quadrature codes differentiellement
AU619944B2 (en) A method of controlling the frequency of a coherent radio receiver and apparatus for carrying out the method
JP3469206B2 (ja) 適応等化機能を備える時分割多元接続（ｔｄｍａ）通信システム
AU682700B2 (en) Digital radio communication equipment
US5361400A (en) Apparatus and method for removing distortion in a received signal
US5438595A (en) Method of estimating the speed of a mobile unit in a digital wireless communication system
US5970102A (en) Circuit and method for detecting frequency correction burst in TDMA digital mobile communication system
AU724387B2 (en) Compensation of doppler shift in a mobile communication system
US5677934A (en) Multipath propagation compensation in a TDMA system
AU636263B2 (en) Frequency and time slot synchronization using adaptive filtering
WO1995005705A1 (fr) Systeme de transmission numerique sans fil et procede de fonctionnement associe
US6038270A (en) Radio receiver apparatus and radio receiving method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA