WO1994027363A1

WO1994027363A1 - Circuitry for amplifier

Info

Publication number: WO1994027363A1
Application number: PCT/DE1994/000569
Authority: WO
Inventors: Jürgen OEHM
Original assignee: Telenorma Gmbh
Priority date: 1993-05-18
Filing date: 1994-05-12
Publication date: 1994-11-24
Also published as: DE4316550C1

Abstract

Two differential voltage-controlled current sources are applied on a substrate by CMOS technology. Each current source has an inverting and a non-inverting input. One current source is designed as an input element (E) and the other current source is designed as a load element (L). The output of the current source designed as an input element (E) and the output of the current source designed as a load element (L) are connected to each other and to a device (A) for calculating the arithmetic difference between both output currents. The output of the device (A) is connected to an input of the load element (L), causing a negative feedback. With this circuitry, an amplifier may be produced which, when properly designed, is characterised by high linearity.

Description

Circuit arrangement for an amplifier

The invention relates to a circuit arrangement for an amplifier, consisting of differential voltage-controlled current sources each having a constant current source, each having an inverting and a non-inverting input and two outputs, one, one

Current source forming input element is connected to a further current source which acts as an active resistance simulation and forms a load element. Such a circuit arrangement is already known. PCT application WO 86/07215 describes an amplifier which is formed from two transconductance amplifiers of the same type, the outputs of the same name of the two amplifiers being connected to one another. One of both

The amplifier acts as an input amplifier, while the other amplifier, whose inputs are connected to the two outputs of the two transconductance amplifiers in terms of negative feedback, acts as an active resistance simulation. About the

Common mode at the two outputs of the known

The above-mentioned document cannot be used as an amplifier

Take notes, as well as its other properties.

The object of the invention is now to design an amplifier of the type mentioned in which the influences such as noise and statistical

Impairment effects on analog parameters, such as B.

Input noise, statistical offset behavior, etc.,

be kept as low as possible. This object is achieved in that the load element (L) is designed such that the (to the maximum value of

Output voltage) related output quantity x ₂ of (on the

Maximum value of the input voltage) related input variable x ₁ follows according to the formula

In the special case C = 1, the total pays off

Transfer function of the amplifier linear, although that

Both the input and the load element pass through their entire non-linear characteristic.

Advantageous developments of the invention result from the subclaims.

The invention is explained in more detail using several exemplary embodiments.

It shows:

1 shows a transconductance element in P-channel technology,

2 shows a transconductance element in N-channel technology, FIG. 3 shows the interconnection of two differential voltage-controlled current sources according to the invention,

4 shows a simplified representation of the interconnection, FIG. 5 shows the small signal behavior of the amplifier according to the invention,

Fig. 6 shows the amplifier according to the invention with asymmetrical

Output carried out by means of a phase reversal and

Adding stage,

Fig. 7 the amplifier according to the invention with asymmetrical

Output implemented by means of a current mirror circuit, Fig. 8 additional wiring options of the amplifier according to the invention and

Fig. 9 the amplifier according to the invention with symmetrical

Output implemented with an adjustable symmetrical current source circuit.

The two basic circuits of a differential voltage controlled current source are shown in FIGS. 1 and 2, wherein the differential voltage controlled current source shown in FIG. 1 is implemented in P-channel technology and the differential voltage controlled current source shown in FIG. 2 is implemented in N-channel technology. Such differential voltage controlled current sources are known. The specialist decides which technology is more suitable for the individual application. In the further exemplary embodiments, generally only one technique is assumed, but the invention can be used independently of a certain technique.

In its simplest design, a differential voltage-controlled current source has at least three transistors. In CMOS technology, a transistor T3 is connected with its source connection and with its gate connection to a fixed reference voltage, for example U _p (FIG. 1). The transistor T3 forms a constant current source, the current of which is equal to the

Reference voltage U _{p is} determined. At the drain connection of the

Transistor T3, the two transistors T1 and T2 are each connected to their source connection. At the respective gate connection of the two transistors T1 and T2

Input voltage of connections + and - applied. An output current I1 and I2 flows at the respective drain connection of the transistors T1 and T2.

The current fed in by the constant current source (T3) is divided into the outgoing current paths. The sum of up dividing flowing currents corresponds to the output current I _{ref of} the transistor T3. The controlled current sources (T1 and T2) in the outgoing current paths are identical. The distribution of the currents (I ₁ and I ₂ ) in the two outgoing current paths can be influenced via a suitable control variable via the input of the differential voltage-controlled current source. The functional relationship between the distribution of the currents in the outgoing current paths and the control variable at the control input (+) and (-) depends on the functional control relationships of the controlled current sources used in the outgoing current paths.

The basic principle is explained in FIG. 3. There are two

Differential voltage-controlled current sources E and L are available, which have a differential voltage-controlled structure

1 or 2 correspond to the current source. The two current outputs of a differential voltage-controlled current source E and L are each connected to a device AE or AL for forming the arithmetic difference, the outputs of which

summarized and with the non-inverting input of the differential voltage-controlled acting as load element L.

Power source are connected. The one differential voltage controlled current source acts as input element E and the second differential voltage controlled current source acts as load element L.

In the _{event of} a differential voltage U _e at the input _element E, the associated current I _out1 flows from its current source _output and is absorbed by the current source _{output of} the load element L due to the circuit requirement. In order for this to work in a suitable manner, one must be established via the output potential of the current source outputs at the inverting input (-) of the load element L, based on the non-inverting input (+) of the load element L.

Set differential voltage U _a . The input _element works according to the function I _out1 = f (U _e ) and the load element L with the inverse function U _a = f (-I _out1 ). With knowledge of the function and inverse function of both elements E and L, the

Specify the transfer function of the overall arrangement U _a = f (U _e ). In conjunction with an arithmetic output stage AE or AL, which simulates the functional according to equation (1), the differential voltage-controlled current source E or L forms a so-called MOS operations transconductance amplifier (OTA).

Here, b is a constant based on a geometry ratio, which has the value "1" in connection with the circuit according to FIGS. 6, 7, 8 and 9. The static

The transfer function of a MOS operation transconductance amplifier results from the equation:

()

The following applies to the transfer function of the circuit arrangement according to FIG. 3, resulting from the respective transfer functions of the individual components according to equation (2):

The index "1" is used in the following to designate sizes of the input element (E) and the index "2" to designate sizes of the load element L. Calculates for the special case C = 1

Replacement sheet According to equation (6), the entire transfer function of the circuit arrangement according to the invention is linear, although the input element E and the load element each pass through their entire non-linear characteristic. With C = 1 the following results for equation 6: x ₂ = —sign (x ₁ ) · x ₁ . (10)

That means z. B. input and load element with the

Design C = 1 operated ( _{i.e. e.g.} I _ref1 = I _ref2 and b ₁ = b ₂ ), then with the same or different design of the transistor _{geometries of the input element} E, compared to that of the load element L, there is a linear transmission relationship between the Differential voltage at the input element E and the differential voltage at the inputs of the load element L.

Design _example : If I _choose I _ref1 = I _ref2 = 1μA and b ₁ = b ₂ , then C = 1 (linear amplification) applies. Is also a

Reinforcement of V = 4 is required and applies e.g. B. U _emax = 0.1V, see above

For a technology with T _ox = 40nm, the result is z. B for a circuit _{listing of} the input and load elements with N-channel transistors for a given channel length of L _eff1 = L _eff2 = 20μm for W _eff1 = 96μm and for W _eff2 - 6μm.

By describing the amplifier about each

Components follows according to equation (6) that, if suitable

Dimensioning of the structure according to FIG. 3 inverting or non-inverting amplification or damping is possible. For C = 1, the transfer function is linear in the amplifying or damping case within the limits of U _emax and U _amax . For example, you can use these two values

Design factor I _{ref be} determined, the maximum values being limited by the supply voltage and the necessary common-mode ranges for the elements E and L within the circuit. The upper limit of the maximum possible gain with C = 1 is also given:

For the circuit arrangement with any C values, the following applies to the small signal amplification V at the operating point I _r = I _l = I _ref / 2:

Since I _ref1 and I _{ref2 are} also in a fixed relationship to one another via the geometric ratio of a current mirror, the gain V is ultimately only determined by the geometric relationships of MOS transistors and is therefore independent of the operating point, supply voltage, temperature or other parameters. The following applies to FIGS. 3, 6, 7 and 8:

To make transistors T13 and T23 suitable for the previous one

To interpret the example given would be e.g. B. following

Sizing conceivable:

b ₁ and b ₂ are also determined only by geometric relationships and have those shown in FIGS. 6, 7, 8 and 9

Circuits the value one. In particular, the two

Elements E and L have different common mode operating points without the transfer function according to equation (6) and thus the small signal gain being influenced thereby. This is due to the common mode independence of equation (2). Applying equation (12a) to the above

Example, the following applies:

This shows that the specification "linear amplification of large signals with V = 4" is also operated by the general equation (12a) for small signal amplification.

If equation (12) is analyzed, it becomes clear that the gain of the circuit arrangement can be placed on the one hand in the geometric relationships of the differential transistors of the elements E and L and / or on the other hand in the ratio of the reference currents of the elements E and L. Von der Adjustment of the gain via b ₁ / b ₂ should not be used for circuitry reasons. The result would be a deterioration in the characteristic behavior due to additional statistical effects of inconsistency and noise.

In Fig. 3 it is shown that each element E and L has its own device AE and AL for forming the arithmetic difference between the two output currents, the outputs of the two devices AE and AL being combined. After the

Circuit arrangements according to FIGS. 6, 7 and 8, however, it is possible to dispense with an individual device AE and AL and instead to combine the outputs of the same name of the two elements E and L and a common device A for forming the arithmetic difference between the

To supply output currents. The output of the device A is in turn connected to an input of the load element L.

The difference formation of the branch currents of the individual elements E and L, which would normally have to be carried out for each element in accordance with equation (1), is therefore carried out only once, which, in addition to the lower outlay, brings about a gain in accuracy in current arithmetic. There is no freedom to choose the current factors b ₁ and b ₂ as desired. In the following description they are used with the value 1.

The device A for forming the arithmetic difference I _out according to FIG. 6 is using a common one

Phase inversion and adding stage, and the device A for

The arithmetic difference ∑ I _out according to FIG. 7 is formed using a common current mirror circuit. 9, the arithmetic difference die I _{out flows} according to equation (13) between the

Current inputs and outputs.

Note: In the amplifier according to the invention ∑ I _o ut = 0.

The transformation according to equations (13) shows that

branch currents of the same name in terms of circuitry directly

can be summarized. However, the following must apply:

When using a common device for the formation of the arithmetic difference, it follows:

The above equation is proof that equation (6) is valid both for the amplifier according to the invention with symmetrical and with asymmetrical output.

For additional influences such as noise and

To keep statistical impairment effects - which inevitably arise at b ₁ = b ₂ ≠ 1 through additional current mirrors - as low as possible, the following applies: if b ₁ = b ₂ , then always apply: b ₁ = b ₂ = 1 The decisive difference between the two circuit variants according to FIG. 6 and FIG. 7 is not only statically seen in the different effort, but also in

Common mode behavior and in the output resistance r _out . In the considerations idealized so far, the output resistance was simplified

In practical implementation, the current arithmetic of the output stage has an approximation due to the channel length modulation of all transistors at the "OUT" node

Power source characteristics. It generally applies to all basic circuit variants:

Here, α is the quiescent current ratio T36 / T35 (FIG. 6).

Here g _{m is} the small signal steepness of an element E or L and g _{out is} the output conductance of the current arithmetic. In the current mirror circuit and in the device K, α is always 1.

The decisive advantage for the accuracy of the gain setting when using the phase inversion and adding stage for the current arithmetic, in contrast to the current mirror, lies in the complete decoupling of the g _{DS influence of} the transistors of the elements E and L on the output resistance r * _out . The slopes gml and gm2, on the other hand, appear transformed by the value at the exit. By using cascode current mirrors for the current arithmetic, the effect of g _DSN and 9 _{DSP of} the two output transistors of the phase inversion and adding stage is negligible; equation (16) then changes to equation (12) with b ₁ = b ₂ = 1. 8 further circuit variants are explained. The capacitor C1, which is connected between the output of the device A to form the arithmetic difference and against ground, makes it possible to provide a defined band limitation of the amplifier and at the same time to achieve the stability of the amplifier. If the device A for forming the arithmetic difference is designed as a simple current mirror arithmetic, the arrangement works stably even without the capacitor.

If the output signal of the device A or K is too heavily loaded to form the arithmetic difference, then the output or the outputs of the device can each with the

Input of a buffer B are connected, the respective output of which is connected to an input of the load element L directly or indirectly via a direct current path in the sense of a

Negative feedback is connected.

If a signal inversion takes place in the buffer B, then the other input of the load element L is with the output of the

Connect Buffers B. It applies in general to all the applications discussed so far that the input of the load element must always be connected to the output potential of the elements E and L, so that a negative feedback effect arises.

The respective output of a buffer B or the output of device A or the outputs of device K to form the arithmetic difference can also be via a real or complex active or passive network

Negative feedback with the input or inputs of the

Be load element L connected, for example via a

Resistor R2 with an input of the load element 2, an AC signal path to the signal ground from this input via a further resistor R1. Through this

Resistance feedback consisting of resistors R1 and R2, the gain can be increased independently of the internal gain gml / gm2. Especially for the case C = 1 Transfer function linear within the voltage limits Uemax and u * _amax according to equation (18).

In the case of the design example "linear amplification of large signals with V = 4" applies e.g. B. for the case R1 = R2:

U ^* _amax = 2 · U _amax = 0.8Volt

The new overall gain V ** is now:

Equations (18) and (18a) are also valid if: b ₁ = b _2. For the design example "linear amplification of large signals with V = 4", z. B. with R1 = R2: V ** = 2. V = 8

The effective reference current of the current source transistors T13 and T23 can be influenced via the transistors T14 and T24 (FIG. 8):

With the change of I * _ref , all associated properties of the differential voltage controlled current sources change.

9, the outputs of the transistors TU and T21 or the outputs of the transistors T12 and T22 of the elements E and L are combined and connected to an input of the load element L. The application of this

Circuitry is not limited to the construction of elements E and L according to FIG. 9; it is also applicable in the construction of the Elements E and L according to Fig. 6, 7 or 8. This is used for

Formation of a current source with balanced outputs. This measure results in high suppression values for the

Common mode and the operating voltage penetration reached. However, this creates the disadvantage of a symmetrical one

Output arithmetic, namely that the direct selectability of the common mode position of the output differential voltage U _{a is lost} by external wiring. The compensation circuit K eliminates this disadvantage within a certain range via a further control process. The reference _voltage u _{ref1 is used for this} . All derived relationships for the basic principle according to FIGS. 6 and 7 between the input voltage U _e and the output voltage U _a remain valid here as well. This applies in particular to the static transmission behavior according to equation (6) and the associated distortion behavior. The dynamic relationships are identical in the formation of the principle with symmetrical or asymmetrical outputs in conjunction with an additional capacitance C1, if

It is taken into account that in the case of symmetrical outputs the capacitor C1 must be parallel to the output voltage U _a or C 1/2 of the outputs according to GND or V _dd .

The two elements E and L according to FIG. 9 also differ from the previously shown embodiments by the different design of the constant current source. So far, a common transistor T13 and T23 was present for an element E and L, respectively. By dividing the current source into two current sources, each of which supplies half the constant current, it is possible to connect the outputs of the two constant current sources T15 and T16 or T25 and T26

to connect passive or also active network to one another, as is shown for element E by transistors T17 and T18 and for element L by transistors T27 and T28. The use of a passive or active network connecting the two current sources to one another increases the linear range. At the same time, this measure also increases the common mode sensitivity due to the growing influence of the substrate Effect. Measures to linearize the amplification behavior of the elements via the degeneracy of the coupling between the input transistors have the inherent disadvantage of the increasing penetration of local statistical inconsistency effects and noise influences on the electrical parameters of the circuit.

From the point of view of dynamic and statistical properties of the electrical parameters of a circuit, structures are those which are improved by suitable superimposition of the effect of square MOS input characteristics

Achieve linearity, much cheaper than structures that achieve the same nominal linearity by degenerating the coupling of the input transistors.

In the embodiment according to FIG. 9, it is also conceivable to influence half the constant current by connecting one transistor to each of the two current sources (T15, T16), as will be explained with reference to FIG. 8 (transistor T13).

The circuit arrangement according to FIG. 9 can also be used

Buffer stages B are operated, as was explained with reference to FIG. 8. In this case, both outputs are the

Circuit K with a buffer stage B and its output is connected to the corresponding input of the

To connect load element L directly or indirectly.

Claims

PATENT CLAIMS:

1. Circuit arrangement for an amplifier, consisting of

each having a constant current source,

Differential voltage-controlled current sources, each with an inverting and a non-inverting input and two outputs each, one current source forming an input element with another, as the active one

Resistance simulation acting current source forming a load element is connected,

characterized,

that the load element (L) is designed such that the output variable x ₂ (based on the maximum value of the output voltage) follows the input variable x ₁ (based on the maximum value of the input voltage) according to the formula

2nd Circuit arrangement according to claim 1,

characterized in that

that the product from the respective output stream of

Constant current source of one element evaluates the product of the respective with a first constant (b1)

Output current of the constant current source of the other element corresponds to a second constant (b2), where the real constants (b1, b2) evaluate the arithmetic difference of the output currents of an element.

3. Circuit arrangement according to one of claims 1 or 2,

characterized,

that the constants (b1, b2) are firmly stamped.

4. amplifier according to one of claims 1 or to 3,

characterized,

that the small signal gain (V) from the formula

calculated.

5. Circuit arrangement according to one of claims 1 to 4,

characterized,

that the similar outputs of the input element (E) and the load element (L) are combined and each have an input of a circuit (A) to form the

arithmetic difference of the two output currents of the two current sources is connected, the output signal of the circuit (A) the inverting input (-) of the

Load element (L) is supplied and forms the output signal of the amplifier.

6. Circuit arrangement according to one of claims 1 to 5,

characterized,

that the circuit (A) to form the arithmetic

Difference of the output currents as phase reversal and

Adding stage is formed.

7. Circuit arrangement according to one of claims 1 to 5,

characterized,

that the circuit (A) is designed as a current mirror.

8. Circuit arrangement according to one of claims 1 to 7,

characterized, that the output signal of the circuit (A) is fed to a buffer stage (B), the output of which is connected directly or indirectly to the inverting input (-) of the load element (L).

9. Circuit arrangement according to claim 8,

characterized,

that the buffer stage (B) is designed as a signal inversion stage, the output of which is connected directly or indirectly to the non-inverting input (+) of the load element (L).

10. Circuit arrangement according to one of claims 1 to 9,

characterized,

that the output of the circuit (A) or the output of the

Buffer stage (B) is connected via a real or complex resistor (R2) to an input of the load element (L), with another real or complex resistor (Rl) between the two inputs of the load element (L)

connected.

11. Circuit arrangement according to one of claims 1 to 10,

characterized,

that the output of the circuit (A) is connected to ground or to a supply voltage via a capacitor (Cl).

12. Circuit arrangement for an amplifier, consisting of

each having a constant current source,

Differential voltage-controlled current sources, each with an inverting and a non-inverting input and two outputs each, one current source forming an input element with another being active

Resistance replica acting, a load element forming current source is connected by the similar outputs of the input element and the load element, respectively

summarized and each with an input of

Load element are connected accordingly, characterized,

that parallel to the two inputs of the load element (L) with their two inputs a circuit (K) for

Influencing the size of the current present at the respective input is connected.

13. Circuit arrangement according to one of claims 1 to 12,

characterized,

that the constant current source is formed from two transistors (T15, T16), that in each case a voltage-controlled

Transistor (T11, T12) on one of the two transistors

(T15, T16) of the constant current source is connected and that the outputs of the two constant current sources are connected to one another via an active or passive network (T17, T18).

14. Circuit arrangement according to one of claims 1 to 13,

characterized,

that with the power source (T13, T23) or the two

Current sources (T15 / T16, T25 / T26) another transistor

(T14, T24) or respectively a further transistor is connected, via which or which the output current of the

Current source (T13, T23) or current sources (T15 / T16, T25 / T26) is changeable.

15. Circuit arrangement according to one of claims 12 to 14, characterized in

that a capacitor is connected to each other or to ground or to a supply voltage to the two outputs of the circuit (K).

16. Circuit arrangement according to one of claims 12 to 15, characterized in

that the circuit (K) is designed as a symmetrical current source with two outputs.

17. Circuit arrangement according to one of claims 12 to 16, characterized in that a buffer stage is connected to each of the two outputs of the circuit (K) and that the outputs of the buffer stages are connected directly or indirectly to the inputs of the load element (L) in the sense of negative feedback.