WO1994023414A1

WO1994023414A1 - System for driving an electronic display

Info

Publication number: WO1994023414A1
Application number: PCT/US1994/001680
Authority: WO
Inventors: Barry W. Herold
Original assignee: Motorola, Inc.
Priority date: 1993-03-31
Filing date: 1994-02-14
Publication date: 1994-10-13
Also published as: AU6392394A; TW237538B; CN1096882A

Abstract

A method and apparatus process frames of data to drive an actively addressed display (100) having pixels (108) controlled by first and second groups (104, 106) of electrodes. The apparatus comprises a first processor and a second processor including a digital buffer memory (606, 608) and a drive signal generator (610, 612). A first frame of data representing pixel values is loaded (1204) by the first processor into the digital buffer memory (606) while the second processor concurrently calculates (1206) first electrode drive signals for a time slot (t). The first electrode drive signals are calculated as a function of second electrode drive signals for the time slot (t) and selected pixel values for pixels (108) collectively controlled by a corresponding first electrode (104). The selected pixel values are from a second frame of data loaded during a preceding transmission.

Description

SYSTEM FOR DRIVING AN ELECTRONIC DISPLAY

Field of the Invention

This invention relates in general to electronic displays, and more specifically to a method and apparatus for driving high information content, direct multiplexed, rms responding electronic displays.

Background of the Invention

An example of a direct multiplexed, rms responding electronic display is the well-known liquid crystal display (LCD). In such displays, a nematic liquid crystal material is positioned between two parallel glass plates having electrodes applied to each surface in contact with the liquid crystal material. The electrodes typically are arranged in vertical columns on one plate and horizontal rows on the other plate for driving a picture element (pixel) wherever a column and row electrode overlap. A high information content display, e.g., a display used as a monitor in a portable laptop computer, requires a large number of pixels to portray arbitrary patterns of information. Matrix LCDs having 480 rows and 640 columns forming 307,200 pixels are widely used in computers today, and matrix LCDs with millions of pixels are expected soon.

In so-called rms responding displays, the optical state of a pixel is substantially responsive to the square of the voltage applied to the pixel, i.e., the difference in the voltages applied to the electrodes on the opposite sides of the pixel. LCDs have an inherent time constant that characterizes the time required for the optical state of a pixel to return to an equilibrium state after the optical state has been modified by changing the voltage applied to the pixel. Recent technological advances have produced

LCDs with time constants approaching the frame period used in many video displays (approximately 16.7 milliseconds). Such a short time constant allows the LCD to respond quickly and is especially advantageous for depicting motion without noticeable smearing of the displayed image.

Conventional direct multiplexed addressing methods for LCDs encounter a problem when the display time constant approaches the frame period. The problem occurs because conventional direct multiplexed addressing methods subject each pixel to a short duration "selection" pulse once per frame. The voltage level of the selection pulse is typically 7-13 times higher than the rms voltage averaged over the frame period. The optical state of a pixel in an LCD having a short time constant tends to return towards an equilibrium state between selection pulses, resulting in lowered image contrast, because the human eye integrates the resultant brightness transients at a perceived intermediate level. In addition, the high level of the selection pulse can cause alignment instabilities in some types of LCDs.

To overcome the above-described problems, an "active addressing" method has been developed. The active addressing method continuously drives the row electrodes with signals comprising a train of periodic pulses having a common period T corresponding to the frame period. The row signals are independent of the image to be displayed and preferably are orthogonal and normalized, i.e., orthonormal. The term orthogonal denotes that if the amplitude of a signal applied to one of the rows is multiplied by the amplitude of a signal applied to another one of the rows, the integral of this product over the frame period is zero. The term normalized denotes that all the row signals have the same rms voltage integrated over the frame period T.

During each frame period a plurality of signals for the column electrodes are calculated and generated from the collective state of the pixels in each of the columns. The column voltage at any time t during the frame period is proportional to the sum obtained by considering each pixel in the column, multiplying a "pixel value" representing the optical state (-1 representing fully "on", +1 representing fully "off", and values between -1 and +1 representing proportionally corresponding gray shades) of the pixel by the value of that pixel's row signal at time t, and adding the products obtained thereby to the sum. If the orthonormal row signals switch between only two row voltage levels (+1 and -1), the above sum may be represented as the sum of the pixel values corresponding to rows having the first row voltage level, minus the sum of the pixel values corresponding to rows having the second row voltage level. If driven in the active addressing manner described above, it can be shown mathematically that there is applied to each pixel of the display an rms voltage averaged over the frame period, and that the rms voltage is proportional to the pixel value for the frame. The advantage of active addressing is that it restores high contrast to the displayed image, because instead of applying a single, high level selection pulse to each pixel during the frame period, active addressing applies a plurality of much lower level (2-5 times the rms voltage) selection pulses spread throughout the frame period. In addition, the much lower level of the selection pulses substantially reduces the probability of alignment instabilities.

A problem with active addressing results from the large number of calculations required per second. For example, a gray scale display having 480 rows and 640 columns, and a frame rate of 60 frames per second requires just under ten billion calculations per second. While it is of course possible with today's technology to perform calculations at that rate, the architectures proposed to date for calculation engines used for actively addressed displays have not been optimized to minimize power consumption. The power consumption issue is particularly important in portable applications, such as battery-powered laptop computers, in which battery life is a primary design consideration.

Thus, what is needed is a method and apparatus for driving an actively addressed display in a manner that minimizes the power consumption of the required calculation engine.

Summary of the Invention

One aspect of the present invention is a method in a processing system for processing successively transmitted frames of data for driving an actively addressed display.

The display comprises pixels controlled by a plurality of first and second electrodes, and the processing system comprises a first processor and a second processor, the first and second processors including a digital buffer memory and a drive signal generator. The method comprises the steps of (a) loading by the first processor a first frame of data representing a plurality of pixel values into the digital buffer memory, and (b) calculating by the second processor concurrently with step (a) one of a plurality of first electrode drive signals for one of the plurality of first electrodes for a time slot of a predetermined number of time slots. The one of the plurality of first electrode drive signals is calculated as a function of a plurality of predetermined second electrode drive signals for the time slot and a selected plurality of pixel values for pixels collectively controlled by the one of the plurality of first electrodes. The selected plurality of pixel values are from a second frame of data loaded during a preceding transmission.

Another aspect of the present invention is a processing system for processing successively transmitted frames of data for driving an actively addressed display. The display comprises pixels controlled by a plurality of first and second electrodes. The processing system comprises a first processor including a first digital buffer memory for loading and storing a first frame of data representing a first plurality of pixel values. The processing system further comprises a second processor coupled to the first processor for coordination therewith. The second processor includes a second digital buffer memory for loading and storing a second frame of data representing a second plurality of pixel values. The first and second processor further comprise a drive signal generator including a calculation engine for coupling to the first and second digital buffer memories for calculating from a frame of data contained therein one of a plurality of first electrode drive signals for one of the plurality of first electrodes. The drive signals are calculated for a time slot of a predetermined number of time slots. The one of the plurality of first electrode drive signals is calculated as a function of a plurality of predetermined second electrode drive signals for the time slot and a selected plurality of pixel values for pixels collectively controlled by the one of the plurality of first electrodes. Another aspect of the present invention is an electronic device, comprising electronic circuitry for generating information comprising successively transmitted frames of data, and an enclosure coupled to the electronic circuitry for supporting and protecting the electronic circuitry. The electronic device further comprises an actively addressed display coupled to the electronic circuitry for displaying the information therefrom, and the actively addressed display comprises pixels controlled by a plurality of first and second electrodes. The electronic device further comprises a processing system coupled to the electronic circuitry for processing the information for driving the actively addressed display. The processing system comprises a first processor including a first digital buffer memory for loading and storing a first frame of data representing a first plurality of pixel values, and a second processor coupled to the first processor for coordination therewith. The second processor includes a second digital buffer memory for loading and storing a second frame of data representing a second plurality of pixel values. The first and second processor further comprise a drive signal generator including a calculation engine for coupling to the first and second digital buffer memories for calculating from a frame of data contained therein one of a plurality of first electrode drive signals for one of the plurality of first electrodes. The drive signals are calculated for a time slot of a predetermined number of time slots. The one of the plurality of first electrode drive signals is calculated as a function of a plurality of predetermined second electrode drive signals for the time slot and a selected plurality of pixel values for pixels collectively controlled by the one of the plurality of first electrodes.

Brief Description of the Drawings

FIG. 1 is a front orthographic view of a portion of a conventional liquid crystal display. FIG. 2 is an orthographic cross-section view along the line 2-2 of FIG. 1 of the portion of the conventional liquid crystal display.

FIG. 3 is an eight-by-eight matrix of Walsh functions in accordance with the preferred embodiment of the present invention.

FIG. 4 depicts drive signals corresponding to the Walsh functions of FIG. 3 in accordance with the preferred embodiment of the present invention.

FIG. 5 is an electrical block diagram of a display system in accordance with the preferred embodiment of the present invention.

FIG. 6 is an electrical block diagram of a processing system of the display system in accordance with the preferred embodiment of the present invention. FIG. 7 is an electrical block diagram of an rms correction factor calculator of the processing system in accordance with the preferred embodiment of the present invention.

FIG. 8 is an electrical block diagram of a calculation engine of the processing system in accordance with the preferred embodiment of the present invention. FIG. 9 is an electrical block diagram of a controller of the processing system in accordance with the preferred embodiment of the present invention.

FIG. 10 is an electrical block diagram of a personal computer in accordance with the preferred embodiment of the present invention.

FIG. 11 is a front orthographic view of the personal computer in accordance with the preferred embodiment of the present invention. FIG. 12 is a flow chart depicting the operation of the display system in accordance with the preferred embodiment of the present invention.

FIG. 13 is a flow chart depicting the operation of the rms correction factor calculator in accordance with the preferred embodiment of the present invention.

FIG. 14 is a flow chart depicting the operation of the calculation engine in accordance with the preferred embodiment of the present invention.

Description of the Preferred Embodiment

Referring to FIGs. 1 and 2, orthographic front and cross-section views of a portion of a conventional liquid crystal display (LCD) 100 depict first and second transparent substrates 102, 206 having a space therebetween filled with a layer of liquid crystal material 202. A perimeter seal 204 prevents the liquid crystal material from escaping from the LCD 100. The LCD 100 further includes a plurality of transparent electrodes, comprising row electrodes 106 positioned on the second transparent substrate 206, and column electrodes 104 positioned on the first transparent substrate 102. At each point at which a column electrode 104 overlaps a row electrode 106, such as the overlap 108, voltages applied to the overlapping electrodes 104, 106 can control the optical state of the liquid crystal material 202 therebetween, thus forming a controllable picture element (pixel). While an LCD is the preferred display element in accordance with the preferred embodiment of the present invention, it will be appreciated that other types of display elements may be used as well, provided that such other types of display elements exhibit an optical characteristics responsive to the square of the voltage applied to each pixel, similar to the rms response of an LCD.

Referring to FIGs. 3 and 4, an eight-by-eight (third order) matrix of Walsh functions 300 and the corresponding Walsh waves 400 in accordance with the preferred embodiment of the present invention are shown. Walsh functions are orthonormal and are thus preferable for use in an actively addressed display system, as discussed in the Background of the Invention herein above. When used in such a display system, voltages having levels represented by the Walsh waves 400 are uniquely applied to a selected plurality of electrodes of the LCD 100. For example, the Walsh waves 404, 406, and 408 could be applied to the first (uppermost), second, and third row electrodes 106, respectively, and so on. In this manner each of the Walsh waves 400 would be applied uniquely to a corresponding one of the row electrodes 106. It is preferable not to use the Walsh wave 402 in an LCD application, because the Walsh wave 402 would bias the LCD with an undesirable DC voltage. It is of interest to note that the values of the Walsh waves 400 are constant during each time slot t. The duration of the time slot t for the eight Walsh waves 400 is one-eighth of the duration of one complete cycle of Walsh waves 400 from start 410 to finish 412. When using Walsh waves for actively addressing a display, the duration of one complete cycle of the Walsh waves 400 is set equal to the frame duration, i.e., the time to receive one complete set of data for controlling all the pixels 108 of the display 100.

The eight Walsh waves 400 are capable of uniquely driving up to eight row electrodes 106 (seven if the Walsh wave 402 is not used) . It will be appreciated that a practical display has many more rows. For example, displays having four-hundred-eighty rows and six-hundred- forty columns are widely used today in laptop computers. Because Walsh function matrices are available in complete sets determined by powers of two, and because the orthonormality requirement does not allow more than one electrode to be driven from each Walsh wave, a five- hundred-twelve by five-hundred-twelve (2⁹ x 2⁹) Walsh function matrix would be required to drive a display having four-hundred-eighty row electrodes 106. For this case the duration of the time slot t is 1/512 of the frame duration. Four-hundred-eighty Walsh waves would be used to drive the four-hundred-eighty row electrodes 106, while the remaining thirty-two would be unused, preferably including the first Walsh wave 402 having a DC bias.

Referring to FIG. 5, an electrical block diagram of a display system 500 in accordance with the preferred embodiment of the present invention comprises a plurality of processing systems 510 coupled to a data input line 508, preferably eight bits wide, for receiving frames of data to be displayed. To reduce calculation requirements for each of the processing systems 510 the LCD 100 has been partitioned into eight areas 511 each serviced by one of the processing systems 510, and each containing one- hundred-sixty column electrodes 104 and two-hundred-forty row electrodes 106. The processing systems 510 are coupled by column output lines 512, preferably eight bits wide, to video digital-to- analog converters (DACs) 502, such as the model CXD1178Q DAC manufactured by Sony Corporation, for converting the digital output signals of the processing systems 510 into corresponding analog column drive signals. The DACs 502 are coupled to column drive elements 504 of an analog type, such as the model SED1779D0A driver manufactured by Seiko Epson Corporation, for driving the column electrodes 104 of the LCD 100 with the analog column drive signals. Two of the processing systems 510 are also coupled by row output lines 514 to row drive elements 506 of a digital type, such as the model SED1704 driver also manufactured by Seiko Epson Corporation, for driving the row electrodes 106 of the upper and lower partitions of the LCD 100 with a predetermined set of Walsh waves. It will be appreciated that other similar components can be used as well for the DACs 502, the column drive elements 504, and the row drive elements 506.

The column and row drive elements 504, 506 receive and store a batch of drive level information intended for each of the column and row electrodes 104, 106 for the duration of the time slot t (FIG. 4). The column and row drive elements 504, 506 then substantially simultaneously apply and maintain the drive levels for each of the column and row electrodes 104, 106 in accordance with the received drive level information until a next batch, e.g., a batch corresponding to the next time slot t, is received by the column and row drive elements 504, 506. In this manner the transitions of the drive signals for all the column and row electrodes 104, 106 occur substantially in synchronism with one another.

Referring to FIG. 6, an electrical block diagram of one of the processing systems 510 of the display system in accordance with the preferred embodiment of the present invention comprises the data input line 508 coupled to first and second write control logic elements 602, 604. The first and second write control logic elements 602, 604 comprise a conventional serial-to-parallel converter, a conventional counter, and conventional random access memory (RAM) control logic. The function of the first and second write control logic elements 602, 604 is to receive data comprising pixel states from the data input line 508, to convert the received data into data bytes, and to send the data bytes over the parallel busses 630 to the first and second buffer RAMs 606, 608 for storage. The data bytes within the first and second buffer RAMs 606, 608 are organized by the first and second write control logic elements 602, 604 into blocks, each block corresponding to substantially all the pixels 108 controlled by a single column electrode 104 and falling within the area 511 serviced by the processing system 510. A controller 622 is coupled by a control bus 624 to the first and second write control logic elements 602, 604 and to the first and second buffer RAMs 606, 608 for controlling their operation. The controller 622 is further coupled by the control bus 624, by a virtual value line 636, and by a first time slot line 637 to first and second calculation engines 610, 612 for controlling their operation. The controller 622 is further coupled by the control bus 624 to first and second row drive shift registers 614, 616 for controlling their operation also. The controller 622 is also coupled by the control bus 624 to an rms correction factor calculator 632 for controlling the rms correction factor calculator 632 and for receiving and storing correction factors calculated by and sent from the rms correction factor calculator 632. The rms correction factor calculator 632 is also coupled to the data input line 508 for monitoring the frames of data and calculating correction factors therefrom, as explained herein below regarding FIG. 7. A frame sync line 638 and a clock line 642 also are coupled to the controller 622 to provide synchronization for the controller 622.

The controller 622 coordinates the operation of the first and second write control logic elements 602, 604 such that the first and second write control logic elements 602, 604 alternate in processing the frames of data received from the data input line 508. That is, the first write control logic element 602 receives a frame of data and transmits the frame of data to the first buffer RAM 606. Then the second write control logic element 604 receives a next frame of data and transmits that frame of data to the second buffer RAM 608. Then the first write control logic element 602 receives a next frame of data and transmits that frame of data to the first buffer RAM 606, and so on, receiving and transmitting alternate frames of data. The first and second buffer RAMs 606, 608 are coupled by parallel data busses 634 to first and second calculation engines 610, 612 for calculating values for driving the column electrodes 104 for each Walsh wave time slot t. The parallel data busses 634 are sufficiently wide to transmit simultaneously pixel values for substantially all the pixels 108 controlled by a single column electrode 104 and falling within the partitioned area 511 serviced by the processing system 510. For example, in the processor 510 servicing two-hundred-forty rows and having eight-bit pixel values, the first and second parallel data busses 634 each must have one-thousand nine-hundred-twenty parallel paths. The structure and operation of the first and second calculation engines 610, 612 are described in greater detail herein below.

The first and second calculation engines 610, 612 are also coupled to first and second row drive shift registers 614, 616 by parallel transfer busses 636 for transferring the Walsh function values to the first and second calculation engines 610, 612. The parallel transfer busses 636 must be sufficiently wide to transfer a one-bit Walsh function value for each row serviced by the processing system 510. For example, in the processor 510 servicing two-hundred-forty rows, the parallel transfer busses 636 must have two-hundred-forty parallel paths. It will be appreciated that while Walsh functions are preferred, other orthonormal functions may be used as well by the first and second calculation engines 610, 612 to perform the calculations.

The function of the first and second row drive shift registers 614, 616 is to receive from the controller 622 the Walsh function values corresponding to the rows serviced by the processor 510 for each time slot t. Having received the Walsh function values for the time slot t, the first and second row drive shift registers 614, 616 then transfer the received Walsh function values for the time slot t to the first and second calculation engines 610, 612 for use in calculating column drive signals for the time slot, as described herein below. The first and second row drive shift registers 614, 616 also drive the row output line 514 with the Walsh function values corresponding to the rows serviced by the processor 510 for each time slot t.

The controller 622 coordinates the operation of the first and second calculation engines 610, 612 and the first and second row drive shift registers 614, 616 such that the first and second calculation engines 610, 612 and the first and second row drive shift registers 614, 616 alternate in processing the frames of data read from the first and second buffer RAMs 606, 608. That is, the first calculation engine 610 and the first row drive shift register 614 process a frame of data and drive the column output line 512 and the row output line 514 in accordance with the values calculated for the frame of data. Then the second calculation engine 612 and the second row drive shift register 616 process the next frame of data and drive the column output line 512 and the row output line 514 in accordance with the values calculated for that next frame of data. Then the first calculation engine 610 and the first row drive shift register 614 process the next frame of data and drive the column output line 512 and the row output line 514 in accordance with the values calculated for that frame of data, and so on, processing alternate frames of data.

The reason for the alternating processing taking place within the processing system 510 is so that while the first buffer RAM 606 is receiving a new frame of data, the second buffer RAM 608 can be delivering a previously received frame of data to the second calculation engine 612 for output, and vice versa. It will be appreciated that because the first and second calculation engines 610, 612 and the first and second row drive shift registers 614, 616 are each active only during alternate frames of data, one of the first and second calculation engines 610, 612 and one of the first and second row drive shift registers 614, 616 could be eliminated. This would of course require the addition of control and data routing circuitry to allow a single calculation engine to receive data alternately from both the first and second buffer RAMs 606, 608. For similar reasons, the first and second write control logic elements 602, 604 could be combined into a single write control logic element. For integrated circuit fabrication reasons, however, the preferred architecture is the fully duplicated architecture depicted in FIG. 6.

Referring to FIG. 7, an electrical block diagram of the rms correction factor calculator 632 of the processing system 510 in accordance with the preferred embodiment of the present invention comprises the data input line 508, for receiving input and control signals, and the control bus 624, for controlling the rms correction factor calculator 632. For a display using +1 to represent a fully "off" pixel and -1 to represent a fully "on" pixel, and using Walsh functions having values of only +1 and -1, the correction factor for each column of the display is

where N is the number of real rows, and I_± is the pixel value for the ith row of the column.

Adjusting for eight-bit pixel values having a range of 0-255, and assuming there are two-hundred-forty real rows, equation (1) becomes

which simplifies to

which simplifies further to

It is the function of the rms correction factor calculator 632 to calculate this correction factor for each column from the data arriving over the data input 508.

The rms correction factor calculator 632 further comprises a first accumulator 710 coupled to the data input line 508 for summing the pixel values received. The output of the first accumulator 710 is coupled to both inputs of a first subtracter 712, wherein the minuend input data is first shifted eight bits to the left to multiply the minuend input data by two-hundred-fifty-six, thus producing an output value of 255∑ I .

The data input line 508 is also coupled to the input of a first look-up table element 704 for determining the square of the pixel value. The output of the first look-up table element 704 is coupled to the input of a second accumulator 706 for summing the squares of the pixel values. The output of the second accumulator 706 is coupled to the subtrahend input of a second subtracter 708, to which the output of the first subtracter 712 is coupled at the minuend input for obtaining the difference 255∑I - ∑ I². The output of the second subtracter 708 is coupled to a second look-up table element 714 for determining the square root value

The output of the second look-up table element 714 is coupled to an input of a multiplier element 716. The other input of the multiplier element 716 is preprogrammed for a constant value K. The value of K provides for the division factor of 1975 from equation (4), as well as any other drive level adjustments that may be required for the LCD 100. The output of the multiplier element 716 is coupled by the control bus 624 to the controller 622 for storing the calculated correction factor. It will be appreciated that an arithmetic logic unit or a microcomputer can be substituted for some or all of the first and second look-up table elements 704, 714 and the multiplier element 716. It will be further appreciated that a microcomputer can also replace all the elements of the rms correction factor calculator 632.

Referring to FIG. 8, an electrical block diagram of one of the calculation engines 610, 612 of the processing system 510 in accordance with the preferred embodiment of the present invention comprises a plurality of 8-bit exclusive-OR (XOR) elements 802, 804, 806. The XOR elements 802, 804, 806 are coupled to the parallel data busses 634 for receiving pixel values from one of the buffer RAMs 606, 608, under the control of the controller 622. The XOR elements 802, 804, 806 are also coupled to the parallel transfer busses 636 for receiving Walsh function row values from one of the row drive shift registers 614, 616, also under the control of the controller 622. The function of the XOR elements 802, 804, 806 is to complement the bits of the pixel values whenever the corresponding row value is a logic ONE, and to leave the pixel value unchanged whenever the corresponding row value is a logic ZERO. A value of ONE must be added to each complemented pixel value (as explained herein below) in order to correctly subtract the pixel value from a sum being accumulated by the calculation engine 610, 612. The outputs of the XOR elements 802, 804, 806 are coupled to adder elements 808, 810, 812, which are coupled to each other, for generating a sum of the pixel values that have not been complemented by the XOR elements 802, 804, 806, and for subtracting from the sum the pixel values that have been complemented. The input of the first adder element 808 is coupled to the output 822 of a correction factor adjusting system, comprising elements 816, 818, 820 for adjusting the sign of the correction factor in accordance with the Walsh function value for the time slot for the virtual row element corresponding to the column being calculated, and for adding the requisite value of ONE to each of the complemented pixel values. The output of the last adder element 812 is coupled to a parallel driver 814, preferably eight bits wide, for driving the column output line 512.

A correction factor adjusting system comprises an XOR element 816 coupled to the controller 622 by the control bus 624 for receiving the correction factor for the column, as stored previously by the controller 622, and for receiving over the virtual value line 636 the virtual row value of the Walsh function for the virtual row element corresponding to the column being calculated. The output of the XOR element 816 is coupled to an input of an adder element 818. The other input of the adder element 818 is coupled to the virtual value line 636. The function of the XOR element 816 and the adder element 818 so coupled is to cause the sign of the correction factor value to be negative whenever the virtual row value is a logic ONE, and positive whenever the virtual row value is a logic ZERO. The output of the adder 818 is coupled to an input of an adder 820. The other input of the adder 820 is preprogrammed for a constant value of one-hundred-twenty for all time slots except the first, for which the adder 820 is preprogrammed for a value of two-hundred-forty. This is accomplished by shifting the preprogrammed value of one-hundred-twenty by one bit to the left whenever the x2 element 824 is enabled by the first time slot line 637 from the controller 622.

The reason for adding the constant values is to accomplish the requisite addition of ONE to each complemented pixel value. The predetermined Walsh factors for the two-hundred-forty real rows have exactly one- hundred-twenty logic ONEs in every time slot except the first time slot, which has two-hundred-forty logic ONEs. This means that for every time slot except the first there will be one-hundred-twenty pixel values complemented by the XOR elements 802, 804, 806 of the calculation engine 610,

612. For the first time slot , all two-hundred-forty pixel values will be complemented. As indicated herein above, a value of ONE must be added to each of the complemented pixel values in order to correctly subtract the pixel values from the sum. The adder 820 and the x2 element 824 accomplish this.

Referring to FIG. 9, an electrical block diagram of the controller 622 of the processing system 510 in accordance with the preferred embodiment of the present invention comprises a microprocessor 901 coupled to a read-only memory (ROM) 902 containing operating system software. The ROM 902 further contains predetermined Walsh function values 904, e.g., two-hundred-fifty-six time slot values for each of the two-hundred-forty real row electrodes 106, plus one virtual row. The ROM 902 also has been pre¬ programmed with an assigned frame portion value 912 indicating the portion of the frame of data, i.e., the portion of the display, that the processing system 510 comprising the controller 622 is assigned to process. The microprocessor 901 is also coupled to a random access memory (RAM) 906, comprising a location for storing a function alternator 908 for alternating the functions of elements of the processing system 510, as described herein above. The RAM 906 further comprises a location for storing one-hundred-sixty column correction factors 910 received from the rms correction factor calculator 632 over the control bus 624. The microprocessor 901 is further coupled to the frame sync line 638 and to the clock line 642 for receiving frame sync and clock signals, respectively, from a source of the frames of data, e.g., a processor of a personal computer. The microprocessor 901 is coupled to the processing system 510 by the control bus 624, the virtual value line 636, and the first time slot line 637 for controlling the processing system 510.

Referring to FIG. 10, an electrical block diagram of a personal computer 1000 in accordance with the preferred embodiment of the present invention comprises the display system 500 coupled to a microcomputer 1002 by the data input line 508 for receiving frames of data from the microcomputer 1002. The display system 500 is further coupled to the microcomputer 1002 by the frame sync line 638 and the clock line 642 for receiving frame sync and clock, from the microcomputer 1002. The microcomputer 1002 is coupled to a keyboard 1004 for receiving input from a user.

Referring to FIG. 11, a front orthographic view of the personal computer 1000 in accordance with the preferred embodiment of the present invention depicts the display system 500 supported and protected by a housing 1102. The keyboard 1004 is also depicted. Personal computers, such as the personal computer 1000, often are constructed as portable, battery-powered units. The display system 500 is particularly advantageous in such battery-powered units, because the reduced calculation rate of the processing system 510 of the display system 500 compared to conventional processing systems for actively addressed displays greatly reduces the power consumption, thus extending the battery life.

For the purpose of discussing the operation of the display system 500, it is necessary to define some terms. The term "first processor" as used herein below refers to a first portion of the plurality of processing systems 510. The first portion collectively comprises the first write control logic elements 602, the first buffer RAMs 606, the first calculation engines 610, and the first row drive shift registers 614, of the plurality of processing systems 510. The term "second processor" as used herein below refers to a second portion of the plurality of processing systems 510. The second portion collectively comprises the second write control logic elements 604, the second buffer RAMs 608, the second calculation engines 612, and the second row drive shift registers 616, of the plurality of processing systems 510. The rms correction factor calculators 632 and the controllers 622 collectively are common to both the first and second processors.

System operation is such that when frame sync is received, each controller 622 of the plurality of processing systems 510 determines from the assigned frame portion value 912 which portion of the frame of data the processing system 510 that comprises the controller 622 is assigned to process. The controller 622 then delays the start of processing by the corresponding processing system 510 until the frame of data reaches the assigned portion. The controller 622 also accesses the function alternator 908 to control the alternation of processing functions between the first and second processor.

Referring to FIG. 12, a flow chart depicting the operation of the display system 500 in accordance with the preferred embodiment of the present invention begins with the controllers 622 of the first and second processors waiting 1202 for frame sync. When frame sync arrives, the first processor loads 1204 the current frame of data while the rms correction factor calculators 632 calculate the. column correction factors for the portion of the frame of data assigned to the respective processing systems 510 corresponding to each of the rms correction factor calculators 632. This is followed by the storing of the calculated column correction factors by the controllers 622 in the RAM 906 at the location for storing column correction factors 910.

Meanwhile, the second processor concurrently calculates 1206 in the second calculation engines 612 the column signals from a frame of data stored previously in the second buffer RAMs 608, using Walsh function values supplied to the second row drive shift registers 616 by the controllers 622. The second processor then drives the column output line 512 and the row output line 514 with the calculated column signals and the Walsh function values, respectively. The controllers 622 coordinate the processing systems 510 to calculate and drive the column and row output lines 512, 514 at the correct times corresponding to their respective portions of the frames of data.

Next, the first and second processors again wait 1208 for frame sync. When frame sync arrives, the first processor calculates 1210 in the first calculation engines 610 the column signals from the frame of data stored previously in the first buffer RAMs 606, using Walsh function values supplied to the first row drive shift registers 614 by the controllers 622. The first processor then drives the column output line 512 and the row output line 514 with the calculated column signals and the Walsh function values, respectively. The controllers 622 coordinate the processing systems 510 to calculate and drive the column and row output lines 512, 514 at the correct times corresponding to their respective portions of the frames of data.

Meanwhile, the second processor concurrently loads 1212 the current frame of data while the rms correction factor calculators 632 calculate the column correction factors for the portion of the frame of data assigned to the respective processing systems 510 corresponding to each of the rms correction factor calculators 632. This is followed by the storing of the calculated column correction factors by the controllers 622 in the RAM 906 at the location for storing column correction factors 910. The flow then returns to step 1202, and the process repeats.

By alternately loading the first and second buffer RAMs 606, 608 with a full frame of data before processing the frame of data in the processing systems 510, the display system 500 advantageously allows the data to be processed in parallel, thereby significantly reducing the calculation rate, e.g., by a factor of two-hundred-forty, compared to conventional actively addressed display systems. By further dividing the LCD 100 into the eight areas 511 for processing as described herein above, the processing load is reduced by an additional factor of eight. Thus, the processing systems 510 are able to operate at a clock rate of approximately two and one-half MHz. The reduction in the calculation rate significantly reduces the power consumption of the display system 500, thus enabling substantially improved battery life in a portable electronic device that includes the display system 500. Referring to FIG. 13, a flow chart depicting the operation of the rms correction factor calculator 632 in accordance with the preferred embodiment of the present invention begins with the controller 622 waiting 1302 for its assigned time after frame sync for its assigned start- processing time corresponding to the area 511 of the LCD 100 assigned to the controller 622. When the start- processing time arrives, the first and second accumulator elements 710, 706 are initialized 1304 to zero by the controller 622. Next, the first look-up table element 704 squares 1310 the pixel value, and the squared pixel value is then added 1314 to the second accumulator element 706 to derive ∑I . Concurrently, the pixel value is added 1312 to the first accumulator element 710 to derive ∑ I . If in step 1316 the pixel values for all real rows of the column being calculated have not been received, the flow returns to step 1306 to receive a next pixel value.

If, on the other hand, in step 1316 the pixel values for all real rows of the column being calculated have been received, then ∑ I is multiplied 1318 by two-hundred- fifty-five, as described herein above in the discussion of FIG. 7. Next, ∑ I² is subtracted 1320 from the value obtained in step 1318, the subtraction being done by the second subtracter element 708. Then the square root of the value obtained in step 1320 is determined 1322 by the second look-up table element. The value determined in step 1322 is then multiplied 1323 by the constant K in the multiplier element 716. Next, the column correction factor value for the column I

j is transmitted from the rms correction factor calculator 632 to the controller 622 over the control bus 624, after which the controller 622 stores 1324 the value in the RAM 906 at the location for storing column correction factors 910 corresponding to the calculated column. If, in step 1326, the controller 622 determines that the calculated column is not the last column assigned to the processing system 510, then the controller 622 returns the rms correction factor calculator 632 to step 1304 to begin processing the next column of data. If, on the other hand, the controller 622 determines that the calculated column is the last column assigned to the processing system 510, then the controller 622 returns the rms correction factor calculator 632 to step 1302 to wait for the next start-processing time to arrive.

Referring to FIG. 14, a flow chart depicting the operation of the calculation engine 610, 612 in accordance with the preferred embodiment of the present invention begins with the controller 622 waiting 1402 after frame sync for its assigned start-processing time corresponding to the area 511 of the LCD 100 assigned to the controller 622. When the start-processing time arrives, the controller 622 selects 1404 a next time slot for processing and initializes the row drive shift register 614, 616 with Walsh function values for the time slot for each of the rows assigned to the controller 622, plus the virtual row, e.g., two-hundred-forty-one Walsh function values for the time slot.

The controller 622 then selects 1406 a next column and retrieves from the RAM 906 and then transmits to the calculation engine 610, 612 the correction factor value calculated earlier for the selected column. Next, the controller 622 controls the buffer RAM 606, 608 to transfer 1408 in parallel to the calculation engine 610, 612 the pixel values corresponding to the rows of the selected column. Concurrently, the calculation engine 610, 612 receives 1410 from the row drive shift register 614, 616 the Walsh function values for the time slot for each of the rows assigned to the controller 622. The calculation engine 610, 612 adjusts 1412 the correction factor value in accordance with the virtual row drive signal for the selected column and the selected time slot, the adjustment made as described herein above in reference to FIG. 8.

Next, the calculation engine 610, 612 derives a column drive signal by adding 1414 together the adjusted correction factor value and the pixel values of the selected column corresponding to real rows having a row drive signal of ONE, and subtracting from that sum the pixel values of the column corresponding to real rows having a row drive signal of ZERO. Then the calculation engine 610, 612 and row drive shift register 614, 616 drive 1416 the column and row output lines 512, 514 during the time slot with the (calculated) column and (predetermined) row drive signals, respectively.

It is important to note that the steps 1406, 1408, 1410, 1412, and 1414 are preferably performed substantially simultaneously and in parallel to achieve optimum calculation speed. Also, as was discussed herein above in reference to FIG. 5, in the preferred embodiment of the present invention only two of the processing systems 510 are used to drive the row drive elements 506. It will be appreciated that even a single processing system 510 is sufficient to drive the row drive elements 506, because the row drive signals for corresponding rows in each of the group of two-hundred-forty rows in the top and bottom halves of the LCD 100 are predetermined and identical to one another.

In step 1418 the controller 622 checks whether the last column has been processed for the selected time slot. If not, the flow returns to step 1406 to select and process a next column. If, on the other hand, at step 1418 the last column has been processed for the selected time slot, then the controller 622 checks 1422 whether the last time slot for the frame of data has been processed. If not, the flow returns to step 1404, where the controller 622 selects a next time slot for processing. If, on the other hand, in step 1422 the last time slot for the frame of data has been processed, then flow returns to step 1402, where the controller 622 will wait to process a next frame of data. The preceding discussion and analysis of the preferred embodiment of the present invention applies to pixel values represented by eight-bit data. It will be appreciated that the present invention can be adjusted to accommodate pixel values represented by both larger and smaller numbers of bits, e.g., sixteen-bit pixels or four-bit pixels.

Thus, the preferred embodiment of the present invention provides a method and apparatus for driving an actively addressed display in a manner that advantageously minimizes the power consumption of the required calculation engine. By performing calculations in parallel for all the pixel values of a column at once instead of doing the calculations one pixel at a time, the preferred embodiment of the present invention substantially reduces the required calculation speed and thus substantially reduces the power required to perform the calculations. The reduced power compared to conventional drivers for actively addressed displays is a particularly important advantage in portable, battery-powered applications, such as laptop computers, in which long battery life is a highly desirable feature.

Claims

1. A method in a processing system for processing successively transmitted frames of data representing pixel values for driving an actively addressed display comprising pixels controlled by a plurality of first and second electrodes, the processing system comprising a first processor and a second processor, the first and second processors comprising a digital buffer memory and a drive signal generator, the method comprising the steps of:

(a) loading into the digital buffer memory by the first processor the pixel values from a frame of data of the successively transmitted frames of data;

(b) loading into the digital buffer memory by the second processor the pixel values from the next frame of data of the successively transmitted frames of data; and

(c) calculating by the first processor concurrently with step (b) a drive signal for application to one of the plurality of first electrodes during a time slot of a predetermined number of time slots, wherein the predetermined number is related to the number of electrodes in the plurality of second electrodes, and wherein the drive signal is calculated as a function of a plurality of predetermined drive signals for application to the plurality of second electrodes during the time slot in combination with selected pixel values from the frame of data transmitted and loaded immediately before said next frame, the selected pixel values corresponding to pixels collectively controlled by the one of the plurality of first electrodes.

2. The method of claim 1, wherein step (c) comprises the step of: (d) driving from the drive signal generator during the time slot the one of the plurality of first electrodes with the calculated drive signal, while concurrently driving the plurality of second electrodes with the plurality of predetermined drive signals.

3. The method of claim 2, further comprising the step of:

(e) repeating step (c) to calculate additional drive signals for application to additional ones of the plurality of first electrodes during the time slot, until drive signals applicable to substantially all of the plurality of first electrodes during the time slot have been calculated and driven.

4. The method of claim 3, further comprising the step of:

(f) repeating steps (c) and (e) for additional ones of the predetermined number of time slots until drive signals applicable to substantially all of the plurality of first electrodes during substantially all of the predetermined number of time slots have been calculated and used to drive corresponding ones of the plurality of first electrodes.

5. The method of claim 4, further comprising the steps of:

(g) performing, by the first processor after completing step (f) , during the next subsequent frame of data of the successively transmitted frames of data, the step (b) previously performed by the second processor; and (h) performing concurrently with step (g), by the second processor during said next subsequent frame of data, the steps (c) (e), and (f) performed previously by the first processor.

6. The method of claim 5, further comprising the step of:

(i) repeating steps (b), (c), and (e) through (h) to process additional subsequent ones of the successively transmitted frames of data.

7. The method of claim 1, wherein step (c) comprises the steps of:

(d) transferring the selected pixel values from the digital buffer memory to the drive signal generator substantially simultaneously and in parallel; and

(e) processing in parallel by the drive signal generator the selected pixel values transferred in step (d) to calculate the drive signal.

8. The method of claim 7, wherein signal values for the plurality of predetermined drive signals for the time slot consist of logic ONES and ZEROES, and wherein an additional one of the plurality of predetermined drive signals corresponds to a plurality of virtual pixels, and wherein the method further comprises the step of: (f) calculating an rms correction factor as a function of the selected pixel values, wherein the rms correction factor is calculated as

in which P is the number of bits used to represent each of the pixel values, N is the number of electrodes in the plurality of second electrodes, I_t is one of the selected pixel values controlled by an ith one of the plurality of second electrodes, and sign of the rms correction factor is determined from the additional one of the plurality of predetermined drive signals, the sign being positive when the additional one is ONE and negative when the additional one is ZERO, and wherein step (e) comprises the steps of:

(g) adding together ones of the selected pixel values for pixels collectively controlled by the one of the plurality of first electrodes in response to corresponding pixel-controlling ones of the plurality of predetermined drive signals having a signal value of ONE assigned for the time slot, to derive a first subtotal; (h) subtracting from the first subtotal derived in step (g) ones of the selected pixel values for pixels collectively controlled by the one of the plurality of first electrodes in response to corresponding pixel- controlling ones of the plurality of predetermined drive signals having a signal value of ZERO assigned for the time slot, to derive a second subtotal; and (i) adding the rms correction factor calculated in step (f) to the second subtotal calculated in step (h) to derive a value for the drive signal.

9. A processing system for processing successively transmitted frames of data representing pixel values for driving an actively addressed display comprising pixels controlled by a plurality of first and second electrodes, the processing system comprising: a first processor comprising a first digital buffer memory for loading and storing the pixel values from a frame of data of the successively transmitted frames of data; and a second processor coupled to the first processor for coordination therewith, the second processor comprising a second digital buffer memory for loading and storing the pixel values from the next frame of data of the successively transmitted frames of data, wherein the first and second processors further comprise a drive signal generator including a calculation engine for coupling to the first and second digital buffer memories for calculating from the pixel values contained therein a drive signal for application to one of the plurality of first electrodes during a time slot of a predetermined number of time slots, wherein the predetermined number is related to the number of electrodes in the plurality of second electrodes, and wherein the drive signal is calculated as a function of a plurality of predetermined drive signals for application to the plurality of second electrodes during the time slot in combination with selected pixel values, the selected pixel values corresponding to pixels collectively controlled by the one of the plurality of first electrodes.

10. The processing system of claim 9, further comprising a controller coupled to the first and second processors for controlling and coordinating the operation thereof.

11. The processing system of claim 9, further comprising a driver element for driving during the time slot the one of the plurality of first electrodes with the calculated drive signal, and for concurrently driving the plurality of second electrodes with the plurality of predetermined drive signals.

12. The processing system of claim 11, wherein the first and second processors further comprise an electrode selector element coupled to the calculation engine for calculating additional drive signals for application to additional ones of the plurality of first electrodes during the time slot, until drive signals applicable to substantially all of the plurality of first electrodes during the time slot have been calculated and driven.

13. The processing system of claim 12, wherein the first and second processors further comprise a time-slot repeater element coupled to the electrode selector element for calculating additional drive signals for additional ones of the predetermined number of time slots until drive signals applicable to substantially all of the plurality of first electrodes during substantially all of the predetermined number of time slots have been calculated and used to drive the corresponding ones of the plurality of first electrodes.

14. The processing system of claim 13, further comprising a processor alternator element for controlling the first and second processors to perform alternate operations for every successive frame of data, the first processor loading and storing a frame of data while the second processor transfers and processes a previously stored frame of data in the drive signal generator to calculate a corresponding plurality of drive signals, and thereafter the second processor loading and storing the next frame of data while the first processor transfers and processes the previously stored frame of data in the drive signal generator to calculate a next corresponding plurality of drive signals.

15. The processing system of claim 9, wherein the first and second processors further comprise: a parallel transfer element coupled to the calculation engine and coupled to the first and second digital buffer memories for transferring substantially simultaneously and in parallel the selected pixel values from the first and second digital buffer memories to the calculation engine; and a parallel processing element coupled to the calculation engine for processing in parallel the selected pixel values to calculate the drive signal.

16. The processing system of claim 15, further comprising an rms correction factor calculator for calculating an rms correction factor as a function of the selected plurality of pixel values, wherein the rms correction factor is calculated as

(2^P - l)VN

in which P is the number of bits used to represent each of the pixel values, N is the number of electrodes in the plurality of second electrodes, I_x is one of the selected pixel values controlled by an ith one of the plurality of second electrodes, and sign of the rms correction factor is determined from an additional one of the plurality of predetermined drive signals, the sign being positive when the additional one is ONE and negative when the additional one is ZERO, and wherein signal values for the plurality of predetermined drive signals for the time slot consist of logic ONES and ZEROES, and wherein the additional one of the plurality of predetermined drive signals corresponds to a plurality of virtual pixels, and wherein the parallel processing element comprises an adder/subtracter element coupled to the rms correction factor calculator for adding together ones of the selected pixel values for pixels collectively controlled by the one of the plurality of first electrodes in response to corresponding pixel-controlling ones of the plurality of predetermined drive signals having a signal value of ONE assigned for the time slot to derive a first subtotal, and further for subtracting from the first subtotal ones of the selected pixel values for pixels collectively controlled by the one of the plurality of first electrodes in response to corresponding pixel-controlling ones of the plurality of predetermined drive signals having a signal value of ZERO assigned for the time slot to derive a second subtotal, and further for adding the rms correction factor to the second subtotal to derive a value for the drive signal.

17. An electronic device, comprising: electronic circuitry for generating information comprising successively transmitted frames of data representing pixel values; an enclosure coupled to the electronic circuitry for supporting and protecting the electronic circuitry; an actively addressed display coupled to the electronic circuitry for displaying the information therefrom, wherein the actively addressed display comprises pixels controlled by a plurality of first and second electrodes; and a processing system coupled to the electronic circuitry for processing the information for driving the actively addressed display, wherein the processing system comprises: a first processor comprising a first digital buffer memory for loading and storing the pixel values from a frame of data of the successively transmitted frames of data; and a second processor coupled to the first processor for coordination therewith, the second processor comprising a second digital buffer memory for loading and storing the pixel values from the next frame of data of the successively transmitted frames of data, wherein the first and second processors further comprise a drive signal generator including a calculation engine for coupling to the first and second digital buffer memories for calculating from the pixel values contained therein a drive signal for application to one of the plurality of first electrodes during a time slot of a predetermined number of time slots, wherein the predetermined number is related to the number of electrodes in the plurality of second electrodes, and wherein the drive signal is calculated as a function of a plurality of predetermined drive signals for application to the plurality of second electrodes during the time slot in combination with selected pixel values, the selected pixel values corresponding to pixels collectively controlled by the one of the plurality of first electrodes.

18. The electronic device of claim 17, further comprising a controller coupled to the first and second processors for controlling and coordinating the operation thereof.

19. The electronic device of claim 17, further comprising a driver element for driving during the time slot the one of the plurality of first electrodes with the calculated drive signal, and for concurrently driving the plurality of second electrodes with the plurality of predetermined drive signals.

20. The electronic device of claim 19, wherein the first and second processors further comprise an electrode selector element coupled to the calculation engine for calculating additional drive signals for application to additional ones of the plurality of first electrodes during the time slot, until drive signals applicable to substantially all of the plurality of first electrodes during the time slot have been calculated and driven.

21. The electronic device of claim 20, wherein the first and second processors further comprise a time-slot repeater element coupled to the electrode selector element for calculating additional drive signals for additional ones of the predetermined number of time slots until drive signals applicable to substantially all of the plurality of first electrodes during substantially all of the predetermined number of time slots have been calculated and used to drive the corresponding ones of the plurality of first electrodes.

22. The electronic device of claim 21, further comprising a processor alternator element for controlling the first and second processors to perform alternate operations for every successive frame of data, the first processor loading and storing a frame of data while the second processor transfers and processes a previously stored frame of data in the drive signal generator to calculate a corresponding plurality of drive signals, and thereafter the second processor loading and storing the next frame of data while the first processor transfers and processes the previously stored frame of data in the drive signal generator to calculate a next corresponding plurality of drive signals.

23. The electronic device of claim 17, wherein the first and second processors further comprise: a parallel transfer element coupled to the calculation engine and coupled to the first and second digital buffer memories for transferring substantially simultaneously and in parallel the selected pixel values from the first and second digital buffer memories to the calculation engine; and a parallel processing element coupled to the calculation engine for processing in parallel the selected pixel values to calculate the drive signal.

24. The electronic device of claim 23, further comprising an rms correction factor calculator for calculating an rms correction factor as a function of the selected plurality of pixel values, wherein the rms correction factor is calculated as

Vr ps *^* -*& - in which P is the number of bits used to represent each of the pixel values, N is the number of electrodes in the plurality of second electrodes, I_χ is one of the selected pixel values controlled by an ith one of the plurality of second electrodes, and sign of the rms correction factor is determined from an additional one of the plurality of predetermined drive signals, the sign being positive when the additional one is ONE and negative when the additional one is ZERO, and wherein signal values for the plurality of predetermined drive signals for the time slot consist of logic ONES and ZEROES, and wherein the additional one of the plurality of predetermined drive signals corresponds to a plurality of virtual pixels, and wherein the parallel processing element comprises an adder/subtracter element coupled to the rms correction factor calculator for adding together ones of the selected pixel values for pixels collectively controlled by the one of the plurality of first electrodes in response to corresponding pixel-controlling ones of the plurality of predetermined drive signals having a signal value of ONE assigned for the time slot to derive a first subtotal, and further for subtracting from the first subtotal ones of the selected pixel values for pixels collectively controlled by the one of the plurality of first electrodes in response to corresponding pixel-controlling ones of the plurality of predetermined drive signals having a signal value of ZERO assigned for the time slot to derive a second subtotal, and further for adding the rms correction factor to the second subtotal to derive a value for the drive signal.