WO1994019743A1

WO1994019743A1 - Intermediate processor disposed between a host processor channel and a storage director with error management

Info

Publication number: WO1994019743A1
Application number: PCT/US1994/001447
Authority: WO
Inventors: James R. Bergsten; Shih-Tsung Hwang; David J. King
Original assignee: Andor Systems, Inc.
Priority date: 1993-02-17
Filing date: 1994-02-09
Publication date: 1994-09-01

Abstract

An intermediate processor (22) includes a main processor coupled to a plurality of front end circuits, and each front end circuit is coupled to a plurality of control unit interface circuits. Each control unit interface circuit is coupled to host computers (21, 22, 23) through channels (24-29). Any control unit interface circuit may communicate with any front end circuit. The main processor is also coupled to a plurality of mass storage devices (64, 66, 68) through a plurality of channel of back end circuits. Tracks of data from the mass storage devices are stored in a main storage memory located in the main processor. A unique buffer circuit allows data to be communicated between the main processor and the circuits coupled to it immediately without requiring the circuits to operate at the main processor clocking rate. Each front end circuit includes a nonvolatile storage memory for storing change data sufficinet to update the mass storage devices in the event of a power or hardware failure.

Description

intermediate processor disposed between a host processor channel and a storage director with error management

BACKGROUND OF THE INVENTION

This invention relates to computing systems and, more particularly, to processors which manage data flow between one or more mass storage devices and one or more host computers.

Fig. 1 is a block diagram of a known computing system 4. Computing system 4 includes a host processor 5 having I/O channels 6 and 7. Channels 6 and 7 are coupled to storage directors 8 and 9, respectively, through respective buses 10 and 11. Storage directors 8 and 9 are coupled to corresponding mass storage devices 12 and 13 through respective buses 14 and 15. Each storage director 8, 9 is dedicated to its associated channel and mass storage device for communicating data from the mass storage device to host computer 5. Because of such hardware dedication, host computer data destined for a particular mass storage device cannot be transferred to that mass storage device if its associated channel is busy, even if the other channel is idle. The same is true for the communication of data from the mass storage device to the host computer. Additionally, if more mass storage is desired, then additional channels and storage directors must be added to accommodate them. For applications which use many mass storage devices, the amount of hardware needed to service all the mass storage devices becomes excessive.

SUMMARY OF THE INVENTION

The present invention is directed to a computing system having an intermediate processor disposed between one or more host computers and one or more mass storage . devices to eliminate the dedicated hardware required in conventional computing systems. The intermediate processor allows any host computer to communicate with any mass storage device through any host computer channel.

In one embodiment of the present invention, the intermediate processor includes a main processor coupled to a plurality of front end circuits, and each front end circuit is coupled to a plurality of control unit interface circuits. Each control unit interface circuit is coupled to a host computer channel. Any control unit interface circuit may communicate with any front end circuit. The main processor is also coupled to a plurality of mass storage devices through a plurality of channel or back end circuits. Tracks of data from the mass storage devices are stored in a main storage memory located in the main processor. A unique buffer circuit allows data to be communicated between the main processor and the circuits coupled to it immediately without requiring the circuits to operate at the main processor clocking rate.

When a host computer needs data from one of the mass storage devices, it makes a request through a selected one of its channels. The control unit interface circuit coupled to the selected channel may obtain the requested data by communicating with any one of the front end circuits which, in turn, obtains the requested data from the main storage memory in the main processor. If the front end circuit cannot obtain the requested data immediately, it disconnects from the control unit interface circuit while the main processor retrieves a track containing the requested data from the appropriate mass storage device. Once the requested data becomes available, the front end circuit reconnects with any available control unit interface circuit coupled to the requesting host computer. Each front end circuit includes a nonvolatile storage memory for storing change data sufficient to update the mass storage devices in the event of a power or hardware failure. When such a failure occurs, the data stored in either the main storage memory in the main processor or the data stored in the nonvolatile memories in the plurality of front end circuits are used to update the mass storage devices in chronological order. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. l is a block diagram of a known data processing system; Fig. 2 is a block diagram of a particular embodiment of a data processing system according to the present invention;

Fig. 3 is a block diagram of a particular embodiment of the intermediate processor shown in Fig. 2; Fig. 4 is a block diagram of particular embodiment of a control unit interface shown in Fig. 3;

Fig. 5 is a block diagram of a particular embodiment of a front end circuit shown in Fig. 3;

Fig. 6 is a block diagram of a particular embodiment of a channel circuit shown in Fig. 3;

Fig. 7 is a diagram of a particular embodiment of an M-bus shown in Fig. 3;

Figs. 8A-8O are timing diagrams showing various methods of operation of the M-bus shown in Fig. 10; Fig. 9 is a diagram of a particular embodiment of a path identification table according to the present invention;

Fig. 10 is a diagram showing a particular embodiment of a channel interface bus shown in Fig. 3;

Fig. 11 is a are block diagram of a particular embodiment of a portion of the input/output buffer and control circuits shown in Figs. 5-6;

Figs. 12A-B show a particular embodiment of the console bus shown in Figs. 3; and

Fig. 13 is a flow chart showing a particular method according to the present invention for data recovery in the event of a power failure in the apparatus shown in Fig. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OVERVIEW Fig. 2 is a block diagram of a particular embodiment of a data processing system 20 according to the present invention. Data processing system 20 includes host computers 21, 22 and 23. Host computers 21-23 may comprise, e.g., any IBM System/370, System/390, ES/3090, ES/9000 (or compatible) computer that uses OEMI I/O channels. A host computer may be a physical processor or a processor logical partition. Each host computer includes two channels. For example, host computer 21 includes host channels 24 and 25; host computer 22 includes host computer channels 26 and 27; and host computer 23 includes host channels 28 and 29. Each channel is coupled to an intermediate processor 22 through host channel buses 30- 35, respectively.

Intermediate processor 22 is coupled to a console 36 through a console bus 40 and to a remote storage unit 44 through a communication link 48 which may be a Tl or T3 communication link. Remote storage 44 may be another data processing system such as data processing system 20 now being described. Console 36 is coupled to a disk drive 50 through a bus 51.

Intermediate processor 22 is also coupled to storage directors 58, 60 and 62 through processor-director buses 52, 54 and 56, respectively. Storage directors 58-62 may comprise, e.g., an IBM series 3880, 3990-1-2-3 or series 6100 storage director, a Hitachi 7980-3 storage director, or a disk drive interface such as the disk drive interface shown in Figs. 4 and 9 and described below. Each storage director is coupled to a mass storage device 64, 66 or 68 through respective director-storage buses 71, 72 and 73. Mass storage devices 64-68 may comprise-, e.g., an IBM 3380 (D/E, J/K) or 3390 storage device, an Amdahl 6380 (D/E, J/K) storage device, or a Hitachi 7380 D/E, J/KX, K or 7390 (1/2/F) storage device.

Unlike data processing system 10 shown in Fig. 1, each host computer channel need not have a dedicated storage director. By adding intermediate processor 22, any host computer channel may communicate with any storage director. INTERMEDIATE PROCESSOR

Fig. 3 is a block diagram of a particular embodiment of intermediate processor 22. Intermediate processor 22 includes a main processor 74 which controls a plurality of interface circuits that are coupled to the external data processing elements. In this embodiment, main processor 74 is an IBM 370-XA compatible processor, and it uses IBM 370-XAO features to perform I/O operations. Main processor 74 includes a main storage memory 75, a portion of which comprises a track buffer 77 for storing tracks of data from the mass storage devices. The organization and operation of track buffer 77 is disclosed in copending U.S. patent application Serial No.

entitled Track Buffer With Embedded Sense Data, incorporated herein by reference. In this embodiment, full tracks of data are read and stored in track buffer 77 regardless of the number of records requested by host computers 21-23.

The interface circuits include, e.g., sixteen control unit interface (CUI) circuits 78A-P, each of which may be coupled to a host computer channel through a host channel bus. For example, CUI circuits 78A and 78B are coupled to host channels 24 and 25 through host channel buses 30 and 31, respectively. Each CUI circuit 78A-P employs the IBM OEMI channel protocol and appears to its corresponding host channel as one or more storage directors.

Each CUI circuit is coupled to a plurality, e.g., eight front end (FE) circuits 82A-H through a corresponding number of M-buses 84A-H. That is, CUI circuit 78A is coupled to FE circuits 82A-H through M-buses 84A-H (where FE circuit 82A is coupled to M-bus 84A, FE circuit 82B is coupled to M- bus 84B, etc.) , CUI circuit 78B is coupled to FE circuits 82A- H through M-buses 84A-H, and so on. Each FE circuit 82A-H is coupled to main processor 4 through a corresponding channel interface bus (CIB) 86A-H. Each FE circuit operates so that, to a CUI circuit, the FE circuit appears to be a control processor. To main processor 74, the FE circuit appears to be a non-standard IBM OEMI channel. Each FE circuit is constructed on a single board together with a channel (CH) circuit such as one of channel circuits 90A-H. Channel circuits 90A-H also communicate with main processor 74 by sharing CIB's 86A-H with FE circuits 82A- H and function as a standard IBM 370-XA or IBM 3090 mainframe channel using the IBM OEMI channel protocol. Each CH circuit 90A-H further communicates with an associated storage director through OEMI channel buses 91A-H.

Finally, a plurality of channel circuits 90I-Y (two per physical board) may be coupled to main processor 74 through respective channel interface buses 86I-P for communication of data to remote storage 44 over T3 communication link 48. Of course, channel circuits 90A-H may be used for communication of data to remote storage 44, and channel circuits 90I-Y may be used as additional paths to the local storage directors.

Each FE-CH circuit pair communicates with console 36 through interface-console buses 94A-H which form a part of console bus 40. Channel circuits 90I-Y also preferably communicate with console 36 through interface-console buses (not shown) . Main processor 74 communicates with console 36 over a processor-console bus 98 which forms another part of console bus 40.

CONTROL UNIT INTERFACE CIRCUIT

Fig. 4 is a block diagram showing the structure of CUI. circuits- 78A and 78B. In this> embodiment, two CUI circuits are constructed together on the same physical board and share the same M-bus connections. The other boards containing the other pairs of CUI circuits are constructed the same. Assume, as before, that CUI circuit 78A is coupled to host channel 24 through host channel bus 30, and that CUI circuit 78B is coupled to host channel 25 through host channel bus 31. Since host channels 24 and 25 operate according to IBM 370 OEMI protocol, each host channel bus 30, 31 typically comprises two separate cables (labelled OEMI busl30A-B and OEMI tag 105A-B in Fig. 4). OEMI bus cablesl03A-B each comprise an 8-bit data input bus with parity bit that communicates data from the associated CUI circuit to the host channel and an 8-bit output bus with parity bit that communicates data from the channel to the associated CUI circuit. OEMI tag cables 105A-B each provide the control signals needed for the sequences of selection, streaming data transfers, interlock of data transfers, status presentation and error recovery. A complete description of the OEMI structures and protocol may be found in the IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturer's Information manual, incorporated herein by reference, so further details shall be omitted.

CUI circuit 78A includes an error detection code generator/checker 104A coupled to OEMI bus cable 103A and OEMI tag cable 105A, an OEMI channel control sequencer 108A coupled to error detection code generator/checker 104A through buses

109A and 113A, and an M-bus controller 116A coupled to OEMI channel control sequencer 108A through buses 118A. M-bus controller 116A is coupled to an M-bus arbitration logic circuit 120 through a bus 119A. A control register file 125A is coupled to M-bus arbitration logic circuit 120 through a bus 126A for storing operating parameters. Similarly, CUI circuit 78B includes an error detection code generator/checker

104B coupled to OEMI bus cable 103B and to OEMI tag cable 105B, an OEMI channel control sequencer 108B coupled to error detection code generator/checker 104B through buses 109B and

113B, and an M-bus controller 116 coupled to OEMI channel control sequencer 108B through a bus 118B. M-bus controller

116B is coupled to M-bus arbitration logic circuit 120 through a bus 119B, and a control register file 125B is coupled to M- bus arbitration logic circuit 120 through a bus 126B.

M-bus arbitration logic circuit 120 determines which CUI circuit 78A or 78B can use a particular M-bus at any particular time. M-bus arbitration logic circuit 120 also permits both CUI circuits 78A and 78B to be active simultaneously over different M-buses. M-bus arbitration logic circuit 120 is coupled to a storage control array logic circuit 121 through a line 122. Storage control array logic circuit 121 is, in turn, coupled to a storage control array (SCA) 123 through a line 124. All global information that can be shared by the FE circuits is saved in SCA 120. SCA 120 preferably comprises a 64 kilobyte RAM that can be accessed by any one of the M-buses 84A-H. M-bus arbitration logic circuit 120 multiplexes communications between M-buses 84A-H, host channel buses 30, 31 and SCA 123. In this embodiment, simultaneous access to SCA 120 is not permitted. Storage control array logic 124 allows data to be written into SCA 120 from any one of the M-bus ports even when both CUI circuits 78A and 78B are busy.

FRONT END CIRCUIT Fig. 5 is a block diagram of FE circuit 82A. FE circuits 82B-H are constructed the same way. FE circuit 82A includes a bit-slice microprocessor 142 for controlling communication between a CUI circuit and main processor 74, a work-area random access memory 146 coupled to processor 190 through a bus 148, a data transfer routing logic circuit 134 coupled to processor 142 through a bus 150 for controlling data transfers between processor 142 and M-bus 84A, an M-bus control sequencer circuit 130 coupled to data transfer routing logic circuit 134 through a bus 136 for controlling the actual transfer of data on M-bus 84A, a non-volatile storage memory 138 coupled to processor 142 through a bus 139 and to data transfer routing logic circuit 134 through a bus 140 for- storing error recovery data, a console interface control sequencer circuit 160 coupled to processor 142 through a bus 164 for controlling information transfer over console interface bus 94A, an input/output buffer and control circuit 168 coupled to processor 142 through a bus 170 for buffering the data transferred between processor 142 and CIB 86A, and a channel interface control sequencer circuit 178 coupled to input/output buffer and control circuit 168 through a bus 174 for controlling the actual data transfer on CIB 86A. FE circuits 82A-H accept caching storage director commands from host computers 21-23. Non-read/write commands are executed by the FE circuits and checked (if needed) for validity. If a command requires an operation by main processor 74, the FE circuits pass the valid parameters to main processor 74 and return status information to the requesting host computer. If a command is the first read/write command in a chain for a particular track, the FE circuit queries main processor 74 to determine whether the track already exists in track buffer 77. If so, main processor 74 returns the track's location as a list of Indirect Data Address Words (IDAW's) . Each IDAW specifies a 4 kilobyte segment of main storage 75. If the requested track is not present in track buffer 77, the FE returns retry status to the requesting host computer, and main processor 74 constructs a command chain to read the track from mass storage into track buffer 77. Once the chain has completed, main processor 74 notifies the FE circuit that the track is available and provides its location as a list of IDAW's. The FE circuit then operates on the track until the track is no longer needed or until the end of the list is reached.

CHANNEL CIRCUIT

Fig. 6 is a block diagram of CH circuit 90A. CH circuits 90B-H (and 90I-Y) are constructed the same way. Channel circuit 90A includes a bit slice microprocessor 190 for controlling communication between main processor 74 and OEMI channel bus 91A, a work-area random access memory 194 coupled to processor 190 through a bus 195, a console interface control sequencer 198 coupled to processor 190 through a bus 202 for controlling information transfer between processor 190 and console interface bus 94A, and a data transfer routing logic circuit 206 coupled to processor 190 through a bus 210 for controlling data flow among processor 190, CIB 86A and OEMI channel bus 91A as required. For transferring data between processor 190 and CIB 86A, a channel interface control sequencer 214 is coupled to data transfer 10 routing logic 206 through a bus 218, to channel interface bus 86A, and to an input/output buffer and control circuit 222 through a bus 226. Input/output buffer and control circuit 222 is coupled to processor 190 through a bus 230 and buffers 5 the data transferred between processor 190 and channel interface bus 86A. For transferring data between processor 190 and OEMI channel bus 91A, an OEMI channel control sequencer 240 is coupled to data transfer routing logic 206 through a bus 244 and to an error detection and code generator

10 circuit 248 through a bus 250. Error detection and code generator circuit 248 is coupled to OEMI channel bus 91A.

Each CH circuit 90A-H accepts CCW chains created by main processor 74 and executes them (without checking for validity or correct length) using the OEMI bus and tag

15 protocol. The CH circuits also accept status information and blocks of data from the storage directors for main processor 74. Each CH circuit can read and write directly to main storage 75.

20 STORAGE DIRECTOR

An alternative embodiment of intermediate processor 22 is shown in Fig. 4. The only difference between this processor and the one shown in Fig. 3 is the substitution of back end (BE) circuits 100A-H for channel circuits 90A-H. BE

25 circuits 100A-H are coupled to disk drive interface (DDI) circuits 99A-H through M-buses 101A-H much like FE circuits 82A H are coupled to CUI circuits 78A-P. That is, BE circuit 100A is coupled to DDI circuits 99A-H through M-bus 101A, BE circuit 100B is coupled to DDI circuits 99A-H through M-bus

30 101B, etc. DDI circuits 99A-H are described in connection with Fig. 9. Each DDI circuit 99A-H is coupled to four disk drives. For example, DDI circuit 99A is coupled to disk drives 102A-D through disk drive interface buses 103A-D. The function of a BE circuit is similar to that of a standard IBM

35 370 mainframe channel (and CH circuits 90A-Y) except it communicates with the DDI circuits through an M-bus rather than an IBM OEMI channel. This embodiment also may include CH circuits (not shown) for communication with remote storage 44 or other local storage directors, and any BE circuit may be replaced with a CH circuit. If desired, the BE circuits also may communicate with remote storage 44 or may function as alternate paths to other local storage directors.

M-BUS

Fig. 7 is a diagram of the signal lines which comprise each M-bus 84A-H. Each M-bus includes a SELECT line 300 which is used by an FE circuit to select a CUI circuit; an SRS line 304 which signals that the CUI circuit is selected and is in an idle state; a BCS line 308 which is used by the FE circuit to indicate that a command is to be passed to a CUI circuit; an ATTENTION line 312 which is used by a CUI circuit to indicate either than an error occurred during data transfer or that the CUI circuit needs to have some of its registers read due to some action by the disk drives or a host mainframe; a SYNC line 316 and an ACK line 320 that are used during data transfers to indicate that a byte of information has been sent or received; a READY line 324 that is used during a data transfer by the CUI circuit to indicate that it is active and waiting for the next byte of information; a BROADCAST line 328 that is used by an FE circuit to reconnect to a CUI circuit; a reserved line 332 that is reserved for future expansion; eight bidirectional DATA lines 334-350 and a PARITY line 354 for providing parity for DATA lines 334-350.

Figs. 8A-0 show the timing of the signals on the M- bus for various situations. In general, the control signals are used in a handshaking manner to execute commands or report status. Elements connected to the M-buses use a data streaming method to pass data at a rate of approximately 4.5 megabytes per second. Data streaming is controlled by the SYNC and ACK signals depending upon the direction of data transfer. A data transfer can be paused by inactivating the READY signal. After an operation completes, or while the M- bus is not busy, a status byte is present that indicates the state of the CUI circuits. Active high signals are shown, but any signal could be active low, if desired.

Fig. 8A shows the signals which appear on an M-bus when a CUI circuit (or multiple CUI circuits) receives a command from its associated channel or otherwise needs to connect with an FE circuit. Assuming only one CUI circuit needs service, the CUI circuit initially generates a high signal on ATTENTION line 312 of an available M-bus. Since the selected FE circuit is coupled to all CUI circuits through that M-bus, it does not automatically know which CUI circuit generated the request. Consequently, the selected FE circuit generates a high signal on BCS line 308 to allow the requesting CUI circuit to identify itself. During the identification process, each DATA line uniquely identifies one CUI circuit from each board. Since there are 8 data lines and 16 CUI circuits, two identification steps are required. Since the CUI circuits are constructed as eight boards with two CUI circuits per board, the first identification step may be used to identify one CUI circuit on each board, and the second identification step may be used to identify the other CUI circuit on each board. The first identification step begins with the generation of a high signal on BCS line 308. If the requesting CUI circuit is a member of the first group of CUI circuits, then it generates a high signal on its associated DATA line at that time. Otherwise the circuit waits for the second identification step. The second identification step begins when the FE circuit generates a high signal on SYNC line 316. During that time, the CUI circuits in the second group may identify themselves by generating a high signal on the assigned DATA line. Thereafter, the signals on BCS line 308 and SYNC line 316 are dropped, and the FE circuit then may establish communication with the identified CUI circuit.

Once an FE circuit knows that a CUI circuit needs service, or any other time a FE circuit wants to connect with a specific CUI circuit, it generates the sequence of signals shown in Fig. 8B. As shown in Fig. 8B, a high signal is generated on SELECT line 300, and simultaneously therewith the FE circuit places the address of a requested CUI circuit on data lines 334-350. The addressed circuit responds by generating a high signal on SRS line 308, and the two circuits may communicate as necessary. The raising of the SEL signal is performed by microcode as is the detection of the SRS signal. The raising of the SRS signal is performed by the arbitration logic in the circuit being selected.

Fig. 8C shows the sequence of signals when a requested circuit is busy. In this instance, the requested circuit responds to the SEL signal by generating a high signal on ACK line 320. Thereafter, the FE circuit generates a low signal on SELECT line 300 (i.e., it drops the request) which causes the requested circuit to drop the signals on ACK line 320. Of course, the requesting circuit may try again at a later time. The raising of the SEL signal is performed by microcode as is the detection of the busy signal (ACK from the CUI) . The indication of busy is performed by the arbitration logic in the requested circuit.

Fig. 8D shows the sequence of signals when processing is complete or when the FE circuit otherwise wants to disconnect from the requested circuit. The FE circuit drops the SEL signal which, in turn, causes the requested circuit to drop the SRS signal. The dropping of the SEL signal is performed by microcode as is the detection of the response on the SRS line. The dropping of the SRS signal is performed by the arbitration logic on the requested circuit and is an indication that there are no current operations pending. In this embodiment, a particular CUI circuit may be reserved for a particular FE circuit (via commands issued while the two circuits are linked) , so lowering the SRS signal does not necessarily mean that the CUI circuit is free to operate with other devices.

Fig. 8E shows the sequence of signals when an FE circuit writes to a control register in a CUI circuit. This is how operating parameters are passed to the CUI circuits. A high signal is generated on BCS line 308, and simultaneously therewith a read or write command (e.g., a zero or one) and starting register number are provided on DATA lines 334-350. Thereafter, the CUI circuit drops the SRS signal to indicate that the command and address have been accepted. The CUI circuit then generates a high signal on READY line 324 to indicate that it is ready for the first byte of data. The FE circuit generates a high pulse on SYNC line 316 and simultaneously places the first byte of data on data lines 334-350. The CUI circuit responds by generating a high pulse on ACK line 320 to indicate that the byte has been received. The sequence continues with the successive generation of SYNC and ACK signals until the data transfer is complete. It should be noted that only the starting address is supplied to the CUI circuit. The CUI circuit increments an internal address counter upon the occurrence of each SYNC signal to determine the next storage location. When the FE circuit has transferred all the data, it drops the BCS signal to inform the CUI circuit that the data transfer is complete. The CUI circuit responds by generating a high signal on SRS line 304 and by dropping the READY signal. The CUI circuit also places status information on data lines 334-350 to indicate the status of the data transfer.

Fig. 8F shows the sequence of signals on the M-bus when data (i.e., operating parameters) are read from the CUI control registers. In this case, the starting address refers to the first register read in the CUI circuit. Fig. 8G shows the sequence of signals on the M-bus when an error is detected upon a read or write to the CUI control registers. The detection of an error is indicated by the generation of a high signal on ATTENTION line 312 and then the generation of the high signal on SRS line 304. Fig. 8H shows the sequence of signals on the M-bus when an FE circuit writes to the SCA in a particular CUI board. As with reads and writes to CUI registers, only a starting address is provided to the CUI circuit. However, the command and address are not provided simultaneously in this sequence. Instead, the command is supplied when the BCS signal goes high, the high order address bits are provided when the BCS signal goes low, and the low order address bits are provided when the BCS signal again goes high. The changes in the SRS signal acknowledge receipt of the command and address bytes. Fig. 81 shows the sequence of signals on the M-bus when data is read from the SCA. Fig. 8J shows the sequence of signals on the M-bus when an error is detected upon a read or write to the SCA. In this embodiment, ATTENTION line 312 does not connect directly to the SCA hardware, so an indication of an error is provided by an early rise of the signal on SRS line 304. Figs. 8K and 8L are timing diagrams showing the sequence of signals on the M-bus when data is to be transferred to and from a host channel, respectively. Transferring data to the channel is initiated by writing an appropriate command into a sequence control register in the CUI circuit. Additional parameters (direction, streaming mode, etc.) can be specified in other registers. The channel data follows the transmission of the CUI sequence control register data.

Fig. 8M shows the sequence of signals on the M-bus when data is transferred from a host channel with truncation. Data transfer from the host channel is truncated by generating a high signal on SRS line 304.

Fig. 8N shows the sequence of signals on the M-bus when an error is detected during the transfer of data to or from a host channel. As with reading or writing data to the CUI control registers, an error is indicated by the rising of the signal on ATTENTION line 312.

Before discussing the timing diagram shown in Fig. 80, a discussion of channel paths is in order. When host computers 21, 22 and 23 are powered up, they issue a set-group-path-ID command to storage directors 58, 60 and 62. In known systems, the command identifies the host to the devices which make up the path from a particular host channel to its associated disk drive, and the path does not change once it is set. In the present invention, the FE circuits are not dedicated to a particular host channel and may communicate with any CUI circuit. Thus, an FE circuit which received a data request from a host and which disconnected from the host to service the request must be able to reconnect with a CUI circuit connected to that host to complete the operation. To accomplish this, intermediate processor 22 intercepts the set-group-path-ID commands when issued, and each FE circuit builds a table as shown in Fig. 9 which describes which CUI circuits are associated with which host. For example, host 21 has a group ID of 0, and its channels 24 and 25 are coupled to CUI circuits 78A and 78B, respectively. Each CUI circuit stores its group ID in an appropriate register. An FE circuit which serviced a data request from host 21 thus may transfer data to host 21 by reconnecting with any available CUI circuit having group ID 0.

Fig. 80 shows the sequence of signals on the M-bus when an FE circuit wants to reconnect with a CUI circuit. Rather than serially poll each CUI circuit, a parallel approach to reconnection is employed without requiring a resource manager. The FE circuit initially generates a high signal on BROADCAST line 328 and simultaneously places the group ID on data lines 334-350. The same group ID is sent to all CUI circuits. Thereafter, all available CUI circuits compare the broadcast group ID to their own group ID to determine whether they belong to the group. The CUI circuits that have valid comparisons then attempt to connect with their associated host channels. Thereafter, the successful CUI circuits generate a high signal on their respective ATTENTION lines 312. The FE circuit then proceeds, with the identification scheme discussed in connection with Fig. 8A (i.e., the available CUI circuit generates a high signal on its associated data line to identify itself) . The FE circuit knows from the group path ID table (Fig. 9) which CUIs it can use for reconnection to the host. The FE circuit chooses a CUI that has the correct group ID and has a high signal on its ATTENTION line 312, places the desired CUI ID on the DATA lines, and generates a high signal on SELECT line 300 to begin a normal selection process. The identified CUI responds to the signal on SELECT line 300 by generating a high signal on SRS line 304 to indicate that it is ready and idle. The FE circuit then generates a high signal on BCS line 308 to begin the normal sequence to read the control register of the selected CUI circuits as discussed in connection with Fig. 8F to ensure that the attention signal was raised in response to the BROADCAST signal and not for some other reason. The FE circuit then generates a high signal on BCS line 308 to begin a normal sequence to write to the CUI control registers to enable a CUI-initiated selection sequence to the host. After the CUI circuit generates the high signal on ACK line 320, the FE circuit drops the BROADCAST signal. This informs the other responding CUI circuits that they have not been selected, and those CUI circuits may go on to other tasks. When host communication is finished, the CUI circuit generates a high signal on SRS line 304 and places status information on the DATA lines.

CHANNEL INTERFACE BUS

Fig. 10 shows the construction of the CIB. As noted previously, the CIB connects between main processor 74 and the FE and CH circuits. The CIB comprises a VALID line 404' for indicating that a valid information packet for main processor 74 is present on the data lines; SOURCE/DEST1 and SOURCE/DEST2 lines 408 and 412, respectively, for indicating the destination of the data transfer; CMD1 and CMD2 lines 416 and 420, respectively, for indicating the data packet type (e.g., data, set data buffer pointer, cache request, or miscellaneous command); a reserved line 424; a PARITY line 428 for bidirectional DATA lines 430-444; a DIRECTION line 448 for indicating a current transfer direction on the CIB (generated by the CIB arbitration logic on the FE and CH circuits) ; an MC2IHNEXT line 452 for indicating that main processor 74 will transmit a byte of information on the next clock cycle; and a clock line 456 for synchronizing data transfer activities between main processor 74 and the FE and CH circuits.

Main processor 74 may not request a connection by generating a signal on MC2IHNEXT line 452 until the signal on DIRECTION line 448 has been deactivated by the FE or CH circuit. When main processor 74 requests the ^• bus by generating the signal on MC2IHNEXT line 452, the direction of data transfer reverses at the start of the next main processor cycle. This ensures that the FE or CH circuit has priority over bus transfers and that no more than one main processor machine cycle is lost during changes in the direction of bus transfers.

The CIB can transfer data at a rate of 20 megabytes per second, but the circuits attached to it do not necessarily transfer data at that rate. In fact, main processor 74 operates at a slower rate then the FE and CH circuits. Consequently, each FE circuit includes an input/output buffer and control circuit 168 (Fig. 5) , and each CH circuit includes an input/output buffer and control circuit 222 (Fig. 6) .

These buffer and control circuits ensure that the FE and CH circuits are not locked to the main processor 74 clock rate.

Fig. 11 shows a portion of an input/output buffer and control circuit which may be used with any of the FE or CH circuits to accommodate the different data transfer rates. An input FIFO 470 may be provided for communicating data from main processor 74 to the FE or CH circuits. FIFO 470 is a conventional FIFO which produces an (active high) empty signal on an empty line 471 for indicating when the FIFO is empty. The signal on line 471 is propagated through an inverter 472 whose output is coupled to an input terminal 473 of flip-flop 474. The Q output terminal 4.75 of flip-flop.4.7 is coupled to the input terminal of flip-flop 476. The resulting output signal on the Q output terminal 477 functions as a READ FIFO signal and indicates to the reading circuit that FIFO 470 contains data and may be read. In this embodiment, the FE and

CH circuits immediately begin reading the data from FIFO 470 when the READ FIFO signal is generated. Flip-flops 474 and

^• 476 are clocked by the bit-slice processor clock on a line 478 from the FE or CH circuit to ensure that the READ FIFO signal arrives synchronously to the FE or CH circuit. Unfortunately, if the buffer were constructed only as described so far, the FE or CH circuit would continue trying to read the data from the FIFO when it is empty because the empty signal would not appear at the Q output terminal 477 of flip-flop 476 in time. To prevent this situation, a reset line 479 is connected between the output terminal of inverter 472 and an asynchronous reset terminal of flip-flop 474.

CONSOLE BUS

Figs. 12A-B show the construction of the console bus 40. More specifically, Fig. 12A shows the portion of console bus 40 coupled between the console and the FE and CH circuits (94A-H, Fig. 3), and Fig. 12B^'shows the portion of console bus 40 coupled between console 36 and main processor 74 (98, Fig. 3). As shown in Fig. 12A, the portion of console bus 40 coupled between console 36 and the FE and CH circuits comprises a DATA line 500 for indicating whether the data lines contain a data byte or a command byte; an ARB line 504 for indicating the direction of the information transfer; a VAL line 508 for indicating that valid information is present on the data lines; an ACK line 512 for indicating that the receiver has the data and is busy processing it (when the receiver drops the signal on this line, the receiver is ready to receive another byte) ; an ATTENTION line 516 for indicating that the FE and CH circuit wants to send a message to console 36; DATA lines 520-534; and a PARITY line 536 associated with data lines 520-534.

The FE and CH circuits may only send a message across the bus when console 36 has set ARB to receive. Once console 36 grants the bus to the requesting circuit, it maintains the ARB signal until the signal on ATTENTION line 516 drops.

As shown in Fig. 12B, the portion of console bus coupled between the console and the FE and CH circuits comprises DIN lines 600-614 for communicating data from console 36 to main processor 74; a CIN line 616 for indicating whether DIN lines 600-614 contain a command or data; a DSI line 618 for indicating that DIN lines 600-614 contain valid information; a PIN line 620 for providing an odd parity bit for the DIN signals; an EN line 622 for indicating that main processor 74 is ready to receive a data byte; DO lines 624-638 for communicating information from main processor 74 to console 36; a CO line 640 for indicating whether DO lines 624- 638 contain a command or data; a DSO line 642 for indicating whether DO lines 624-638 contain valid information; a PO line 6'44 for providing an odd parity bit for the DO signals; and an ACK line 646 for indicating that main processor 74 received a byte of information.

DATA INTEGRITY

Since the host computers believe they are communicating directly with the storage directors, the hosts assume that data communicated to intermediate processor 22 has been immediately written to mass storage. In reality, the data has only been written into track buffer 77 in main processor 74, and such internal memories have a greater risk of failure than typical mass storage devices. To enhance data integrity, two copies of the written data are stored on two separate sets of memory chips on two different boards. The first copy, comprising track images, is stored in track buffer 77 of main processor 74, and the second copy is stored in the NVS memory 138 in the FE circuits. If desired, temporary files need not be stored in NVS memory 138. At the conclusion of the host application program, the file can be retained or discarded. If it is retained, it can. be destaged to mass storage before returning channel end to the program. Unlike main processor 74, the NVS memories do not store track images. Instead, the NVS memories contain only the minimum data needed to reconstruct the tracks needed to update the mass storage devices. The data stored in the NVS memories also include error correction codes. In this embodiment, 6 bits of error correction code protect every 16 bits of NVS data. When a track has been written from track buffer 77 to the mass storage device, the storage space in NVS memory 138 for the backup data for that track is de-allocated. The data stored in the track buffer 77 of main processor 74 is backed up by an independent power source which keeps console 36 and main processor 74 working for up to ten minutes. When a power failure is detected, the software in main processor 74 searches track buffer 77 for tracks which have yet to be written to mass storage. When it finds data yet to be written to mass storage, it sends the data to console 36 which stores it on disk drive 50.

NVS memory 138 in each FE circuit is backed up with a lithium battery which keeps the memory valid for 48 hours. Each FE circuit has its own set of logic to determine when it needs this secondary power source.

Figs. 13A and 13B describe a particular embodiment of a method according to the present invention for ensuring data integrity in case of a power failure or other error. As shown in Fig. 13A, the first step is to detect an error in step 700. Error detection may be accomplished, e.g., through hardware detection such as a parity error or through software detection such as a time-out on a data transfer. The FE circuit which detected the error reports the error to the host computers 21-23 in a step 702 and reports the error to console 36 in a step 704. Console 36 is responsible for determining what happened and then supervising the recovery process. Thus, console 36 ascertains in a step 706 whether the error occurred as a result of an FE circuit failure or a main processor failure. If the error occurred as a result of an FE circuit failure, then console 36 takes the failed FE offline in a step 708 and instructs main processor 74 to destage all tracks from track buffer 77 that were modified by the failing FE circuit in a step 710. If it is ascertained that the main processor 74 failed, then console 36 stops and restarts each CH circuit 90 in a step 712. This terminates any communication that the CH circuit was involved in, and prepares it to start communication when requested by an alternate main processor. Console 36 then notifies each FE circuit 82 of the failure in a step 714. Each FE circuit then de-selects any component with which it is communicating. assumes an idle state and acknowledges the notification in a step 716. After all FE/CH circuits have disconnected, console 36 notifies each FE/CH circuit to switch its interface to the alternate main processor in a step 718. The alternate main processor starts in a step 720 and establishes communication with each FE and CH circuit in a step 722. The alternate main processor then establishes communication with each mass storage device connected to each CH circuit in a step 724 and requests copies of all track images stored in each FE circuit which have not been deallocated in a step 726. Since each FE circuit has its own NVS memory 138, and since the same or different tracks of data may be changed by the host computers at different times, care must be taken to update the mass storage devices in the proper sequence. Thus, the alternate main processor sorts all track images into chronological order in a step 730. It is then ascertained in a step 732 whether the alternate main processor has access to the mass storage device. If it does not have access, then it will mark the track as "pinned" in a step 734. If it has access, the alternate main processor writes the information to the mass storage devices in a step 736. After the track has been written successfully, the alternate main processor directs the appropriate FE circuit 82 to deallocate the storage space in NVS memory 138 for the track in a step 738. The second main processor repeats these steps until all tracks have been written to the mass storage devices, or have been marked as "pinned." After this process has been completed the alternate main processor notifies console 36 in a step 742. Console 36 then notifies each FE circuit 82 that it should resume communications with the host systems in a step 744.

While the above is a complete description of a preferred embodiment of the present invention, various modifications may be employed. For example, intermediate processor 22 may be modified to operate with I/O protocols other than the OEMI standard. Consequently, the scope of the invention should not be limited except as described in the claims.

Claims

WHAT IS CLAIMED IS:

1. An intermediate processor for coupling between a plurality of host computer channels and a storage director which controls I/O operations to a mass storage device comprising: channel coupling means for coupling to the plurality of host computer channels; a plurality of front end circuits, each front end circuit being coupled to the channel coupling means; a main processor coupled to the plurality of front end circuits, the main processor having a main storage memory for storing data from the mass storage device; storage director coupling means, coupled to the main processor, for coupling the main processor to the storage director; and wherein each front end circuit includes channel selecting means for selecting any one of the host computer channels for communication therewith.

2. The intermediate processor according to claim 1 wherein the main processor includes a buffer for storing data from the mass storage device.

3. The intermediate processor according to claim 2 wherein the main processor further comprises data storing means, coupled to the buffer, for storing all data communicated from the mass storage device to the host channel in the buffer.

4. The intermediate processor according to claim 2 wherein the main processor further comprises data storing means, coupled to the buffer, for storing full tracks of data from the mass storage device in the buffer.

5. The intermediate processor according to claim 4 wherein each front end circuit includes a nonvolatile storage memory for storing a change data record for reproducing changes made to one of the tracks stored in the buffer.

6. The intermediate processor according to claim 5 wherein the change data record comprises less than a full track of data.

7. The intermediate processor according to claim 6 wherein the change data record includes a time stamp indicating when a change was made to the associated track stored in the track buffer.

8. The intermediate processor according to claim 7 wherein each front end circuit includes main processor failure detecting means for detecting a main processor failure.

9. The intermediate processor according to claim 8 further comprising error management means, coupled to each front end circuit, for updating tracks of data in the mass storage device with associated change data records stored in the nonvolatile storage memory of each front end circuit.

10. The intermediate processor according to claim 9 wherein the error management means comprises polling means for requesting from each front end circuit a list of time stamps corresponding to each change data record stored in the associated nonvolatile storage memory.

11. The intermediate processor according to claim 10 wherein the error management means further comprises master time stamp list generating means for generating a master time stamp list from the time stamp list from each front end circuit.

12. The intermediate processor according to claim 11 wherein each front end circuit further comprises: time stamp comparing means, coupled to the nonvolatile storage memory, for comparing a selected time stamp from the master time stamp list with a time stamp stored in the nonvolatile storage memory; and track update means, coupled to the time stamp comparing means, for updating a data track in the mass storage device with the change data record corresponding to the selected time stamp when the selected time stamp matches a time stamp stored in the nonvolatile storage memory.

13. The intermediate processor according to claim 2 wherein the channel coupling means comprises: a plurality of control unit interface circuits, each control unit interface circuit being coupled to one of the plurality of host channels; and front end coupling means for coupling each control unit interface circuit to the plurality of front end circuits so that any front end circuit may communicate with any control unit interface circuit.

14. The intermediate processor according to claim 13 wherein the front end coupling means comprises a control unit interface bus having a plurality of data lines, each data line corresponding to a selected one of the control unit interface circuits.

15. The intermediate processor according to claim 14 wherein each front end circuit further comprises broadcast means for generating a broadcast signal, and wherein each control unit interface circuit includes means for generating an identifying signal on its associated data line in response to the broadcast signal when the control unit interface circuit is available for a linked communication.

16. The intermediate processor according to claim 15 wherein each front end circuit includes linked communication establishing means for establishing a linked communication with a control interface circuit which generated an identifying signal on the control unit interface bus. 26

17. A control circuit for controlling the transfer of data stored in a buffer by a first data processing element to a second data processing element, wherein the first data processing element writes the data in the buffer at a first

5 clock rate and the second data processing element reads the data from the buffer at a second clock rate, the first clock rate being slower than the second clock rate, wherein the second data processing element generates a clock signal occurring at the second clock rate, and wherein the buffer

10 generates a first buffer signal when data is stored in the buffer and a second buffer signal when no data is stored in the buffer, the control circuit comprising: a first latching element comprising: a first input terminal coupled to the buffer for 15 receiving the first and second buffer signals therefrom; a first clock terminal coupled to the second data processing element for receiving the clock signal therefrom; wherein the first latching element generates, at a

20 first output terminal in response to the clock signal, a first first latching signal when the first buffer signal is applied to the first input terminal and a second first latching signal when the second buffer signal is applied to the first input terminal;

25 a forced signal terminal coupled to the buffer for receiving the first and second buffer signals therefrom; wherein the first latching element immediately generates the second first latching signal at the first output terminal when the second buffer signal is applied

30 to the forced signal terminal; a second latching element comprising: a second input terminal coupled to the first output terminal; a second clock terminal coupled to the second data 35 processing element for receiving the clock signal therefrom; wherein the second latching element generates, at a second output terminal in response to the clock signal, a first second latching signal when the first first latching signal is applied to second input terminal and a second second latching signal when the second first latching signal is applied to the second input terminal.

18. The control circuit according to claim 17 wherein the first latching element comprises a first flip-flop having an asynchronous reset terminal coupled to the buffer for receiving the first and second buffer signals therefrom, and wherein the second latching element comprises a second flip- flop having an input terminal coupled to an output terminal of the first flip-flop.