WO1994014162B1 - Pattern search and refresh logic in dynamic memory - Google Patents
Pattern search and refresh logic in dynamic memoryInfo
- Publication number
- WO1994014162B1 WO1994014162B1 PCT/US1993/011820 US9311820W WO9414162B1 WO 1994014162 B1 WO1994014162 B1 WO 1994014162B1 US 9311820 W US9311820 W US 9311820W WO 9414162 B1 WO9414162 B1 WO 9414162B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- bit
- storage device
- word
- memory
- Prior art date
Links
- 230000001808 coupling Effects 0.000 claims 3
- 239000007787 solid Substances 0.000 claims 3
- 230000003287 optical Effects 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000000737 periodic Effects 0.000 abstract 1
Abstract
The invention is a dynamic storage device (Figs. 3-10) requiring periodic refresh, and including logical operation circuitry (e.g., 21 and 24 of Fig.4) within the refresh circuitry (19 of Fig. 4). The individual storage positions of the storage device are periodically read by a refresh amplifier (RE of Fig. 4), and then a logical operation is performed on the refresh data before the data is applied to the write amplifier (WR of Fig. 4). This operation allows implementation of associative data base searching by cyclically executing data compare and other logical operations within the refresh circuitry. Storage systems for use with such devices (e.g., Fig. 12) are also disclosed.
Claims
AMENDED CLAIMS
[received by the International Bureau on 23 June 1994 (23.06.94); original claims 1-12, 15-17 and 22-33 amended; original claims 13 and 14 cancelled; new claims 36 and 37 added; remaining claims unchanged (5 pages)]
1. An information storage and searching apparatus comprising: (a) an information-storage device;
(b) at least one electronic memory device, which device is integra on a semiconductor chip, electronically coupled to the storage device, and having a plurality of multiple-bit word storage locations, wherein each wor storage location consists of a plurality of uniform-length subunits; (c) said memory device having associated with each of the word storage locations: (i) a comparator circuit coupled to compare a comparand having length equal to the subunits with information stored in each of the subunits, and (ii) a single-bit storage element coupled to the comparison circuit so as to indicate a match between the comparand and information in least one of the subunits;
(d) said memory device being controllable to output in sequence information stored in at least a selected portion of each word storage locatio having a subunit matching the comparand; and
(e) a control device configured (i) to control the couplings betwee the storage device and the memory device to transfer information stored in the storage device to the memory device, (ii) to pass a comparand to the memory device, and (iii) to cause the memory device to perform said outpu sequence.
2. The apparatus of claim 1 wherein the information storage device includes at least one magnetic storage device.
3. The apparatus of claim 1 wherein the information storage device includes at least one optical storage device.
4. The apparatus of claim 1 wherein the information storage device includes at least one multiple-platter storage device. 5. The apparatus of claim 1 wherein the information storage device includes at least one solid state memory device.
6. The apparatus of claim 1 wherein the information storage device includes at least one magnetic tape storage.
7. The apparatus of claim 1 wherein the information storage device includes at least one flash memory device.
8. The apparatus of claim 4 wherein the information storage device includes at least one read head associated with each platter of the multiple-platter storage device.
9. The apparatus of claim 1 wherein the memory device comprises:
(a) a multitude of bit-storage cells on a single semiconductor chip distributed among a plurality of logical word cells;
(b) wherein the bit cells of each word cell are arranged in at least one column comprised of a plurality of bit cells;
(c) a plurality of amplifiers on the chip, each column associated with one of said amplifiers;
(d) wherein each of the amplifiers may be electrically coupled to a bit cell in any column with which that amplifier is associated; (e) an addressing circuit configured to control the couplings, respectively, between each of the amplifiers associated with columns of at least one word cell and each bit cell in a row of each of the associated colum
(f) wherein the addressing circuit is coupled to permit coupling o the amplifiers to bit cells in any row of the associated columns; and (g) a comparison circuit on the chip, coupled to the amplifiers in a least one word cell and having an output line, which circuit is configured to compare a selected comparand with bits amplified by said amplifiers and to generate an electrical signal on said output line when the comparand match the bits amplified from the bit cells in at least one row of the columns. 10. The apparatus of claim 1 wherein the memory device comprises at le one associative memory on an integrated circuit.
11. The apparatus of claim 1 wherein the control device switches a switchable data bus.
12. The apparatus of claim 1 wherein the control device includes at least integrated processor circuit and a program store containing at least one sequence o instructions.
15. The apparatus of claim 1 wherein the comparison circuit is electricall connected to a refresh circuit connected tc periodically refresh information at each word storage location. 16. The apparatus of claim 8 wherein said control device comprises:
(a) means for enabling the read heads of a plurality of the platters the same time;
(b) means for .assembling the information read by the enabled rea heads in a predetermined sequence; and (c) means for transferring the assembled information to predeter¬ mined locations in the memory device. 17. The apparatus of claim 1 wherein:
(a) the memory device comprises a plurality of banks of solid state memory devices;
(b) the control device switches a switchable bus capable of connect¬ ing the storage device to any selected one of the memory banks; and (c) the control device is coupled to control one of the memory banks while at least one other memory bank is coupled to the storage device.
18. A data storage system comprising:
(a) memory means for storing a plurality of multiple bit words in predetermined multiple-bit word storage locations; and (b) means for searching the multiple-bit word storage locations for any predetermined pattern of bits of data and for transferring any matching bit pattern to a predetermined location in the memory means relative to its original location.
19. A data storage device comprising: (a) dynamic data storage means, integrated on a single semiconduc¬ tor chip, for storing a plurality of multiple-bit data words in a plurality of addressable predetermined multiple-bit word storage locations, said locations requiring refreshing to retain data, wherein bits of the words form an array;
(b) addressing circuit means integrated on the chip for periodically addressing each of said locations;
(c) refresh circuit means, integrated on the chip and randomly connectable by said addressing circuit means to each of said locations, for periodically refreshing the data stored in each of said locations, wherein said refresh circuit means includes a plurality of sense amplifiers, each of which is associated with one of said locations;
(d) means for reading a plurality of bits of each data word simulta¬ neously into sense amplifiers associated with the data word; and
(e) logic means, integrated on the chip and electrically coupled to the sense amplifiers, for comparing, for each data word, a first subset of bits in the sense amplifiers to at least one predetermined value, and for setting a second subset of bits in the sense amplifiers to a predetermined value.
20. The apparatus of claim 19 wherein the memory means comprises means for storing a plurality of multiple-bit words, each in a row of a bit array, and wherein the refresh circuit means comprises means for refreshing a plurality of columns of the bit array at a time.
21. The apparatus of claim 19 wherein the reading means comprises means for reading a byte of each data word simultaneously.
22. A method of storing and searching on data comprising:
(a) storing electronic data in a data storage device;
(b) transferring the data from the data storage device to a plurality of multiple-bit word storage locations of a content-addressable memory circuit; and (c) searching every bit of each word storage location containing the transferred data for a selected subset of that data.
23. The method of claim 22 wherein storing data includes storing data on at least one magnetic storage device.
24. The method of claim 22 wherein storing data includes storing data on at least one optical storage device.
25. . The method of claim 22 wherein storing data includes storing data on at least one multiple-platter storage device.
26. The method of claim 22 wherein storing data includes storing data on at least one solid state memory device. 27. The method of claim 22 wherein storing data includes storing data on at least one magnetic tape.
28. The method of claim 22 wherein storing data includes storing data on at least one flash memory device.
29. The method of claim 25 wherein transferring data includes reading data from a plurality of the platters simultaneously.
30. The method of claim 22 wherein searching includes causing the content-addressable memory to compare a comparand with data stored in the memory and indicate all word storage locations containing a match between the comparand and data stored in at least one subset of such word storage locations. 31. The method of claim 22 further comprising periodically refreshing data stored at each location of the memory, and wherein searching includes comparing the stored data and the comparand during refreshing.
32. The method of claim 29 wherein transferring includes:
(a) enabling read heads of a plurality of the platters at the same time;
(b) assembling data read by the enabled read heads in a predeter¬ mined sequence; and
(c) transferring the assembled data to predetermined locations in the data storage device. 33. The method of claim 22 wherein the content-addressable memory includes a plurality of content-addressable memory banks and:
(a) wherein transferring includes selecting a first of a plurality of th memory banks as a target for the transferred data;
(b) wherein searching includes searching a second of the memory banks while transferring; and
(c) further comprising switching the first and second memory banks after a time so that transferring uses the second bank as a target and searching operates on data in the first bank.
34. A method of storing and manipulating data comprising:
(a) storing a plurality of multiple-bit data words in a plurality of predetermined multiple-bit word storage locations;
(b) periodically accessing each of said locations to refresh the data stored in each of said locations by reading a plurality of bits of each data word simultaneously into sense amplifiers associated with each of said locations;
(c) for each data word, comparing a first subset of bits in the sense amplifiers to a predetermined value; and
(d) setting a second subset of bits in the sense amplifiers to values determined by the results of the comparison.
35. The method of claim 34 wherein steps (c) and (d) are performed a plurality of times, each time with another predetermined value, while the bits remain in the sense amplifiers.
36. The apparatus of claim 1 wherein each of said subunits comprises a byte.
37. The method of claim 22 further comprising outputting in sequence data stored in at least a selected portion of each word storage location containing said selected data subset.
STATEMENT UNDER ARTICLE 19
The relationship of the attached claims to the original claims are as follows: Claims 13 and 14 have been canceled. Claims 36 and 37 are new claims. Claims 18- 21 and 34-35 have not been changed. All of the remaining claims, claims 1-12, 15-17, and 22-33 have been substantially amended. Each claim attached corresponds to the correspondingly numbered claims of the original application.
Because of the word limit of Section 205 of the PCT Administrative Instructions, it is not possible to point out with specificity all of the amendments to the claims. However, the claims have been substantially revised to better define the invention. Specifically, applicant has amended the claims to clarify that the claimed invention contains a system of searching any subset of multi-bit words for a comparand, in some instances while refreshing the circuit if it is a dynamic one. Each bit is stored in a single storage location.
Claim 18 refers to a system for comparing a subset of multi-bit words to a comparand and transferring matching patterns to another bit location. Claims 19-21 and 34-35 refer to a system for comparing a subset of multi-bit words to a comparand and writing the result of the comparison at another bit location.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950702379A KR100230767B1 (en) | 1992-12-07 | 1993-12-06 | Method of data storage and search for dynamic memory |
| JP6514306A JPH08504992A (en) | 1992-12-07 | 1993-12-06 | Pattern retrieval and refresh logic in dynamic storage |
| EP94903480A EP0676081A4 (en) | 1992-12-07 | 1993-12-06 | Pattern search and refresh logic in dynamic memory. |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/987,008 US5758148A (en) | 1989-03-10 | 1992-12-07 | System and method for searching a data base using a content-searchable memory |
| US07/987,008 | 1992-12-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1994014162A1 WO1994014162A1 (en) | 1994-06-23 |
| WO1994014162B1 true WO1994014162B1 (en) | 1994-08-04 |
Family
ID=25532983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1993/011820 WO1994014162A1 (en) | 1992-12-07 | 1993-12-06 | Pattern search and refresh logic in dynamic memory |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5758148A (en) |
| EP (1) | EP0676081A4 (en) |
| JP (1) | JPH08504992A (en) |
| KR (1) | KR100230767B1 (en) |
| CA (1) | CA2150822A1 (en) |
| WO (1) | WO1994014162A1 (en) |
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1992
- 1992-12-07 US US07/987,008 patent/US5758148A/en not_active Expired - Fee Related
-
1993
- 1993-12-06 JP JP6514306A patent/JPH08504992A/en active Pending
- 1993-12-06 KR KR1019950702379A patent/KR100230767B1/en not_active IP Right Cessation
- 1993-12-06 CA CA002150822A patent/CA2150822A1/en not_active Abandoned
- 1993-12-06 EP EP94903480A patent/EP0676081A4/en not_active Withdrawn
- 1993-12-06 WO PCT/US1993/011820 patent/WO1994014162A1/en not_active Application Discontinuation
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