WO1994011985A2

WO1994011985A2 - Programmable audio timing generator for digital video tape recording

Info

Publication number: WO1994011985A2
Application number: PCT/US1993/010573
Authority: WO
Inventors: Eric Hung
Original assignee: Ampex Systems Corporation
Priority date: 1992-11-13
Filing date: 1993-11-08
Publication date: 1994-05-26
Also published as: WO1994011985A3

Abstract

An audio timing generator includes a programmable means, and a number of signal logics and counter logics. It provides timing information for audio data processing in a VTR recording channel. The present invention provides an audio timing generator adaptable to various industry standards including but not limited to 625/50 and 525/59.94 video tape recording systems. Further, it is adaptable to provide timing information correction within a field when audio timing delays in the recording channel had changed.

Description

PROGRAMMABLE AUDIO TIMING GENERATOR FOR DIGITAL YTPEO

TAPE RECORDING

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The present invention relates to a digital signal processing apparatus in a signal recording and reproducing system. More particularly, it relates to a digital timing generator providing timing information for processing digital video and digital audio signals in a video tape recorder (hereinafter referred to as the VTR).

DESCRIPTION OF THE RELATED ART

Digital information processing within a signal recording and reproducing system such as a VTR offers numerous advantages over its analog counterpart One advantage is the very little or no loss of digitized information content under digital processing environment. This environment includes digital processing of analog signals such as audio and video information. When audio and video information are recorded on a physical medium, playback degradation effects due to medium deterioration can be circumvented by copying digitized data sample values from the deteriorated medium to a new medium. As a result, these digital sample values are easier to manipulate than their analog representations. Furthermore, digital data processing of audio and video information in increasingly complex systems produces little loss of information.

While recording and reproducing technology becomes more complex, the processing time delays of audio signals with respect to their associated video signals can result. These time delays must be adjusted so that the video and audio signals are recorded onto a magnetic medium conforming to digital recording formatting rules. Similarly, in a reproducing channel, these time delays, if not compensated, would cause lip-sync problems.

Digital timing generators in recording channels are used for indicating where audio signals are in time relative to their associated video signals and vice versa. This knowledge enables the recording channels not only to adjust for the signal time delays before the actual recording process, but also to control timing relationships of various signal processing activities within the recording channel.

The conventional timing generators have relatively simple configurations because the sampling frequency of an analog audio signal is selected to be an integral multiple of the vertical synchronous signal for video signals. This relationship allows a pre¬ determined number of digital audio samples and their associated video information to be recorded during one vertical synchronous signal period (hereinafter referred to as a "field"). This field includes a video field and an audio field. For example, for a system conforming to 625/50 TV line standard such as a PAL system having an audio sampling frequency of 48 kHz, a total of 48,000/50 or 960 digital audio samples can be recorded into their associated audio field. Its PAL associated timing generators typically are configured to respond to information such as the vertical synchronous signal and the 960 audio sample count limit per audio field. The sample count given at any given time is indicative of the timing relationship between video and audio signals. That type of information can be used by other digital signal processing apparatus in the recording channel for timing control and adjustment purposes.

In some cases, the audio sampling frequency is not an integral multiple of the vertical synchronous signal for video signals. For example, for a 525/59.94 standard system such as a NTSC system having an audio sampling frequency of 48 kHz, this indicates that approximately 48,000/59.94 or 800.8 digital audio samples can be recorded for every field. This non-integer sample number of audio samples in a field complicates the timing generator configurations. In principle, instead of dividing up a sample, a field may contain either 800 or 801 audio samples or alternatively, 4004 audio samples for every 5 fields. Its NTSC associated timing generators are typically configured to indicate whether there are 4004 audio samples in eveiy 5 fields. Like the 625/50 timing generators, any displacements or any lack of displacements from the criteria are so indicated by the timing generators and used by other processing apparatus in the recording channels for timing control and adjustment purposes.

These audio timing generators in recording channels support numerous signal processing apparatus which contribute to video and audio recording and editing activities. One such apparatus may be a FIFO logic allowing audio information to be stored within one field. A FIFO collects digital audio samples at the sampling frequency. For every audio sample stored into the FIFO, a count is registered in its associated timing generator. After a pre-determined sample count (or a pre-determined time delay) relative to a field is reached in the timing generator, all of the audio samples in the FIFO may be 'bursted out' of the FIFO in a time compressed format at a high frequency to be recorded inside a fixed duration within the field. This pre-determined sample count may have a value less than 960 for 625/50 systems, or a value less than 800 or 801 for 525/59.94 systems.

Audio riming generators in VTR recording channels provide timing information of digital audio samples to be recorded in an audio field with respect to their associated video field. The timing information is used for activities including VTR audio recording and audio editing. In record mode, the timing information is based on an initial digital audio sample count at the start of an unit of fields. A field unit may have a field length of one field such as in a 625/50 system or a field length of 5 fields in a 525/59.94 system. All field units supposedly contain the same number of digital audio samples. And, within each field, this initial sample count indicates the inherent audio time delays relative to the field. In editing modes, field information from reproducing channels is incorporated so that digital audio samples can be properly synchronized to their associated reproduced fields before recording. Insert edit is one of the editing modes. It inserts or appends a data stream into a reproduced data stream. Read-Modify- Write (hereinafter referred to as RMW) is another editing mode where a data stream segment is read from the reproduced data stream, and may be modified before being written back to the same locations of the reproduced data stream.

Unfortunately, a 625/50 timing generator is designed and used for the 625/50 standard whereas a 525/59.94 timing generator is designed and used only for the 525/59.94 standard. There is no flexibility for a timing generator to interchange between the two line standards. For that matter, there is a need for a general purpose audio timing generator in digital video tape recording receptive to various standards in the industry.

In addition, conventional audio timing generators provide a pre-fixed time delay offset from the beginning of a vertical synchronous signal period before audio samples arc time compressed to be recorded. Each time delay offset takes into consideration of inherent time delays uniquely generated by their associated audio data processing activities. If an audio data processing activity is added to, deleted from or changed in the recording channel, then the inherent time delays may be altered causing its associated pre- fixed time delay offseted timing generator inoperable. Therefore, a need exists for a timing generator capable of time base correction within a field.

SUMMARY OF THE TN NTTON

The present invention provides an audio timing generator adaptable to various industry standards including but not limited to 625/50 and 525/59.94 video tape recording systems. Further, it is adaptable to provide timing information correction within a field when audio timing delays in the recording channel had changed.

An audio timing generator according to the present invention includes a CPU, and a number of signal logics, and counter logics. The counter logics include a sample counter logic and a field counter logic. Each counter logic further includes a counter and its associated comparison logic. The CPU responsive to operator demands issues operation mode commands such as record, insert edit or RMW to the timing generator. Depending on the operation mode command received, the timing generator makes use of various information available to it and produces timing information by its counters, namely, sample counter and field counter.

An audio sample count is registered in the sample counter for every audio sampling period. When the total audio sample count reaches a CPU established number representing the maximum audio sample count allowed in a field, the sample counter is then cleared and an additional field count is registered in the field counter. When the field counter reaches a maximum field count established by the CPU, the field counter is then cleared allowing the counter to start over. Both counters are free running and both arc clocked by the audio sampling frequency.

When the audio sampling frequency is not an integral multiple of the vertical synchronous signal, one field may not contain the same number of digital audio samples as any other field. Therefore, a comparison logic checks for field count values representing fields containing digital audio samples different in number from that of other fields.

Further, this comparison logic initiates changes to be made to the maximum audio sample count allowed in a field so that the sample counter can appropriately count to maximum counts corresponding to fields identified by the field count values. This logic operates even in cases where the audio sampling frequency is an integral multiple of the vertical synchronous signal because in those cases the, CPU, in response to the comparison logic, provides the same maximum audio sample count allowed in a field every time.

Depending on the operation mode command received by the CPU, signal logics such as a vertical sync logic, a 1st sample flag logic and a playback field logic are selectively enabled and disabled. In recording mode, only the vertical sync logic is enabled for generating defined pulses in response to transitions of field units. As mentioned in the foregoing, a field unit includes a pre-determined number of fields or vertical synchronous periods. The pre-determined number is dictated by the industry standard in use at the time. These pulses cause a pre-determined initial sample count to be loaded into the sample counter accounting for the time delay between video and audio information. If the time delay is altered, then this timing change can be corrected by altering the initial sample count value accordingly in the CPU.

In insert edit mode, the vertical sync logic and the playback field logic are enabled. The playback field logic in response to transitions of field units from a reproduced data stream causes the field counter to load a count value identifying selected field locations in the field units. This logic coupling with the operation of the vertical sync logic briefly described above allows data to be inserted or appended in appropriate timed relations to the reproduced data stream.

In RMW edit mode, the playback field logic and the 1st sample flag logic are enabled. Because of the fact that data are being read and written back to the reproduced data stream, the playback field logic allows the timing generator to lock to the field units from the reproduced data stream. In combination of the playback field logic, the 1st sample flag logic indicates the timing occurrence in the reproduced data stream the first digital audio sample relative to a field. This timing information allows a reproduced data stream, possibly modified and written back to the same location on the magnetic medium. Further, the 1st sample flag logic may change the audio sample timing in relation to a field by changing a pre-determined sample count value which is loaded into the sample counter during the RMW mode.

A better understanding of the present invention will become apparent to those skilled in the art by considering the following detailed description taken together with the accompanying drawing.

BRTEF DESCRIPTION OF THE DRAWING

FIGURE 1 is a functional block diagram of an embodiment in accordance to the present invention.

FIGURE 2 is a more detailed logic block diagram of the sample counter logic employed in the embodiment depicted in FIGURE 1.

FIGURE 3 is a more detailed logic block diagram of the field counter logic employed in the embodiment depicted in FIGURE 1.

DETATLED DESCRIPTION OF THE TNVENTTON

In the following description of embodiments of the present invention, like elements will be designated by like reference numerals, and the description of similar elements may not be repeated with reference to subsequent drawing figures related to the various embodiments of the invention. Further, a path in the drawings may represent a multi-lined data bus.

Referring now to drawings, and more particularly, to FIG. 1, there is shown a functional block diagram of an embodiment in accordance to the present invention. This audio timing generator generally designated 100 includes a CPU logic 105, a vertical sync logic 110, a 1st sample flag logic 120, a playback field logic 130, a sample counter logic 140 and a field counter logic 150. There are a number of inputs to the audio timing generator 100. An audio sampling frequency, ASF, is received by the audio timing generator 100 in that ASF is coupled to logics 110, 120, 130, 140, and 150 over paths 111 and 112, 111 and 113, 111 and 114, 111 and 115, 111 and 116, respectively. In preferred embodiments, ASF oscillates at 48 kHz. A signal VERTICAL SYNC is coupled to the vertical sync logic 110 over a path 117. A signal 1ST SAMPLE FLAG is coupled to the 1st sample flag logic 120 over a path 118. A signal PLAYBACK FIELD is coupled to the playback field logic 130 over a path 119. And, a signal COMMAND is coupled to the CPU logic 105 over a path 121.

The audio timing generator 100 outputs a signal AUDIO SAMPLE COUNT from the sample counter logic 140 over a path 122 and a signal AUDIO FIELD COUNT from the field counter logic 150 over a path 123. AUDIO SAMPLE COUNT and AUDIO FIELD COUNT provide timing information necessary for digital audio data processing in recording channels.

In addition to ASF via paths 111 and 112 and VERTICAL SYNC via path 117, two other signals are coupled to the vertical sync logic 110. A signal S 1 is fed into the vertical sync logic 110 from the CPU logic 105 via a path 124. AUDIO FIELD COUNT is fed into the vertical sync logic 110 from the field counter logic 150 via paths 123 and 125. The vertical sync logic 110 outputs a signal LOAD1 coupling to the sample counter logic 140 over a path 126.

In addition to ASF via paths 111 and 113 and 1 ST SAMPLE FLAG via path 118, a signal S2 is coupled to the 1st sample flag logic 120 from the CPU logic 105 via a path 127. The 1st sample flag logic 120 outputs a signal LOAD3 to the sample counter logic 140 over a path 128.

In addition to ASF via paths 111 and 114 and PLAYBACK FIELD via path 119, a signal S3 is coupled to the playback field logic 130 from the CPU logic 105 over a path 129. The playback field logic 130 outputs a signal LOAD2 to the field counter logic 150 over a path 131.

Regarding the sample counter logic 140, it has five inputs. Besides ASF via path 111 and 115, LOAD1 via path 126 from the vertical sync logic 110 and LOAD3 via path 128 from the 1st sample flag logic 120, the sample counter logic 140 also receives input from the CPU logic 105 via a path 132 and receives a signal S/L from the field counter logic 150 over a path 133. The sample counter logic 140 outputs two signals. One is AUDIO SAMPLE COUNT on path 122. The other is a signal ENABLE coupled to the field counter logic 150 over a path 134. Regarding the field counter logic 150, it has four inputs. Besides ASF via path 111 and 116, LOAD2 via path 131 from the playback field logic 130 and ENABLE via path 134 from the sample counter logic 140, the field counter logic 150 receives input from the CPU logic 105 via a path 135.

Regarding the CPU logic 105, it receives COMMAND via path 121, AUDIO

SAMPLE COUNT from the sample counter logic 140 via paths 122, 136 and, AUDIO FIELD COUNT via paths 123 and 137.

Referring now to FIGS. 1 and 2, in FIG. 2, there is shown a more detailed logic block diagram of the sample counter logic 140 employed in the embodiment depicted in FIGURE 1. This sample counter logic 140 includes an OR logic 210, a sample counter 220, and a comparison logic 230. LOAD1 is fed into an input terminal of the OR logic 210 via path 126. LOAD3 is fed into another input terminal of the OR logic 210 via path 128. The OR logic 210 output is coupled to the LOAD input terminal of the sample counter 220 via a path 215. The sample counter 220 also receives three other signals. One is a signal LOAD COUNT from the CPU logic 105 via paths 132, 217. LOAD COUNT is fed into the LOAD COUNT input terminal of the sample counter 220. Another is ASF via path 111 and 115 feeding into the triggering clock input terminal of the sample counter 220. Yet another is ENABLE from the comparison logic 230 via paths 134 and 219. ENABLE is fed into the CLR input terminal of the sample counter 220. The sample counter 220 outputs AUDIO SAMPLE COUNT via a path 122 making it available for data processing in recording channels. Further, AUDIO SAMPLE COUNT is coupled to the CPU logic 105 via paths 122 and 136. The comparison logic 230 includes a multiplex logic 235 and a comparing logic 240. The multiplex logic 235 receives a signal S/L COUNT via paths 132 and 241 and S/L from the field counter logic 150 via path 133. It outputs MAX COUNT to the comparing logic 240 via a path 247. The comparing logic 240 receives two signals, AUDIO SAMPLE COUNT via paths 122 and 243 and MAX COUNT from the multiplex logic 235 via path 247.

Referring now to FIGS. 1 and 3, in FIG. 3, tiiere is shown a more detailed logic block diagram of the field counter logic 150 employed in the embodiment depicted in FIGURE 1. This field counter logic 150 includes a field counter 310 and a comparing logic 320. There are five signals coupled into the field counter 310. LOAD2 is coupled into the LOAD terminal of the field counter 310 via path 131. ENJABLE is coupled into the ENABLE input terminal of the field counter 310 via path 134. A signal LOAD COUNT is coupled into the LOAD COUNT input terminal of the field counter 310 via paths 135 and 315. ASF is coupled to the triggering clock input terminal of the field counter 310 via paths 111 and 116. Lastly, a signal MAX is coupled into the CLR input terminal of the field counter 310 via a path 317. The field counter 310 outputs AUDIO FIELD COUNT via path 123 providing timing information for data processing in recording channels. Internal to the field counter logic 150, AUDIO FIELD COUNT in coupled to an input terminal of the comparing logic 320. External to the field counter logic 150, AUDIO FIELD COUNT is fed into the vertical sync logic via paths 123 and 125. Further, it is fed into the CPU logic 105 via paths 123 and 137. The comparing logic 320 receives AUDIO FIELD COUNT via paths 123 and 319 and receives a signal MAX COUNT from the CPU logic 105 via paths 135 and 321.

Regarding the CPU logic 105, it receives COMMAND via path 121, AUDIO SAMPLE COUNT from the sample counter logic 140 via paths 122, 136, and AUDIO FIELD COUNT via paths 123 and 137. In response to COMMAND, the CPU logic 105 appropriately couples SI to the vertical sync logic 110 via path 124, couples S2 to the 1st sample flag logic 120 via path 127, and couples S2 to the playback field logic 130 via path 129.

Referring now to FIGS. 1,2, and 3, operationally, COMMAND includes but not limited to operation mode commands such as record, insert edit and RMW edit. In record mode, SI and AUDIO FIELD COUNT together enable the vertical sync logic 110 via paths 124 and 123, 125 respectively. Also in record mode, S2 and S3 disable the 1st sample flag logic 120 and playback field logic 130 via pa s 127 and 129 respectively. The vertical synchronous signal, VERTICAL SYNC, of video signals, feeds into the vertical sync logic 110 via path 117. In response to the beginning transitions of field units in VERTICAL SYNC, the vertical sync logic 110 generates LOAD1 in timed relation with ASF. Further, the first fields of field units of VERTICAL SYNC may be identified by a specific AUDIO FIELD COUNT.

In a preferred embodiment, as described in the BACKGROUND OF THE

INVENTION, a VTR of a 625/50 system such as a PAL system, a 525/59.94 system such as a NTSC system or others can be used. If an NTSC system is used, an audio sampling frequency of 48 kHz means each field contains 800.8 digital audio samples or 4004 samples for every five fields. In practice, one of the five fields contains 800 audio samples and it is called a short field or a S field. The remaining four of the five fields contain 801 audio samples and they are called long fields or L fields. Therefore, the pre-determined VERTICAL SYNC periods is five. The first field of this unit of five fields is a S field and this field is identified by an AUDIO FIELD COUNT value of zero. In response to this S field, the vertical sync logic 110 generates LOAD1 which is synchronous to ASF, and has a pulse duration equaling to an ASF signal period. In other words, LOAD 1 references VERTICAL SYNC at every five signal periods or every five fields. LOAD1 feeds into the sample counter 220. This counter 220, clocked by ASF, increments for every digital audio sample sampled. In response to LOAD1, the sample counter 220 loads LOAD COUNT from the CPU logic 105 via paths 132 and 217 into LOJAD COUNT input terminal of the sample counter 220. LOAD COUNT is an empirical number in that it reflects the inherent audio data processing time delays in the recording channel of a VTR. In other words, for each field, because of the inherent audio time delays, the first audio samples instead of occurring immediately adjacent to the beginning transitions of fields, they occur at audio time delays after the beginning field transitions. LOAD COUNT represents the delays by resetting the sample counter 220 to a number adjustable by the CPU logic 105. This number represents the number of digital audio samples already accounted for their associated field when LOAD1 arrives into die counter. But, the associated field to which the number of samples belong is not the current field as registered by the field counter 310; instead this field is the field immediately preceding the current field. Therefore, LOAD COUNT indicates the audio time delays with respect to VERTICAL SYNC. These audio time delays may be altered because of addition, deletion or change of audio data processing apparatus and/or activities. The presence of the CPU logic 105 allows LOAD COUNT to be altered and thus providing time delay correction capability in cases of time delay changes.

S/L is fed into die multiplex logic 235 from the field counter logic 150 via path 133. S/L indicates whetiier the current field is a S field or a L field. In the case of a 525/59.94 system, the multiplexer logic 235 outputs a particular S/L COUNT value as MAX COUNT over path 247. S/L COUNT is fed into the multiplexer logic 235 from the CPU logic 105 over paths 132, 241. In this case, a S/L COUNT value of 800 is selected for S fields and a S/L COUNT value of 801 is selected for L fields. When AUDIO SAMPLE COUNT reaches MAX COUNT, the comparing logic 240 generates ENABLE over path 134 and patiis 134, 219. ENABLE clears the sample counter 220 and enables the field counter 310 allowing it to increment a field count.

In a preferred embodiment when a VTR of a 625/50 system is used, die S L COUNT from the CPU logic 105 over paths 132 and 241 has the same value of 960 whether the field is short or long. This way, die timing generator 100 can be used in eitiier a 525/59.94 system or a 625/50 system. Furthermore, other systems requiring a larger single field digital audio sample size than 960 audio samples or requiring a longer field length than 5 fields per field unit can also be accommodated witii die same functional configuration as die timing generator 100.

In insert edit mode, new video or audio information is to be inserted or appended to a reproduced signal data stream. In order to ensure proper time relationship between the insertion appendage and die reproduced data stream, there must be synchronization between the reproduced signal data stream and the signals to be inserted or appended. The timing generator 100, in case of the insert edit mode, S3 enables the playback field logic 130 over path 129. In addition, S 1 and AUDIO FIELD COUNT together again enable the vertical sync logic 110. And, S2 disables the 1st sample flag logic 120 over path 127.

The playback field logic 130 receives PLAYBACK FIELD from the reproducing channel via path 119. PLAYBACK FIELD is a signal having defined pulses indicative of die time locations of first fields of five field units in a reproduced data stream such as those found in a 525/59.94 VTR system. The playback field logic 130 generates LOAD2 in timed relation with ASF in response to PLAYBACK FIELD. LOAD2 is fed into the field counter logic 150 over path 131. The field counter logic 150, when enabled, resets d e field counter 310 to LOAD COUNT over patiis 135, 315. In a preferred embodiment, loading LOAD COUNT into the field counter 310 over paths 135, 315 resets the field counter to indicate first fields (S fields) of five field units. When AUDIO FIELD COUNT is received by die vertical sync logic 110 via patiis 123, 125, it consequendy generates LOAD1 causing the sample counter 220 to be reset to the pre-determined count value representing audio time delays. This way, video or audio data stream to be inserted or appended is synchronized to die reporduced signal data stream.

In RMW edit mode, video or audio information is read off a magnetic medium, modified and written back to the same location on die magnetic medium. Because the information read and die information to be recorded are from die same reproduced signal source, video and audio data streams are synchronized to other sources are not needed.

Therefore, SI disables die vertical sync logic 110 via path 124 in the timing generator 100.

In contrast, S2 and S3 enable die 1st sample flag logic 120 and the playback field logic 130 respectively.

The 1st sample flag logic 120 receives 1ST SAMPLE FLAG via path 118. 1ST SAMPLE FLAG is a signal having defined pulses indicative of the first digital audio sample in a field from a reproduced data stream. As described in the BACKGROUND OF THE INVENTION, audio signal is sampled at 48 kHz but tiiese samples are recorded witiύn a fixed duration of the field at a much higher frequency. Therefore, die defined pulses of 1ST SAMPLE FLAG do not typically correspond to d e beginning transitions of fields. 1ST SAMPLE FLAG causes the 1st sample flag logic 120 to couple LOAD3 to the sample counter logic 140 via path 128. LOAD3 resets the sample counter 220 with a pre- established count value from die CPU logic 105. This count value may not be the same as the pre-determined value during the record mode. In combination witii the operation of die playback field logic 130 as described above, its field information is solely synchronized to the reproduced first digital audio sample timing. In this situation, die field counter 310 is locked to PLAYBACK FIELD. The sample counter 220 is locked to the 1ST SAMPLE FLAG.

The present invention and its disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. Embodiments may be implemented in various types of digital logic families or technology including ASIC technology. Logic reduction and transformation techniques may be employed to utilize odier arrangements of gates or logic elements which are functionally equivalent to the ones described here. The scope of die invention is indicated by die following claims rather tiian the foregoing description, and all changes tiiat come within the meaning and range of equivalents thercof are intended to be embraced diercin.

Claims

WHAT IS CLAIMED IS:

1. An audio timing generator in a digital signal recording and playback apparatus, said timing generator comprising:

means for providing timing control information;

means in response to the providing means for generating a first load signal, the first load signal being responsive to a first vertical synchronous signal, the first load signal synchronizing to a sampling frequency for an analog audio signal;

means in response to die providing means for generating a second load signal, die second load signal being responsive to a playback field information signal of a reproduced signal, the playback field information signal synchronizing to a second vertical synchronous signal, the second load signal synchronizing to the sampling frequency;

means in response to the providing means for generating a third load signal, die tiiiid load signal being responsive to an incoming defined pulse indicative of die occurrence order of an audio sample within a second vertical synchronous signal period, die third load signal synchronizing to the sampling frequency;

an audio sample counter logic including an audio sample counter and a first comparison logic, the sample counter logic triggering by the sampling frequency generating tiiereby an audio sample count in response to the providing means, die first load signal, die third load signal and die first comparison logic; and

a field counter logic including a field counter and a second comparison logic, die field counter triggering by the sampling frequency generating tiiereby a field count in response to the providing means, the second load signal, and die first and second comparison logic.

2. The audio timing generator in Claim 1 wherein the providing means is a programmable means.

3. The audio timing generator in Claim 2 wherein the first load signal generating means responds to a pre-determined periods of the first vertical synchronous signal, and wherein the second load signal generating means responds to a pre-determined periods of the second vertical synchronous signal.

4. The audio timing generator in Claim 2 wherein the first load signal generating means responds to die field count of the field counter logic.

5. The audio timing generator in Claim 2 wherein the third load signal generating means responds to a defined pulse indicative of die first of die audio samples in the second vertical synchronous signal period.

6. The audio timing generator in Claim 2 wherein the audio sample counter logic further includes an OR logic, the OR logic receiving die first load signal and die third load signal as inputs, the OR logic coupling to a LOAD input of die sample counter.

7. The audio timing generator in Claim 2 wherein the first comparison logic in combination witii die programmable means generate a sample threshold pulse when die audio sample count of the sample counter reaching a pre-determined sample threshold.

8. The audio timing generator in Claim 2 wherein the second comparison logic in combination witii die programmable means generate a field tiireshold pulse when the field count of die field counter reaching a pre-determined field threshold.

9.

audio timing generator in a digital signal recording and playback apparatus, said timing generator comprising

a programmable CPU logic;

a first load signal generator responsive to die CPU logic and a first vertical synchronous signal, die first load signal synchronizing to a sampling frequency for an analog audio signal;

a second load signal generator responsive to the CPU logic and a playback field information signal of a reproduced signal, die playback field information signal synchronizing to a second vertical synchronous signal, the second load signal synchronizing to the sampling frequency;

a third load signal generator responsive to the CPU logic and an incoming defined pulse indicative of die first audio sample witiiin a second vertical synchronous signal period, the third load signal synchronizing to the sampling frequency;

an audio sample counter logic including an audio sample counter and a first comparison logic, the sample counter logic triggering by the sampling frequency generating thereby an audio sample count in response to die providing means, the first load signal, die third load signal and the first comparison logic; and

a field counter logic including a field counter and a second comparison logic, the field counter triggering by the sampling frequency generating tiiereby a field count in response to the providing means, die second load signal, and die first and second comparison logic.

10. The audio timing generator in Claim 9 wherein the first comparison logic in combination with the programmable CPU logic generate a sample threshold pulse when die audio sample count of die sample counter reaching a pre-determined sample threshold.

11. The audio timing generator in Claim 9 wherein the second comparison logic in combination witii the programmable CPU logic generate a field drreshold pulse when die field count of die field counter reaching a pre-determined field drreshold.

12. An audio timing generating method in a digital signal recording and playback apparatus, said tuning generating method comprising the steps of providing timing control information;

generating a first load signal in response to die riming control information and a pre-determined number of periods of a first vertical synchronous signal, d e first load signal synchronizing to a sampling frequency for an analog audio signal;

generating a second load signal in response to die timing control information and a playback field information signal of a reproduced signal, die playback field information signal synchronizing to a second vertical synchronous signal, the second load signal synchronizing to the sampling frequency;

generating a third load signal in response to the timing control information and an incoming defined pulse indicative of die first audio sample witiiin a second vertical synchronous signal period, die tiiird load signal synchronizing to the sampling frequency;

generating an audio sample count in response to the timing control information, the first load signal, die tiiird load signal and an audio sample counter logic, the audio sample counter logic including an audio sample counter and a first comparison logic, the sample counter logic triggering by the sampling frequency; and

generating a field count in response to the timing control information, the second load signal, die audio sample counter logic and a field counter logic, the field counter logic including a field counter and a second comparison logic, die field counter triggering by the sampling frequency;

13. The audio timing generating method in Claim 12 wherein the audio sample count generating step further includes a step of generating a sample threshold pulse when the audio sample count of die sample counter reaching a pre-determined sample threshold.

14. The audio timing generating metiiod in Claim 13 wherein the field count generating step further includes a step of generating a field direshold pulse when the field count of die field counter reaching a pre-determined field direshold.