WO1994010798A1

WO1994010798A1 - Error detection and correction circuit for video synchronization signals

Info

Publication number: WO1994010798A1
Application number: PCT/US1993/010599
Authority: WO
Inventors: Jan S. Wesolowski
Original assignee: Ampex Systems Corporation
Priority date: 1992-11-05
Filing date: 1993-11-05
Publication date: 1994-05-11

Abstract

Error detection and correction of encoded timing reference (or synchronization) signals in the incoming video signal for a digital component video input interface is provided, wherein the timing reference code words in the digital component video signal include a sequence of four words, with the last binary word in the sequence of four words forming the timing reference signal carrying three bits of sync. information accompanied by four protection bits forming a seven bit Hamming code word providing the capability of detection and correction of single bit errors in the timing reference code word, as well as the capability to detect double bit errors without the capability to correct them. The timing reference code word is processed by providing a 3-bit parity checker, a 3-bit relationship checker, and a 4-bit parity checker which provide the results thereof to decision logic for error determination and kind of error. The decision logic also provides select signals which determine the value of the corrected bits which are either the sync. bits, the protection bits or their complement, or all zeroes (on a finding of a multiple bit error).

Description

Error Detecti on and Correction Ci rcuit for Video Synchroni zati on Signal s

TECH ICAL FTEI.D

This invention relates generally to a method and apparatus for error detection and correction of riming reference signals in the incoming video signal for a digital component video input interface.

BACKGROUND ART

Standards groups have been established for providing standards by which certain electronic components interface with other equipment One such standards group is the

COR (International Radio Consultative Committee Recommendations), which issued a data protocol in its recommendation 656 in 1986 entitled "Interfaces for Digital Component Video Signals in 525-line and 625-line Television Systems". In that recommendation, it specified data format and timing relationships with the analog video signal, as part of which a video data block includes an S AV portion and an EAV portion, with a timing reference code at the beginning and end of each video block, with each timing reference code consisting of a four word sequence, with the fourth word containing information defining field 2 identification, the state of field blanking, and the state of line blanking.

SAV and EAV are "start of active video" and "end of active video". These are names used in standards in describing digital video interface. The SAV and EAV portions are sequences of digital words indicating timing in the video signal. Within the video data block, there are two subsequences marked as SAV and EAV, one is at the very beginning of the active portion of the video data and the other one is at the end of the active portion. And the SAV and EAV these are four digital words in sequence, three of them are constant fixed words, and the fourth of them is a variable word which carries the information about whether it is "start of active video" or "end of active video" and also whether the sync is within the active portion of the video field or within the so called vertical blanking. There is also other information indicating whether this particular sync belongs to field number one or field number two of the two fields, i.e., there is a two field sequence. The SAV and EAV words also carry protection bits to protect the information contained in it against noise and against transmission errors, these protection bits allowing for detecting and correcting single bit errors and detecting, without capability of correction, of two bit errors.

The assignment of bits within the fourth word is as follows:

In the recommendation F = 0 during field 1 F = 1 during field 2

V = 0 elsewhere H = 0 in SAV

V = 1 during field blanking H = 1 in EAV

Pθ, Pi, P2 and P3 are protection bits, with these bits having states dependent on the states of the bits F, V and H as shown in the following Table.

Table I

In the prior art, error detection and correction of encoded timing reference signals in an incoming data stream for a video tape recorder and reproducing system has been done using a lookup table. One code utilized is the Hamming code, and the Hamming code word is then used as an index to the lookup table. The indexed element of the table then provides a corrected or best-guess of the sync information, as well as an indication as to whether, and what kind of error has been detected. For manufacturing efficiency and convenience, modern digital circuits have begun to utilize application specific integrated circuits (ASICs) in which a large number of logic elements are contained on one chip formed from an existing catalog of a very large number of basic units. However, with ASIC utilization, it is not cost- effective to implement the lookup table inside of an ASIC. The lookup table requires several memory elements which consume a significant number of available gates and requiring a significant amount of testing to eliminate faulty devices. In accordance with an aspect of the invention, there is provided a cost-effective digital component video sync error detection and correction circuit, well suited for implementation in an ASIC.

DISCLOSURE OF TNVENTTON

The foregoing and other objects of the invention are accomplished by providing a method and apparatus for error detection and correction of encoded timing reference (or synchronization) signals in the incoming video signal for a digital component video input interface. In accordance with the invention, the timing reference code words in a digital component video signal include a sequence of four words, with the last binary word in the sequence of four words forming the timing reference signal carrying three bits of sync information. For noise immunity the three sync bits are accompanied by four protection bits forming a seven bit Hamming code word providing the capability of detection and correction of single bit errors in the timing reference code word, as well as the capability to detect double bit errors without the capability to correct them.

In accordance with the system, the last, or fourth, binary word of the incoming digital signal, which is the timing reference code word is processed by providing a 3-bit parity checker, a 3 bit relationship checker, and a 4-bit parity checker which provide the results thereof to decision logic for error determination and kind of error. A direct/complement operator circuit receives as an input three of the four protection bits (excluding the least significant bit). The H, V and F data bits indicative of the horizontal, vertical and field ID are transmitted to a data selector and to the 3 bit relationship checker and 4-bit parity checker. The least significant bit of the protection bits is provided to the direct/complement operator circuit and provides an additional, or fourth, input to the 4-bit parity checker. Parity determinations to the decision logic are even/odd; the output of the relationship checker is OK/bad; and the output of the decision logic is one of (a) no errors, (b) single bit error or (3) multiple bit error.

Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings in which like reference numerals refer to like elements in the several views.

PRTEF DESCRIPTION OF PRAWINflS

Figure 1 is a block diagram of the timing reference signal error detection and correction system according to the invention; Figures 2A and 2B, collectively referred to as Figure 2, together comprise a logic diagram of the defσrmatter timing reference signal error detection and correction system of Figure 1;

Figure 3 is a logic diagram showing the three bit relationship checker used in the system of Figure 1;

Figure 4 is a logic diagram showing the three bit parity checker used in the system of Figure 1; and

Figure 5 is a logic diagram showing the 4-bit parity checker used in the system of Figure 1.

MODE(S^ FOR CARRYING OUT THE INVENTION

Referring now to the drawings, and particularly to Figure 1, there is shown a block diagram of a digital component timing reference signal or video sync signal error detection and correction circuit, generally designated 10. The circuit 10 includes an input lead 12, and first and second input buses 14, 15. The circuit elements include a direct complement operator circuit 18, a data selector 20, a 3-bit parity checker 22, a 3 bit relationship checker 24, a 4-bit parity checker 26 and decision logic 30. The like elements in Figure 2 are enclosed in broken lines.

The last binary word in the sequence of four words forming the timing reference signal in the digital component video signal carries three bits of sync information. For noise immunity the three sync bits are accompanied by four protection bits forming a seven bit Hamming code word allowing for the detection and correction of single bit errors as well allowing for the detection of multiple bit errors without the capability to correct them. In the drawings, these bits are designated Do through Dg, with data bits D0-D3 effectively being the four protection bits (P0-P3) of the seven bit word. Data bits D4-D6 are the sync information, that is H, V and F, respectively.

Analyzing the code used for protection of the sync bits as set forth in Table I leads to the following observations or conditions:

1. The parity of the bit group consisting of sync bits F, V and H and protection bit P0 is always even.

2. The parity of protection bits PI, P2 and P3 is always even.

* 3. When protection bit P0 value is 0, the values of the protection bits P3, P2, and PI are equal to values of the signal bits F, V, and H, respectively. 4. When protection bit P0 value is 1, the protection bit P3, P2, and PI values are opposite to the values of signal bits F, V, and H, respectively.

Based on the above analysis, the error detection and correction system 10 of the present invention has been implemented in a relatively simple manner, using few gates and combinatorial logic to provide a cost-effective solution avoiding the use of look-up tables. The timing reference signal error detection and correction circuit 10 according to the invention includes: a 3-bit parity checker 22 receiving protection bits P3, P2, and Pj (D3, D2 and Di); a 4-bit parity checker 26 receiving sync bits F, V, H (bits D , D5 and D4) and Po (Do); a 3-bit equal/complementary relationship checker 24 receiving two 3-bit groups: bits P3, P2, and PI in one group, and bits F, V, and H in the other; a 3-bit circuit 18 for providing the direct or complement of bits P3, P2, and PI; a 3-bit data selector 20 for selecting either bits F, V, and H, or bits from the output of the complementing circuit 18, or three bits of zeros, for using them as the corrected sync bits; and decision logic 30 receiving outputs of both parity checkers 22 and 24 and the relationship checker 24, and producing an output for controlling the data selector 20. The decision logic 30 has also a set of outputs for reporting whether there is no error found, or a single bit error or multiple bit error has been found in the code word.

In essence the above components have inputs which, in number, are dictated by the number of bits in the word and the apportionment of such bits between sync information bits and protections bits, that is, there are n bits of sync information with n + 1 protection bits. In the instant example, n is equal to 3, thus providing 3 and 4 bit parity checkers and a 3-bit relationship checker.

By reference to Figure 1, in accordance with the instant invention, the first (or least significant) bit Do, which is the first protection bit, is treated as an even parity bit for the sync bits, F, V and H, (bits D4-D6) which conforms to the bit arrangement in Table I. This bit is provided as an input on lead 12 to the 4-bit parity checker and to the direct complement operator circuit 18, which also receives the protection bits D1-D3 on bus 15. These same protection bits D1-D3 are input, via bus 15, to the 3-bit parity checker 22 and, as a group as the first input to the 3 bit relationship checker 24.

Simultaneously, the H, V and F sync bits D4-D6 are transmitted via bus 14 to the data selector 20, and, as a group, as a second input to the 3 bit relationship checker and the 4-bit parity checker, which also receives the protection bit DO over lead 12.

The 3-bit parity checker 22 outputs an even or odd parity signal over lead 21 or 23, respectively; the 3 bit relationship checker 24 outputs an OK/bad output signal over lead 25; and the 4-bit parity checker 26 outputs an even or odd parity signal over lead 27 or 28, respectively. The decision logic 30 provides reports of states or conditions of errors over lead 33-35, respectively identified as "no errors", "single bit error" and "multiple bit error". The logic 30 also provides a command signal to data selector 30 via lead 37, with the output of the data selector 20 providing the corrected or selected bits via bus 40.

With respect to the conditions previously set forth concerning the attributes of Table

I, the 4-bit parity checker 26 (receiving protection bit P0 on lead 12 along with sync bits H, V and F on bus 14) monitors for the truth of condition 1, that is, that the parity of the bit group formed by the sync bits F, V, H and protection bit P0 is always even. The 3-bit parity checker 22, which receives the protection bits PI, P2 and P3 on bus 15, monitors for the truth of condition 2, that is, that the parity of protection bits PI, P2 and P3 is always even. The 3 bit relationship checker 24 is a form of comparator which monitors the existence of the conditions set forth in 3 and 4, that is whether the sync bit values are equal or opposite to the protection bit values (specifically protection bits PI, P2 and P3).

The relationship checker 24 is kind of a comparator but it provides two items of information, whether the first group of 3 bits (Pl, P2 and P3) and the second group of 3 bits (H, V, and F) are identical, or whether one group is inverted relative to the other, that is, one group can be the one's complement of the other. For example, when the first group is all zeros and the second group is all ones, the output response is OK; when the first group is all zeros and the second group is all zeros, the checker 24 also responds OK. The relationship checker 24 provides a signal indicating whether all bits are identical or all bits are inverted.

Referring to Figures 2A-2B, the video sync signal error detection and correction circuit 10 is shown as a logic diagram with the solid line blocks of Figure 1 depicted with discrete logic components enclosed in broken lines. For example, in Figure 2A, on the left is a broken line rectangle, designated 18, which is the direct/complement operator circuitry; and on the right is a broken line rectangle designated 20, which is the data selector. The direct/complement operator circuit 18 includes three two input XOR (exclusive OR) gates 43-45, one input of each being coupled for receiving one of the bits D1-D3, with the other input of each being commonly coupled for receiving bit DO. For the direct/complement operator circuit 18, the following Table π is the truth table:

Table π

In Table π, the first four columns represent the corresponding data bits identified as P3-P0 from Table I, with the next three columns showing the outputs of the direct/complement operator circuit 18. In essence, if DO is a "0" (zero), the output will correspond to the input bits D1-D3, that is a 101 for D1-D3 will result in a 101 output; conversely, if DO is a "1" (logical one), then the output bit in each location will be the complement of the corresponding input bit, that is, a 010 input for D1-D3 will become a 101 output Thus the data selector 20 is receiving as inputs these three outputs as a first group, as well as the sync bits D4 (H), D5 (V) and D6 (F) as a second group of inputs.

The outputs of the XOR gates 43-45 of the direct/complement operator circuit 18 appears on leads 47-49, respectively, which serve as first inputs to one input of two input NAND gates 51-53, respectively, which are parts of the data selector 20. The other inputs of NAND gates 51-53 are commonly connected to one of the select leads 37a to the data selector logic 20. The other select input 37b serves as a common input to a first input of each of three two input NAND gates 56-58, the other inputs thereof being coupled for receiving bits D4-D6 (H, V and F), these NAND gates 56-58 likewise being part of data selector 20. The data selector 20 also includes three additional two inverted input OR gates 60-62, the outputs of which are designate^ corrected bits or CB0-CB2. The first inputs to the OR gates 60-62 are provided over leads 64-66 as outputs from the NAND gates 56-58, respectively, while the other inputs are provided over leads 67-69 as outputs from the NAND gates 51-53. Data select leads 37b, 37a have four possible inputs, these being 00, 01, 11 and 10 (only two combinations of which are significant, namely 01 and 10), with the first bit position designating lead 37b and the second bit position designating lead 37a.

The select inputs 37b and 37a are also shown in Figure 2B, emanating from the decision logic 30. The inputs to the decision logic 30 include the outputs of the 3-bit relationship checker 24 (an OK signal on lead 25), the Even/Odd outputs on leads 21 and

23, respectively, from the 3-bit parity checker 22, and the Even/Odd outputs on leads 27 and 28, respectively, from the 4-bit parity checker 26. The OK output on lead 25 is provided as a first input to each of three three input NAND gates 80, 82 and 83, with the input to three additional three input NAND gates 81, 87 and 86 being provided via inverter 84. The Even output of the 3-bit parity checker 22 is provided as a second input to NAND gates 80, 81 and 82 as well as a second input to another three input NAND gate 86. The Odd output of the parity checker 22 is provided as a second input to NAND gate 83 as well as a third input to a three input NAND gate 87 and as a first input to two input NAND gate 88, the other input of which is the Odd output of the four-bit parity checker 26. This Odd output is also provided as a third input to NAND gates 82 and 86. The Even output of the 4-bit parity checker 26 is provided as a third input to NAND gate 80, a first input to NAND gate 81 a second input to NAND gate 87, and a third input to NAND gate 83.

Recapping the above, the NAND gate 80 receives its inputs from the OK output on lead 25 as well as both Even outputs of the parity checkers 22 and 26 on leads 21 and 27, respectively. On the other hand, adjacent NAND gate 81 likewise receives the same two Even inputs, along with the inverted OK signal via inverter 84. The next NAND gate 87 receives the Odd signal on lead 23 from the 3-bit parity checker 22, the Even output on lead 27 of the 4-bit parity checker 26, and the inverted OK signal via inverter 84. The next NAND gate 86 receives the inverted OK signal via inverter 84, the Even output on lead 21 from the 3-bit parity checker and the Odd output on lead 28 from the 4-bit parity checker. The NAND gate 82 receives the OK output on lead 25 from the 3-bit relationship checker

24, the Even output of the 3-bit parity checker 22 and the Odd output on lead 28 from the 4- bit parity checker 26. The NAND gate 83 receives the OK output on lead 25, the Odd output on lead 23 from the 3-bit parity checker 22 and the Even output on lead 27 from the 4-bit parity checker. The two input NAND gate 88, as previously described, receives the odd outputs on leads 23 and 28 from the 3-bit parity checker 22 and the 4-bit parity checker 26, respectively.

The decision logic 30 also includes two inverters 90, 91, three three input OR gates 92, 93, and 94, the OR gate 94 receiving the outputs of gates 81, 83 and 88. The inverter

90 receives the output of the NAND gate 80 with the output appearing on lead 33 to provide a "no errors" signal. OR gate 92 receives its inputs from NAND gates 80, 87 and 82, with the output appearing on lead 37b as a first select signal of the two bit select bus 37. OR gate 94 receives its first input from NAND gate 81, with the other two inputs being provided by NAND gates 83 and 88 to signal "multiple bit error". Inverter 91 receives its input from NAND gate 86 and outputs a second select signal on lead 37a. OR gate 93 receives its inputs from NAND gates 87, 86 and 82 to provide an output signal on lead 34 for a "single bit error" signal.

Prior to a detailed discussion of the output results of the data selector 20 and decision logic 30, reference will be had to Figures 3 through 5, wherein Figure 3 is the logic diagram showing the three bit relationship checker, Figure 4 is the logic diagram showing the three bit parity checker, and Figure 5 is the logic diagram showing the 4-bit parity checker used in the system 10 of Figure 1.

The relationship checker 24 is structured for receiving two groups of bits, each comprising three bits, the first group being three of the four protection bits D1-D3 (also referred to as P0-P3), and the second group being the sync bits D1-D3 (also referred to as the H, V and F sync bits). In accordance with the protocol of Table 1, the relationship is checked between the two groups to determine if one group bit arrangement is identical to the other group bit arrangement, or if one group bit arrangement is inverted relative to the other group bit arrangement. In either event, if true, an OK signal is outputted on lead 25. To accomplish this, three two input XOR gates 96-98 are provided, with each XOR gate receiving one bit from each group, to wit, bits Dl and D4 are the inputs to gate 96, bits D2 and D5 are the inputs to gate 97 and bits D3 and D6 are the inputs to gate 98. The outputs of the XOR gates 96-98 are provided to a three input inverted input NAND gate 99 (the gate is activated at a low level when all inputs are low) and a three input NAND gate 100, with all three outputs of the XOR gates 96-98 being inputted to both gates 99 and 100. The outputs of NAND gate 99 and NAND gate 100 are provided to a two input OR gate 101 , the output of which provide the "OK" signal on lead 25.

The following Table IE is a partial truth table for the 3-bit relationship checker, with the first six columns being the data bit level, die next three columns being the outputs of the respective XOR gate comparison, the next two columns being the results of the gates designated, with the last column being the output, a "1" indicating that an OK signal will be output.

Table m

In accordance with the above Table HI, the first six columns represent the data bit levels from Table I, with the respective results being shown thereafter. In essence, as can be seen, the 3-bit relationship checker 24 outputs an OK signal Gogic 1 level) whenever the two groups of inputs are identical, or individual bits in given locations of each group are inverted relative to one another. In the above Table m, every row provides an OK signal; however, it is to be understood that with six bits of data, there are sixty-four possible combinations. Any of the combinations not shown above will produce a Bad or "Not OK" output.

Referring now to Figure 4, the 3-bit parity checker 22 logic will be described, the checker 22 analyzing the three most significant protection bits, that is D3-D1 (or P3-P1). The logic includes an XOR gate 105 receiving as its two inputs Dl and D2; an inverter 106, receiving as its input D3; a second two input XOR gate 107, receiving as its inputs the output of XOR gate 105 and inverter 106; a third two input XOR gate 109, receiving as its inputs the output of XOR gate 105 and a non-inverting driver 108. The output of the XOR gate 107 provides the Even signal on lead 21, while the output of XOR gate 109 provides its Odd output signal on lead 23.

The following Table IV is a partial truth table for the 3-bit parity checker, with the first three columns being the data bit level for bits D3-D 1 , respectively, the next three columns being the outputs of the respective XOR gate 105, inverter 106 and non-inverting amplifier 108, with the next two columns being the Even/Odd result of the gates designated, that is, the outputs, with a "1" in either of the last two columns indicating the respective Even or Odd output of the parity checker 22.

Table IV

In accordance with the above Table IV, the first three columns represent the data bit levels from the first four rows of Table I (the next four rows being repetitive of the first four), with the respective results being shown thereafter. Only those combinations are shown which result in an Even parity, it being understood that any other combinations of bits D3-D1 will result in an Odd parity. In essence, as can be seen, the 3-bit parity checker 21 outputs an Even signal (logic 1 level) for all combinations of bits D3-D1 consistent with the data bits of Table I, it being understood that any variation therefrom will result in the Odd output going true, with the Even output going false.

Referring now to Figure 5, the 4-bit parity checker 26 logic will be described, die checker 26 monitoring that the parity of the four bit group of protection bit P0 (DO) plus the three sync bits D6-D4 (F, V and H sync bits) is even. The logic includes an XOR gate 112 receiving as its two inputs D4 and D5; a second two input XOR gate 113, receiving as its inputs D6 and DO; a third two input XOR gate 114, receiving as its inputs the outputs of XOR gates 112 and 113; an inverter 115 receiving as its input the output of XOR gate 114; and a non-inverting driver 116 likewise receiving the output of XOR gate 114. The output of the inverter 115 provides the Even signal on lead 27, while the output of non-inverting amplifier 116 provides the Odd output signal on lead 28.

The following Table V is a partial truth table for the 4-bit parity checker, with the first four columns being the data bit level for D4-D6 and DO, respectively, die next two columns being the outputs of the respective XOR gates 112 and 113, the next column being the output of XOR gate 114, and the next two columns being the outputs of inverter 115 and non-inverting amplifier 116, these last two columns being the Even/Odd output result of the 4-bit parity checker 26, that is, with a "1" in either of the last two columns indicating the respective Even or Odd output.

Table V

In accordance with the above Table V, the first four columns represent the data bit levels from Table I, the first three columns being the sync bits (F, V and H) with the fourth column being the least significant protection bit P0 or DO, the four bits together forming a group for parity check, with the respective logic gate results being shown thereafter. In essence, as can be seen, the 4-bit parity checker 26 outputs an Even signal (logic 1 level) for all combinations of bits D4-D6 consistent with even parity as represented by the DO bit associated therewith, it being understood that any variation therefrom will result in the Odd output going true, with the Even output going false.

Returning now to Figures 2A and 2B, with the direct/complement operator results of truth Table I, along with the parity and bit group relationships as determined by the truth Tables π though IV, the decision logic 30 operates according to the following truth table, that is Table VI:

2=Eil 4 Biι Relationship Parity Parity Checker Bits

(1) Even Even OK (2) Even Even Bad (3) Odd Even Bad (4) Even Odd Bad (5) Even Odd OK (6) Odd Even OK (7) Odd Odd Don't care

Table VI

The above table has the leftmost column listed with numerical designations in parentheses for purposes of explanation. In cases (2), (6) and (7), which are "multiple bit errors" states, the corrected bit outputs, identified as CB0-CB2 in Figures 1 and 2 on output bus 40, will be all zeros. In cases (1), (3) and (5), die corrected bit outputs will be the sync bits F, V, H, which correspond to bits D4-D6, inclusive. In cases (2) and (4), die corrected bits at the output will correspond to the three most significant protection bits PI, P2 and P3, which correspond to bits D 1 -D3, respectively.

By reference to Figure 2A, as previously described, the inputs are formed as one of two groups - either the sync bits or the protection bits pass through the data selector 20 as the corrected bits, with the protection bits passed dirough to the output either direcdy, or complemented, due to die direct/complement operator 18. This selection is, in turn, determined by die state of the logic levels on the two data select leads 37a, 37b. The logic levels on these two lines are, in turn, determined by the outputs of NAND gate 92 and inverter 91 (See Figure 2B). These outputs, in turn are determined by die outputs of the relationship checker 24, and die two parity checkers 22 and 26. As stated above, if the multiple bit error flag arises, the select leads 37a, 37b are at logic levels which sets all of the outputs of NAND gates 56-58 and 51-52 to a level to insure tiiat the outputs of NAND gates 60-62 will be all zeros.

In accordance with die present invention, there has been shown and described a metiiod and apparatus for providing error detection and correction of encoded timing reference signals in an incoming data stream for a video tape recorder and reproducing system wherein the incoming data stream includes a word having sync bits combined with protection bits in accordance with a specified code or protocol, in the specific example, a seven bit word witii three bits of sync information and four protection bits forming a seven bit Hamming code word. The circuitry employs simple logic gates to accomplish the result without lookup tables in a circuit configuration which is easily implementable on an ASIC. While there has been shown and described a preferred embodiment, it is to be understood that various other adaptations and implementations may be made within the spirit and scope of die invention.

Claims

What is claimed is:

1. Apparatus for error detection and correction of encoded timing reference signals in an incoming data stream for a video tape recorder and reproducing system wherein the incoming data stream includes a word having n sync bits combined with n+1 protection bits for the sync bits, the combination comprising:

an n-bit parity checker for receiving n number of the protection bits;

an n+1 bit parity checker receiving, as a group, the remaining protection bit and die n sync bits for determining the parity thereof;

an n-bit relationship checker receiving two n-bit groups, a first group comprising n number of said protection bits and a second group comprising said sync bits;

an n-bit complementing circuit for providing an output which is identical to the protection bits input to said n-bit parity checker, or the complement thereof;

a data selector for selecting eitiier said sync bits or bits from the output of said complementing circuit; and

decision logic receiving the output results of both parity checkers and the relationship checker, and producing a select signal to said data selector for providing an output of corrected bits therefrom in response to said results.

2. The apparatus according to claim 1 wherein said decision logic includes means for output of errors in said incoming data stream.

3. The apparatus according to claim 2 wherein said output of errors is determined by errors in said sync bits.

4. The apparatus according to claim 3 wherein said select signal to said decision logic provides an output of all zeroes on a finding of multiple bit errors.

5. The apparatus according to claim 1 wherein n equals 3.

6. The apparatus according to claim 5 wherein said incoming data stream includes tiiree sync bits accompanied by four protection bits for forming a seven bit Hamming code word.

* 7. The apparatus according to claim 1 where n equals 3 and wherein said n-bit parity checker receives the three most significant bits of four protection bits.

8. The apparatus according to claim 7 wherein said fourth protection bit is the least significant bit

9. The apparatus according to claim 7 wherein said sync bits are bits for vertical, horizontal and frame.

10. A method for error detection and correction of encoded timing reference signals in an incoming data stream for a video tape recorder and reproducing system wherein the incoming data stream includes a word having n sync bits combined with n+1 protection bits for the sync bits, said metiiod comprising:

checking the parity of n number of the protection bits and providing a first output signal;

checking the parity, as a group, of the remaining protection bit and die sync bits and providing a second output signal;

checking the relationship between said n number of protection bits, as a group, with said sync bits, as a group, and providing a third output signal;

providing a complementing circuit for providing a data bit output which is identical to the protection bits input to said n-bit parity checker, or the complement thereof;

providing a data selector for selecting either said sync bits or said data bit output of said complementing circuit; and

providing decision logic for receiving said first, second and third output signals for producing a select signal to said data selector for providing an output of corrected bits therefrom in response to said output signals.

11. The method according to claim 10 wherein said decision logic further includes outputting signals indicative of errors in said incoming data stream.

12. The method according to claim 10 wherein n equals 3.

13. The method according to claim 10 wherein said incoming data stream includes three sync bits accompanied by four protection bits for forming a seven bit Hamming code word.

14. The method according to claim 10 where n equals 3 and wherein said step of checking die parity of n number of the protection bits includes checking the parity of the three most significant bits of four protection bits.